JP6316751B2 - 変換器 - Google Patents

変換器 Download PDF

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Publication number
JP6316751B2
JP6316751B2 JP2014543364A JP2014543364A JP6316751B2 JP 6316751 B2 JP6316751 B2 JP 6316751B2 JP 2014543364 A JP2014543364 A JP 2014543364A JP 2014543364 A JP2014543364 A JP 2014543364A JP 6316751 B2 JP6316751 B2 JP 6316751B2
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JP
Japan
Prior art keywords
signal
output
clock signal
input
period
Prior art date
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Active
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JP2014543364A
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English (en)
Japanese (ja)
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JPWO2014065408A1 (ja
Inventor
彰 安田
彰 安田
淳一 岡村
淳一 岡村
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Trigence Semiconductor Inc
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Trigence Semiconductor Inc
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Publication of JPWO2014065408A1 publication Critical patent/JPWO2014065408A1/ja
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
    • H03M3/3283—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being in the time domain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
JP2014543364A 2012-10-25 2013-10-25 変換器 Active JP6316751B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012235910 2012-10-25
JP2012235910 2012-10-25
PCT/JP2013/078998 WO2014065408A1 (ja) 2012-10-25 2013-10-25 変換器

Publications (2)

Publication Number Publication Date
JPWO2014065408A1 JPWO2014065408A1 (ja) 2016-09-08
JP6316751B2 true JP6316751B2 (ja) 2018-04-25

Family

ID=50544779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014543364A Active JP6316751B2 (ja) 2012-10-25 2013-10-25 変換器

Country Status (7)

Country Link
US (1) US9362943B2 (cg-RX-API-DMAC7.html)
EP (1) EP2913931A4 (cg-RX-API-DMAC7.html)
JP (1) JP6316751B2 (cg-RX-API-DMAC7.html)
KR (1) KR20150077420A (cg-RX-API-DMAC7.html)
CN (1) CN104718704A (cg-RX-API-DMAC7.html)
IN (1) IN2015DN03872A (cg-RX-API-DMAC7.html)
WO (1) WO2014065408A1 (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104581589B (zh) * 2014-12-31 2018-01-02 苏州上声电子有限公司 基于三态编码的通道状态选取方法和装置
US9397677B1 (en) * 2015-11-02 2016-07-19 Keysight Technologies, Inc. Method and system for digital-to-analog converter performance measurement using equivalent-time sampler
CN105761691A (zh) * 2016-05-04 2016-07-13 深圳市华星光电技术有限公司 栅极扫描线驱动方法、驱动模块及tft-lcd显示面板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471209A (en) * 1994-03-03 1995-11-28 Echelon Corporation Sigma-delta converter having a digital logic gate core
DE60113442T2 (de) * 2001-10-31 2006-01-26 Freescale Semiconductors, Inc., Austin Inkrementaler Delta Analog-Digital-Wandler
US7146144B2 (en) * 2003-10-20 2006-12-05 Northrop Grumman Corporation Frequency agile exciter
JP4687510B2 (ja) * 2006-03-08 2011-05-25 日本電気株式会社 移動通信端末における信号処理システム及びその方法並びにそれを用いた移動通信端末
JP4660778B2 (ja) * 2006-07-27 2011-03-30 国立大学法人 名古屋工業大学 Ｐｗｍ信号生成器、ｐｗｍ信号生成装置およびデジタルアンプ
KR101055250B1 (ko) * 2006-08-23 2011-08-09 아사히 가세이 일렉트로닉스 가부시끼가이샤 델타 시그마 변조기
US7619487B2 (en) * 2007-09-14 2009-11-17 Infineon Technologies Ag Polar modulation without analog filtering
EP2063534B1 (en) * 2007-11-23 2012-02-01 STMicroelectronics Srl Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process
JP2010041478A (ja) * 2008-08-06 2010-02-18 Mitsubishi Electric Engineering Co Ltd パルス幅変調方式のデジタル／アナログ変換器
JP5365437B2 (ja) * 2009-09-11 2013-12-11 株式会社リコー 画像読取装置および画像形成装置
KR101634359B1 (ko) * 2009-09-23 2016-06-28 삼성전자주식회사 클럭 신호의 변화를 통하여 이득을 제어하는 아날로그-디지털 컨버터 및 이를 포함하는 이미지 센서
US8179174B2 (en) * 2010-06-15 2012-05-15 Mstar Semiconductor, Inc. Fast phase locking system for automatically calibrated fractional-N PLL

Also Published As

Publication number Publication date
IN2015DN03872A (cg-RX-API-DMAC7.html) 2015-10-02
WO2014065408A1 (ja) 2014-05-01
EP2913931A1 (en) 2015-09-02
EP2913931A4 (en) 2016-08-03
US9362943B2 (en) 2016-06-07
CN104718704A (zh) 2015-06-17
US20150236713A1 (en) 2015-08-20
JPWO2014065408A1 (ja) 2016-09-08
KR20150077420A (ko) 2015-07-07

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