IN2015DN03872A - - Google Patents

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Publication number
IN2015DN03872A
IN2015DN03872A IN3872DEN2015A IN2015DN03872A IN 2015DN03872 A IN2015DN03872 A IN 2015DN03872A IN 3872DEN2015 A IN3872DEN2015 A IN 3872DEN2015A IN 2015DN03872 A IN2015DN03872 A IN 2015DN03872A
Authority
IN
India
Prior art keywords
clock signal
signal
input unit
unit
input
Prior art date
Application number
Inventor
Akira Yasuda
Jun Ichi Okamura
Original Assignee
Trigence Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trigence Semiconductor Inc filed Critical Trigence Semiconductor Inc
Publication of IN2015DN03872A publication Critical patent/IN2015DN03872A/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
    • H03M3/3283—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being in the time domain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Provided is a data converter which is provided with a clock signal input unit which inputs a clock signal an input unit which inputs an input signal a sampling unit which in response to the clock signal inputted to the clock signal input unit performs sampling of the input signal inputted to the input unit and a signal processing unit which performs signal processing in accordance with the sampling period and outputs an output signal wherein if the period of the clock signal inputted to the clock signal input unit becomes longer the output signals outputted by the signal processing unit are reduced.
IN3872DEN2015 2012-10-25 2013-10-25 IN2015DN03872A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012235910 2012-10-25
PCT/JP2013/078998 WO2014065408A1 (en) 2012-10-25 2013-10-25 Converter

Publications (1)

Publication Number Publication Date
IN2015DN03872A true IN2015DN03872A (en) 2015-10-02

Family

ID=50544779

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3872DEN2015 IN2015DN03872A (en) 2012-10-25 2013-10-25

Country Status (7)

Country Link
US (1) US9362943B2 (en)
EP (1) EP2913931A4 (en)
JP (1) JP6316751B2 (en)
KR (1) KR20150077420A (en)
CN (1) CN104718704A (en)
IN (1) IN2015DN03872A (en)
WO (1) WO2014065408A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104581589B (en) * 2014-12-31 2018-01-02 苏州上声电子有限公司 Channel status choosing method and device based on tri-state coding
US9397677B1 (en) * 2015-11-02 2016-07-19 Keysight Technologies, Inc. Method and system for digital-to-analog converter performance measurement using equivalent-time sampler
CN105761691A (en) * 2016-05-04 2016-07-13 深圳市华星光电技术有限公司 Grid scanning line driving method, driving module and TFT-LCD panel

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471209A (en) * 1994-03-03 1995-11-28 Echelon Corporation Sigma-delta converter having a digital logic gate core
EP1317068B1 (en) * 2001-10-31 2005-09-14 Freescale Semiconductor, Inc. Incremental-delta analogue to digital conversion
US7146144B2 (en) * 2003-10-20 2006-12-05 Northrop Grumman Corporation Frequency agile exciter
JP4687510B2 (en) * 2006-03-08 2011-05-25 日本電気株式会社 Signal processing system and method in mobile communication terminal and mobile communication terminal using the same
US8116368B2 (en) * 2006-07-27 2012-02-14 National University Corporation Nagoya Institute Of Technology PWM signal generator, PWM signal generating device, and digital amplifier
JP4549420B2 (en) * 2006-08-23 2010-09-22 旭化成エレクトロニクス株式会社 Delta-sigma modulator
US7619487B2 (en) * 2007-09-14 2009-11-17 Infineon Technologies Ag Polar modulation without analog filtering
EP2063534B1 (en) * 2007-11-23 2012-02-01 STMicroelectronics Srl Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process
JP2010041478A (en) * 2008-08-06 2010-02-18 Mitsubishi Electric Engineering Co Ltd Pulse width modulation system digital/analog converter
JP5365437B2 (en) * 2009-09-11 2013-12-11 株式会社リコー Image reading apparatus and image forming apparatus
KR101634359B1 (en) 2009-09-23 2016-06-28 삼성전자주식회사 The analog-digital converter controlling gain by changing clock signal, image sensor including the same
US8179174B2 (en) * 2010-06-15 2012-05-15 Mstar Semiconductor, Inc. Fast phase locking system for automatically calibrated fractional-N PLL

Also Published As

Publication number Publication date
EP2913931A1 (en) 2015-09-02
JPWO2014065408A1 (en) 2016-09-08
KR20150077420A (en) 2015-07-07
US9362943B2 (en) 2016-06-07
WO2014065408A1 (en) 2014-05-01
JP6316751B2 (en) 2018-04-25
CN104718704A (en) 2015-06-17
EP2913931A4 (en) 2016-08-03
US20150236713A1 (en) 2015-08-20

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