JP6225674B2 - 半導体装置および通信インタフェース回路 - Google Patents

半導体装置および通信インタフェース回路 Download PDF

Info

Publication number
JP6225674B2
JP6225674B2 JP2013249382A JP2013249382A JP6225674B2 JP 6225674 B2 JP6225674 B2 JP 6225674B2 JP 2013249382 A JP2013249382 A JP 2013249382A JP 2013249382 A JP2013249382 A JP 2013249382A JP 6225674 B2 JP6225674 B2 JP 6225674B2
Authority
JP
Japan
Prior art keywords
register
fuse
input
selector
potential level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013249382A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015106691A (ja
JP2015106691A5 (enExample
Inventor
鈴木　大輔
大輔 鈴木
雅幸 山口
雅幸 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2013249382A priority Critical patent/JP6225674B2/ja
Priority to US14/550,725 priority patent/US9240788B2/en
Publication of JP2015106691A publication Critical patent/JP2015106691A/ja
Publication of JP2015106691A5 publication Critical patent/JP2015106691A5/ja
Application granted granted Critical
Publication of JP6225674B2 publication Critical patent/JP6225674B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2013249382A 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路 Active JP6225674B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013249382A JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路
US14/550,725 US9240788B2 (en) 2013-12-02 2014-11-21 Semiconductor device and communication interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013249382A JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路

Publications (3)

Publication Number Publication Date
JP2015106691A JP2015106691A (ja) 2015-06-08
JP2015106691A5 JP2015106691A5 (enExample) 2016-07-21
JP6225674B2 true JP6225674B2 (ja) 2017-11-08

Family

ID=53266174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013249382A Active JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路

Country Status (2)

Country Link
US (1) US9240788B2 (enExample)
JP (1) JP6225674B2 (enExample)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151623A (en) 1985-03-29 1992-09-29 Advanced Micro Devices, Inc. Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix
JPS61262026A (ja) * 1985-05-15 1986-11-20 三菱電機株式会社 無停電電源装置の短絡保護方式
DE19739246A1 (de) * 1997-09-08 1999-03-11 Siemens Ag Schaltungsanordnung und Verfahren zum Überlastschutz für ein Schaltelement
JP2003249562A (ja) * 2002-02-25 2003-09-05 Seiko Epson Corp 特性調整回路及びそれを用いた半導体装置
KR101165027B1 (ko) * 2004-06-30 2012-07-13 삼성전자주식회사 반도체 메모리 장치에서의 리던던시 프로그램 회로
US7562272B2 (en) * 2005-10-06 2009-07-14 International Business Machines Corporation Apparatus and method for using eFuses to store PLL configuration data
KR100821585B1 (ko) * 2007-03-12 2008-04-15 주식회사 하이닉스반도체 반도체 메모리 장치의 온 다이 터미네이션 회로
JP5422259B2 (ja) * 2009-05-18 2014-02-19 新日本無線株式会社 トリミング回路

Also Published As

Publication number Publication date
US9240788B2 (en) 2016-01-19
JP2015106691A (ja) 2015-06-08
US20150155872A1 (en) 2015-06-04

Similar Documents

Publication Publication Date Title
JP4940013B2 (ja) 半導体装置に対する同時動作信号ノイズ見積り方法、およびプログラム
KR101981891B1 (ko) 반도체 디바이스의 셀 레이아웃
CN1864332B (zh) 可配置的逻辑电路装置
JP2006518095A (ja) 製造された集積回路の設計ミスを修正するための予備のセル構造
US20060279324A1 (en) Mask-programmable logic device with programmable input/output ports
JP4098240B2 (ja) 出力信号縁が柔軟に順序付けられたロックされないデジタルシーケンサ回路
WO2010135477A1 (en) A programmable integrated circuit having built in test circuit
US6822474B2 (en) On chip logic analyzer debug bus
JP6225674B2 (ja) 半導体装置および通信インタフェース回路
JP6540889B2 (ja) 再構成可能回路
US10176865B2 (en) Programmable decoupling capacitance of configurable logic circuitry and method of operating same
US7131033B1 (en) Substrate configurable JTAG ID scheme
US20050157593A1 (en) Apparatus for identification of locations of a circuit within an integrated circuit having low speed performance
US20070183180A1 (en) Option circuits and option methods of semiconductor chips
KR101161809B1 (ko) 고속 동작용 칩을 테스트할 수 있는 번인보드와 그를 이용한 번인 테스트 장치 및 그 방법
CN104090226A (zh) 测试芯片管脚连通性的电路
US9582388B2 (en) Dynamic multi-purpose external access points connected to core interfaces within a system on chip (SOC)
US8020137B2 (en) Structure for an on-demand power supply current modification system for an integrated circuit
CN1770448B (zh) 半导体集成电路和其设计方法
US8694948B2 (en) Reconfigurable circuit generation device, method, and program
US10879903B2 (en) Distributed I/O interfaces in modularized integrated circuit devices
JP4385136B2 (ja) 集積回路設定システム及びその設定方法
Lepercq et al. An interconnection network for a novel reconfigurable circuit board
JP2013055199A (ja) 半導体装置
CN106709154A (zh) 一种集成电路工程修改时减少改动层数的方法

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20150611

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160531

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160531

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170309

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170314

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170424

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170606

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170725

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170912

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170925

R150 Certificate of patent or registration of utility model

Ref document number: 6225674

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150