JP2015106691A5 - - Google Patents

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Publication number
JP2015106691A5
JP2015106691A5 JP2013249382A JP2013249382A JP2015106691A5 JP 2015106691 A5 JP2015106691 A5 JP 2015106691A5 JP 2013249382 A JP2013249382 A JP 2013249382A JP 2013249382 A JP2013249382 A JP 2013249382A JP 2015106691 A5 JP2015106691 A5 JP 2015106691A5
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JP
Japan
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potential level
register
signal
output node
setting unit
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JP2013249382A
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English (en)
Japanese (ja)
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JP2015106691A (ja
JP6225674B2 (ja
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Priority to JP2013249382A priority Critical patent/JP6225674B2/ja
Priority claimed from JP2013249382A external-priority patent/JP6225674B2/ja
Priority to US14/550,725 priority patent/US9240788B2/en
Publication of JP2015106691A publication Critical patent/JP2015106691A/ja
Publication of JP2015106691A5 publication Critical patent/JP2015106691A5/ja
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Publication of JP6225674B2 publication Critical patent/JP6225674B2/ja
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JP2013249382A 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路 Active JP6225674B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013249382A JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路
US14/550,725 US9240788B2 (en) 2013-12-02 2014-11-21 Semiconductor device and communication interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013249382A JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路

Publications (3)

Publication Number Publication Date
JP2015106691A JP2015106691A (ja) 2015-06-08
JP2015106691A5 true JP2015106691A5 (enExample) 2016-07-21
JP6225674B2 JP6225674B2 (ja) 2017-11-08

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ID=53266174

Family Applications (1)

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JP2013249382A Active JP6225674B2 (ja) 2013-12-02 2013-12-02 半導体装置および通信インタフェース回路

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US (1) US9240788B2 (enExample)
JP (1) JP6225674B2 (enExample)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151623A (en) 1985-03-29 1992-09-29 Advanced Micro Devices, Inc. Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix
JPS61262026A (ja) * 1985-05-15 1986-11-20 三菱電機株式会社 無停電電源装置の短絡保護方式
DE19739246A1 (de) * 1997-09-08 1999-03-11 Siemens Ag Schaltungsanordnung und Verfahren zum Überlastschutz für ein Schaltelement
JP2003249562A (ja) * 2002-02-25 2003-09-05 Seiko Epson Corp 特性調整回路及びそれを用いた半導体装置
KR101165027B1 (ko) * 2004-06-30 2012-07-13 삼성전자주식회사 반도체 메모리 장치에서의 리던던시 프로그램 회로
US7562272B2 (en) * 2005-10-06 2009-07-14 International Business Machines Corporation Apparatus and method for using eFuses to store PLL configuration data
KR100821585B1 (ko) * 2007-03-12 2008-04-15 주식회사 하이닉스반도체 반도체 메모리 장치의 온 다이 터미네이션 회로
JP5422259B2 (ja) * 2009-05-18 2014-02-19 新日本無線株式会社 トリミング回路

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