JP6224994B2 - 情報処理装置およびその制御方法 - Google Patents

情報処理装置およびその制御方法 Download PDF

Info

Publication number
JP6224994B2
JP6224994B2 JP2013228754A JP2013228754A JP6224994B2 JP 6224994 B2 JP6224994 B2 JP 6224994B2 JP 2013228754 A JP2013228754 A JP 2013228754A JP 2013228754 A JP2013228754 A JP 2013228754A JP 6224994 B2 JP6224994 B2 JP 6224994B2
Authority
JP
Japan
Prior art keywords
reset operation
circuit block
power consumption
information processing
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013228754A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015088129A5 (enExample
JP2015088129A (ja
Inventor
和也 加山
和也 加山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013228754A priority Critical patent/JP6224994B2/ja
Priority to US14/523,079 priority patent/US9537484B2/en
Publication of JP2015088129A publication Critical patent/JP2015088129A/ja
Publication of JP2015088129A5 publication Critical patent/JP2015088129A5/ja
Application granted granted Critical
Publication of JP6224994B2 publication Critical patent/JP6224994B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2013228754A 2013-11-01 2013-11-01 情報処理装置およびその制御方法 Active JP6224994B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013228754A JP6224994B2 (ja) 2013-11-01 2013-11-01 情報処理装置およびその制御方法
US14/523,079 US9537484B2 (en) 2013-11-01 2014-10-24 Semiconductor device and method of controlling the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013228754A JP6224994B2 (ja) 2013-11-01 2013-11-01 情報処理装置およびその制御方法

Publications (3)

Publication Number Publication Date
JP2015088129A JP2015088129A (ja) 2015-05-07
JP2015088129A5 JP2015088129A5 (enExample) 2016-09-15
JP6224994B2 true JP6224994B2 (ja) 2017-11-01

Family

ID=53006597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013228754A Active JP6224994B2 (ja) 2013-11-01 2013-11-01 情報処理装置およびその制御方法

Country Status (2)

Country Link
US (1) US9537484B2 (enExample)
JP (1) JP6224994B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10620247B2 (en) * 2017-09-27 2020-04-14 Quanta Computer Inc. System and method to detect capacitance of a power supply unit
JP7152214B2 (ja) * 2018-02-16 2022-10-12 株式会社メガチップス 情報処理システム、情報処理装置及び情報処理システムの動作方法
WO2019159547A1 (ja) * 2018-02-16 2019-08-22 株式会社メガチップス 情報処理システム、サーバ装置、情報処理装置、動作制御装置及び情報処理システムの動作方法
JP2021149140A (ja) * 2020-03-16 2021-09-27 ファナック株式会社 電子装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414979A (en) * 1981-02-23 1983-11-15 Telectronics Pty. Ltd. Monitorable bone growth stimulator
US5323067A (en) * 1993-04-14 1994-06-21 National Semiconductor Corporation Self-disabling power-up detection circuit
EP0723331B1 (en) * 1995-01-17 2003-05-07 Vlt Corporation Control of stored magnetic energy in power converter transformers
US6473852B1 (en) * 1998-10-30 2002-10-29 Fairchild Semiconductor Corporation Method and circuit for performing automatic power on reset of an integrated circuit
JP2001101764A (ja) * 1999-09-28 2001-04-13 Internatl Business Mach Corp <Ibm> 消費電力低減方法、消費電力低減回路、制御回路およびハード・ディスク・ドライブ装置
US6690220B2 (en) * 2000-06-30 2004-02-10 Matsushita Electric Industrial Co., Ltd. Reset circuit of semiconductor circuit
JP3703706B2 (ja) * 2000-10-18 2005-10-05 富士通株式会社 リセット回路およびリセット回路を有する半導体装置
JP3437174B2 (ja) 2001-04-12 2003-08-18 沖電気工業株式会社 省電力化集積回路および省電力化集積回路の制御方法
US7667506B2 (en) * 2007-03-29 2010-02-23 Mitutoyo Corporation Customizable power-on reset circuit based on critical circuit counterparts
JP2009054031A (ja) * 2007-08-28 2009-03-12 Toshiba Corp リセット制御装置
JP2011065529A (ja) 2009-09-18 2011-03-31 Renesas Electronics Corp 半導体集積装置およびその制御方法
US8754679B2 (en) * 2009-09-29 2014-06-17 Texas Instruments Incorporated Low current power-on reset circuit and method
JP5333311B2 (ja) * 2010-03-26 2013-11-06 ソニー株式会社 不揮発性記憶装置
JP5936415B2 (ja) * 2012-03-29 2016-06-22 キヤノン株式会社 半導体集積回路、情報処理装置および制御方法
JP2014032724A (ja) * 2012-08-03 2014-02-20 Sharp Corp 半導体記憶装置
JP6110696B2 (ja) * 2013-03-14 2017-04-05 キヤノン株式会社 集積回路及びその制御方法

Also Published As

Publication number Publication date
US20150123719A1 (en) 2015-05-07
US9537484B2 (en) 2017-01-03
JP2015088129A (ja) 2015-05-07

Similar Documents

Publication Publication Date Title
US12422913B1 (en) Power management for a graphics processing unit or other circuit
JP6215630B2 (ja) データトランザクションによって電力供給を制御するＳｏＣ、及びその動作方法
JP6113538B2 (ja) 制御装置、制御方法、プログラムおよび半導体装置
US9405350B2 (en) Memory control device, semiconductor device, and system board
JP5024389B2 (ja) 半導体集積回路
US20150286257A1 (en) Energy efficiency aware thermal management in a multi-processor system on a chip
US10928882B2 (en) Low cost, low power high performance SMP/ASMP multiple-processor system
JP2015528160A (ja) ポータブルコンピューティングデバイスにおける適応型熱管理のためのシステムおよび方法
KR20120095901A (ko) 전력 관리를 위한 클럭 턴온 기법
JP2004220610A (ja) データ処理性能制御方法及び装置
JP6103783B2 (ja) 電力制御装置
JP6224994B2 (ja) 情報処理装置およびその制御方法
KR20160085892A (ko) 칩상의 시스템에서의 동작 주파수 조정 및 작업부하 스케쥴링을 위한 시스템 및 방법
KR102164099B1 (ko) 시스템 온 칩, 이의 작동 방법, 및 이를 포함하는 장치
BR112017007876B1 (pt) Sistema de processamento de processador múltiplo, aparelho, método de comutação de uma pluralidade de processadores entre um modo de processamento múltiplo simétrico (smp) e um modo de processamento múltiplo assimétrico (asmp), e método de processamento em um sistema de processador múltiplo que tem uma pluralidade de processadores
JP6240225B2 (ja) ポータブルコンピューティングデバイスにおける電圧モードの温度駆動型選択のためのシステムおよび方法
JP5936415B2 (ja) 半導体集積回路、情報処理装置および制御方法
KR20180078558A (ko) 시스템 온 칩의 구동 방법, 이를 수행하는 시스템 온 칩 및 이를 포함하는 전자 시스템
TWI470410B (zh) 電子系統及其電源管理方法
CN120344938A (zh) 用于改善计算设备的功率状态转变延迟的技术
US11163345B2 (en) Electronic device to control temperature and computing performance of at least one processing unit and system and method thereof
US9389914B2 (en) Information processing apparatus and control method thereof
CN1332287C (zh) 电源管理的频率电压装置及频率电压控制的方法
US8122273B2 (en) Structure and method to optimize computational efficiency in low-power environments
JP2005092867A (ja) 回路を制御するための方法および装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160726

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160726

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170414

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170424

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170531

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170908

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171006

R151 Written notification of patent or utility model registration

Ref document number: 6224994

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151