JP6224844B2 - 導電層ルーティング - Google Patents

導電層ルーティング Download PDF

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Publication number
JP6224844B2
JP6224844B2 JP2016541713A JP2016541713A JP6224844B2 JP 6224844 B2 JP6224844 B2 JP 6224844B2 JP 2016541713 A JP2016541713 A JP 2016541713A JP 2016541713 A JP2016541713 A JP 2016541713A JP 6224844 B2 JP6224844 B2 JP 6224844B2
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Japan
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contacts
type
active
layer
exposed
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Expired - Fee Related
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JP2016541713A
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English (en)
Japanese (ja)
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JP2017501581A5 (enExample
JP2017501581A (ja
Inventor
スタンリー・スンチュル・ソン
カーン・リム
ジョンゼ・ワン
ジェフリー・ジュンハオ・シュ
シャンドン・チェン
チョ・フェイ・イェプ
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クアルコム，インコーポレイテッド
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Publication of JP2017501581A5 publication Critical patent/JP2017501581A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2016541713A 2014-01-03 2014-11-13 導電層ルーティング Expired - Fee Related JP6224844B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461923482P 2014-01-03 2014-01-03
US61/923,482 2014-01-03
US14/283,162 US9508589B2 (en) 2014-01-03 2014-05-20 Conductive layer routing
US14/283,162 2014-05-20
PCT/US2014/065529 WO2015102753A1 (en) 2014-01-03 2014-11-13 Conductive layer routing

Publications (3)

Publication Number Publication Date
JP2017501581A JP2017501581A (ja) 2017-01-12
JP2017501581A5 JP2017501581A5 (enExample) 2017-02-23
JP6224844B2 true JP6224844B2 (ja) 2017-11-01

Family

ID=52102992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016541713A Expired - Fee Related JP6224844B2 (ja) 2014-01-03 2014-11-13 導電層ルーティング

Country Status (5)

Country Link
US (1) US9508589B2 (enExample)
EP (1) EP3090444B1 (enExample)
JP (1) JP6224844B2 (enExample)
CN (1) CN105874586A (enExample)
WO (1) WO2015102753A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9455226B2 (en) 2013-02-01 2016-09-27 Mediatek Inc. Semiconductor device allowing metal layer routing formed directly under metal pad
US9536833B2 (en) 2013-02-01 2017-01-03 Mediatek Inc. Semiconductor device allowing metal layer routing formed directly under metal pad
EP3131118B1 (en) * 2015-08-12 2019-04-17 MediaTek Inc. Semiconductor device allowing metal layer routing formed directly under metal pad

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117342A (ja) * 1987-10-30 1989-05-10 Oki Electric Ind Co Ltd コンタクトホールの形成方法
JPH0982799A (ja) * 1995-09-13 1997-03-28 Hitachi Ltd 配線基板およびその製造方法
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US20070196983A1 (en) * 2006-02-22 2007-08-23 Hynix Semiconductor Inc. Method of manufacturing non-volatile memory device
WO2007116515A1 (ja) * 2006-04-07 2007-10-18 Philtech Inc. 半導体装置及びその製造方法、ドライエッチング方法、並びに配線材料の作製方法
KR100811442B1 (ko) 2007-02-09 2008-03-07 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US7791109B2 (en) 2007-03-29 2010-09-07 International Business Machines Corporation Metal silicide alloy local interconnect
JP2008270256A (ja) * 2007-04-16 2008-11-06 Denso Corp 半導体装置およびその製造方法
US8907316B2 (en) 2008-11-07 2014-12-09 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
US8124525B1 (en) 2010-10-27 2012-02-28 International Business Machines Corporation Method of forming self-aligned local interconnect and structure formed thereby
DE102011004323B4 (de) 2011-02-17 2016-02-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit selbstjustierten Kontaktelementen und Verfahren zu seiner Herstellung
US8765599B2 (en) * 2012-01-06 2014-07-01 GlobalFoundries, Inc. Semiconductor devices having dielectric caps on contacts and related fabrication methods

Also Published As

Publication number Publication date
US20150194339A1 (en) 2015-07-09
EP3090444B1 (en) 2021-06-30
US9508589B2 (en) 2016-11-29
WO2015102753A1 (en) 2015-07-09
EP3090444A1 (en) 2016-11-09
CN105874586A (zh) 2016-08-17
JP2017501581A (ja) 2017-01-12

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