CN105874586A - 导电层路由 - Google Patents
导电层路由 Download PDFInfo
- Publication number
- CN105874586A CN105874586A CN201480072114.5A CN201480072114A CN105874586A CN 105874586 A CN105874586 A CN 105874586A CN 201480072114 A CN201480072114 A CN 201480072114A CN 105874586 A CN105874586 A CN 105874586A
- Authority
- CN
- China
- Prior art keywords
- contacts
- active
- active contacts
- exposed
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461923482P | 2014-01-03 | 2014-01-03 | |
| US61/923,482 | 2014-01-03 | ||
| US14/283,162 | 2014-05-20 | ||
| US14/283,162 US9508589B2 (en) | 2014-01-03 | 2014-05-20 | Conductive layer routing |
| PCT/US2014/065529 WO2015102753A1 (en) | 2014-01-03 | 2014-11-13 | Conductive layer routing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105874586A true CN105874586A (zh) | 2016-08-17 |
Family
ID=52102992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480072114.5A Pending CN105874586A (zh) | 2014-01-03 | 2014-11-13 | 导电层路由 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9508589B2 (enExample) |
| EP (1) | EP3090444B1 (enExample) |
| JP (1) | JP6224844B2 (enExample) |
| CN (1) | CN105874586A (enExample) |
| WO (1) | WO2015102753A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9536833B2 (en) | 2013-02-01 | 2017-01-03 | Mediatek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
| US9455226B2 (en) | 2013-02-01 | 2016-09-27 | Mediatek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
| EP3131118B1 (en) * | 2015-08-12 | 2019-04-17 | MediaTek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120211837A1 (en) * | 2011-02-17 | 2012-08-23 | Globalfoundries Inc. | Semiconductor device comprising self-aligned contact elements |
| CN103199063A (zh) * | 2012-01-06 | 2013-07-10 | 格罗方德半导体公司 | 具电介质帽盖于接触件上的半导体设备及相关的制造方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01117342A (ja) * | 1987-10-30 | 1989-05-10 | Oki Electric Ind Co Ltd | コンタクトホールの形成方法 |
| JPH0982799A (ja) * | 1995-09-13 | 1997-03-28 | Hitachi Ltd | 配線基板およびその製造方法 |
| US6174803B1 (en) | 1998-09-16 | 2001-01-16 | Vsli Technology | Integrated circuit device interconnection techniques |
| US20070196983A1 (en) * | 2006-02-22 | 2007-08-23 | Hynix Semiconductor Inc. | Method of manufacturing non-volatile memory device |
| JPWO2007116515A1 (ja) * | 2006-04-07 | 2009-08-20 | 株式会社フィルテック | 半導体装置及びその製造方法、ドライエッチング方法、配線材料の作製方法、並びにエッチング装置 |
| KR100811442B1 (ko) | 2007-02-09 | 2008-03-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
| US7791109B2 (en) | 2007-03-29 | 2010-09-07 | International Business Machines Corporation | Metal silicide alloy local interconnect |
| JP2008270256A (ja) * | 2007-04-16 | 2008-11-06 | Denso Corp | 半導体装置およびその製造方法 |
| US8907316B2 (en) | 2008-11-07 | 2014-12-09 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions |
| US8124525B1 (en) | 2010-10-27 | 2012-02-28 | International Business Machines Corporation | Method of forming self-aligned local interconnect and structure formed thereby |
-
2014
- 2014-05-20 US US14/283,162 patent/US9508589B2/en active Active
- 2014-11-13 CN CN201480072114.5A patent/CN105874586A/zh active Pending
- 2014-11-13 EP EP14812669.1A patent/EP3090444B1/en active Active
- 2014-11-13 JP JP2016541713A patent/JP6224844B2/ja not_active Expired - Fee Related
- 2014-11-13 WO PCT/US2014/065529 patent/WO2015102753A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120211837A1 (en) * | 2011-02-17 | 2012-08-23 | Globalfoundries Inc. | Semiconductor device comprising self-aligned contact elements |
| CN103199063A (zh) * | 2012-01-06 | 2013-07-10 | 格罗方德半导体公司 | 具电介质帽盖于接触件上的半导体设备及相关的制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017501581A (ja) | 2017-01-12 |
| US9508589B2 (en) | 2016-11-29 |
| WO2015102753A1 (en) | 2015-07-09 |
| EP3090444A1 (en) | 2016-11-09 |
| US20150194339A1 (en) | 2015-07-09 |
| JP6224844B2 (ja) | 2017-11-01 |
| EP3090444B1 (en) | 2021-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105981157B (zh) | 缩放布局设计中将虚栅极接地 | |
| US10755969B2 (en) | Multi-patterning techniques for fabricating an array of metal lines with different widths | |
| KR102167351B1 (ko) | 라인 백엔드(Back End of Line)(BEOL) 상호접속을 위한 삭감 자기 정렬 비아 및 플러그 패터닝 | |
| TWI742018B (zh) | 用於半導體晶粒的互連結構的金屬化層、用於製造所述金屬化層的方法、包含所述金屬化層的積體電路結構及包含所述積體電路結構的計算裝置 | |
| TWI706442B (zh) | 用於後段製程線路(beol)互連之柵格自行對準金屬穿孔處理方法及由其所生成的結構 | |
| CN105745745A (zh) | 用于后段工艺(beol)互连件的借助光桶的自对准过孔和插塞图案化 | |
| US9401357B2 (en) | Directional FinFET capacitor structures | |
| CN104798219A (zh) | 使用中部制程(mol)导电层的电容器 | |
| CN105874586A (zh) | 导电层路由 | |
| US20150137201A1 (en) | High density linear capacitor | |
| KR101360134B1 (ko) | 반도체 장치의 제조 방법 | |
| CN107004636B (zh) | 通孔材料选择和处理 | |
| US10756085B2 (en) | Integrated circuit with metal gate having dielectric portion over isolation area | |
| CN107482010B (zh) | 一种半导体器件及其制作方法、电子装置 | |
| US9478490B2 (en) | Capacitor from second level middle-of-line layer in combination with decoupling capacitors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160817 |
|
| RJ01 | Rejection of invention patent application after publication |