JP6216454B2 - ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション - Google Patents
ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション Download PDFInfo
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- JP6216454B2 JP6216454B2 JP2016530069A JP2016530069A JP6216454B2 JP 6216454 B2 JP6216454 B2 JP 6216454B2 JP 2016530069 A JP2016530069 A JP 2016530069A JP 2016530069 A JP2016530069 A JP 2016530069A JP 6216454 B2 JP6216454 B2 JP 6216454B2
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
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- Theoretical Computer Science (AREA)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/951,098 US9471726B2 (en) | 2013-07-25 | 2013-07-25 | System level simulation in network on chip architecture |
| US13/951,098 | 2013-07-25 | ||
| PCT/US2014/048190 WO2015013609A1 (en) | 2013-07-25 | 2014-07-25 | System level simulation in network on chip architecture |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016527636A JP2016527636A (ja) | 2016-09-08 |
| JP2016527636A5 JP2016527636A5 (enExample) | 2017-07-27 |
| JP6216454B2 true JP6216454B2 (ja) | 2017-10-18 |
Family
ID=52391193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016530069A Active JP6216454B2 (ja) | 2013-07-25 | 2014-07-25 | ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US9471726B2 (enExample) |
| JP (1) | JP6216454B2 (enExample) |
| KR (1) | KR102285138B1 (enExample) |
| WO (1) | WO2015013609A1 (enExample) |
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| US11176302B2 (en) | 2018-02-23 | 2021-11-16 | Netspeed Systems, Inc. | System on chip (SoC) builder |
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| KR102376750B1 (ko) * | 2018-09-13 | 2022-03-21 | 한국전자통신연구원 | 디버깅을 위한 네트워크를 포함하는 시스템 온 칩 |
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| CN112929846B (zh) * | 2021-02-26 | 2022-07-22 | 北京邮电大学 | 基于车载设备的时间分配方法、装置、设备及存储介质 |
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| JP2016527636A (ja) | 2016-09-08 |
| US20170061053A1 (en) | 2017-03-02 |
| WO2015013609A1 (en) | 2015-01-29 |
| US20150032437A1 (en) | 2015-01-29 |
| US9471726B2 (en) | 2016-10-18 |
| KR20160033695A (ko) | 2016-03-28 |
| KR102285138B1 (ko) | 2021-08-05 |
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