JP2016510549A5 - - Google Patents

Download PDF

Info

Publication number
JP2016510549A5
JP2016510549A5 JP2015553847A JP2015553847A JP2016510549A5 JP 2016510549 A5 JP2016510549 A5 JP 2016510549A5 JP 2015553847 A JP2015553847 A JP 2015553847A JP 2015553847 A JP2015553847 A JP 2015553847A JP 2016510549 A5 JP2016510549 A5 JP 2016510549A5
Authority
JP
Japan
Prior art keywords
host
probability
hosts
noc
acceptance function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015553847A
Other languages
English (en)
Japanese (ja)
Other versions
JP5936793B2 (ja
JP2016510549A (ja
Filing date
Publication date
Priority claimed from US13/961,809 external-priority patent/US8667439B1/en
Application filed filed Critical
Publication of JP2016510549A publication Critical patent/JP2016510549A/ja
Publication of JP2016510549A5 publication Critical patent/JP2016510549A5/ja
Application granted granted Critical
Publication of JP5936793B2 publication Critical patent/JP5936793B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2015553847A 2013-02-27 2014-01-17 全体的なレイテンシを最小限に抑え、相互接続コストを削減するために、自動接続socs ipコアをノードに相互接続する方法 Active JP5936793B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201313779618A 2013-02-27 2013-02-27
US13/779,618 2013-02-27
US13/961,809 US8667439B1 (en) 2013-02-27 2013-08-07 Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost
US13/961,809 2013-08-07
PCT/US2014/012012 WO2014133684A1 (en) 2013-02-27 2014-01-17 Automatically connecting socs ip cores to interconnect nodes to minimize global latency and reduce interconnect cost

Publications (3)

Publication Number Publication Date
JP2016510549A JP2016510549A (ja) 2016-04-07
JP2016510549A5 true JP2016510549A5 (enExample) 2016-05-26
JP5936793B2 JP5936793B2 (ja) 2016-06-22

Family

ID=50158930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015553847A Active JP5936793B2 (ja) 2013-02-27 2014-01-17 全体的なレイテンシを最小限に抑え、相互接続コストを削減するために、自動接続socs ipコアをノードに相互接続する方法

Country Status (4)

Country Link
US (1) US8667439B1 (enExample)
JP (1) JP5936793B2 (enExample)
KR (1) KR101830762B1 (enExample)
WO (1) WO2014133684A1 (enExample)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9244880B2 (en) 2012-08-30 2016-01-26 Netspeed Systems Automatic construction of deadlock free interconnects
US8885510B2 (en) 2012-10-09 2014-11-11 Netspeed Systems Heterogeneous channel capacities in an interconnect
US8601423B1 (en) 2012-10-23 2013-12-03 Netspeed Systems Asymmetric mesh NoC topologies
US9774498B2 (en) 2012-12-21 2017-09-26 Netspeed Systems Hierarchical asymmetric mesh with virtual routers
US9253085B2 (en) 2012-12-21 2016-02-02 Netspeed Systems Hierarchical asymmetric mesh with virtual routers
US9185026B2 (en) 2012-12-21 2015-11-10 Netspeed Systems Tagging and synchronization for fairness in NOC interconnects
US9007920B2 (en) 2013-01-18 2015-04-14 Netspeed Systems QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes
US9009648B2 (en) 2013-01-18 2015-04-14 Netspeed Systems Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification
US9130856B2 (en) 2013-01-28 2015-09-08 Netspeed Systems Creating multiple NoC layers for isolation or avoiding NoC traffic congestion
US8934377B2 (en) 2013-03-11 2015-01-13 Netspeed Systems Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis
US9160627B2 (en) 2013-04-04 2015-10-13 Netspeed Systems Multiple heterogeneous NoC layers
US9185023B2 (en) 2013-05-03 2015-11-10 Netspeed Systems Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
US9571402B2 (en) 2013-05-03 2017-02-14 Netspeed Systems Congestion control and QoS in NoC by regulating the injection traffic
US10027433B2 (en) 2013-06-19 2018-07-17 Netspeed Systems Multiple clock domains in NoC
KR101830685B1 (ko) * 2013-06-29 2018-02-21 인텔 코포레이션 온칩 메시 상호접속부
US9781043B2 (en) 2013-07-15 2017-10-03 Netspeed Systems Identification of internal dependencies within system components for evaluating potential protocol level deadlocks
US9471726B2 (en) 2013-07-25 2016-10-18 Netspeed Systems System level simulation in network on chip architecture
US9054977B2 (en) 2013-08-05 2015-06-09 Netspeed Systems Automatic NoC topology generation
US9473388B2 (en) 2013-08-07 2016-10-18 Netspeed Systems Supporting multicast in NOC interconnect
US9223711B2 (en) 2013-08-13 2015-12-29 Netspeed Systems Combining associativity and cuckoo hashing
US9294354B2 (en) 2013-10-24 2016-03-22 Netspeed Systems Using multiple traffic profiles to design a network on chip
US9830265B2 (en) 2013-11-20 2017-11-28 Netspeed Systems, Inc. Reuse of directory entries for holding state information through use of multiple formats
US9158882B2 (en) 2013-12-19 2015-10-13 Netspeed Systems Automatic pipelining of NoC channels to meet timing and/or performance
US9699079B2 (en) 2013-12-30 2017-07-04 Netspeed Systems Streaming bridge design with host interfaces and network on chip (NoC) layers
US9473415B2 (en) 2014-02-20 2016-10-18 Netspeed Systems QoS in a system with end-to-end flow control and QoS aware buffer allocation
US9319232B2 (en) 2014-04-04 2016-04-19 Netspeed Systems Integrated NoC for performing data communication and NoC functions
US9762474B2 (en) * 2014-04-07 2017-09-12 Netspeed Systems Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)
US9465902B1 (en) 2014-04-11 2016-10-11 Altera Corporation Method and apparatus for designing a system using weighted-cost interconnect synthesis
US9244845B2 (en) 2014-05-12 2016-01-26 Netspeed Systems System and method for improving snoop performance
US9473359B2 (en) 2014-06-06 2016-10-18 Netspeed Systems Transactional traffic specification for network-on-chip design
US9535848B2 (en) 2014-06-18 2017-01-03 Netspeed Systems Using cuckoo movement for improved cache coherency
US9553762B1 (en) 2014-06-26 2017-01-24 Altera Corporation Network-on-chip with fixed and configurable functions
US10528682B2 (en) 2014-09-04 2020-01-07 Netspeed Systems Automatic performance characterization of a network-on-chip (NOC) interconnect
US9742630B2 (en) 2014-09-22 2017-08-22 Netspeed Systems Configurable router for a network on chip (NoC)
US9477280B1 (en) 2014-09-24 2016-10-25 Netspeed Systems Specification for automatic power management of network-on-chip and system-on-chip
US10042404B2 (en) 2014-09-26 2018-08-07 Netspeed Systems Automatic generation of power management sequence in a SoC or NoC
US9571341B1 (en) 2014-10-01 2017-02-14 Netspeed Systems Clock gating for system-on-chip elements
US9529400B1 (en) 2014-10-29 2016-12-27 Netspeed Systems Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
US9660942B2 (en) 2015-02-03 2017-05-23 Netspeed Systems Automatic buffer sizing for optimal network-on-chip design
US9444702B1 (en) 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9928204B2 (en) 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design
US9568970B1 (en) 2015-02-12 2017-02-14 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US10348563B2 (en) 2015-02-18 2019-07-09 Netspeed Systems, Inc. System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
US10050843B2 (en) 2015-02-18 2018-08-14 Netspeed Systems Generation of network-on-chip layout based on user specified topological constraints
US9864728B2 (en) 2015-05-29 2018-01-09 Netspeed Systems, Inc. Automatic generation of physically aware aggregation/distribution networks
US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US10218580B2 (en) 2015-06-18 2019-02-26 Netspeed Systems Generating physically aware network-on-chip design from a physical system-on-chip specification
US9665683B1 (en) * 2015-10-23 2017-05-30 Xilinx, Inc. Designing a system for a programmable system-on-chip using performance characterization techniques
US10452124B2 (en) 2016-09-12 2019-10-22 Netspeed Systems, Inc. Systems and methods for facilitating low power on a network-on-chip
US20180159786A1 (en) 2016-12-02 2018-06-07 Netspeed Systems, Inc. Interface virtualization and fast path for network on chip
US10313269B2 (en) 2016-12-26 2019-06-04 Netspeed Systems, Inc. System and method for network on chip construction through machine learning
US10063496B2 (en) 2017-01-10 2018-08-28 Netspeed Systems Inc. Buffer sizing of a NoC through machine learning
US10084725B2 (en) * 2017-01-11 2018-09-25 Netspeed Systems, Inc. Extracting features from a NoC for machine learning construction
US10469337B2 (en) 2017-02-01 2019-11-05 Netspeed Systems, Inc. Cost management against requirements for the generation of a NoC
US10298485B2 (en) 2017-02-06 2019-05-21 Netspeed Systems, Inc. Systems and methods for NoC construction
CA3060969C (en) * 2017-04-17 2020-12-29 Cerebras Systems Inc. Neuron smearing for accelerated deep learning
US11144457B2 (en) 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10896476B2 (en) 2018-02-22 2021-01-19 Netspeed Systems, Inc. Repository of integration description of hardware intellectual property for NoC construction and SoC integration
US10983910B2 (en) 2018-02-22 2021-04-20 Netspeed Systems, Inc. Bandwidth weighting mechanism based network-on-chip (NoC) configuration
US10547514B2 (en) 2018-02-22 2020-01-28 Netspeed Systems, Inc. Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
US11176302B2 (en) 2018-02-23 2021-11-16 Netspeed Systems, Inc. System on chip (SoC) builder
US11023377B2 (en) 2018-02-23 2021-06-01 Netspeed Systems, Inc. Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
US10860762B2 (en) 2019-07-11 2020-12-08 Intel Corpration Subsystem-based SoC integration
KR102391802B1 (ko) * 2020-11-04 2022-04-29 성균관대학교산학협력단 유전 알고리즘 기반의 토폴로지 합성 방법
CN114500355B (zh) * 2022-02-16 2023-06-16 上海壁仞智能科技有限公司 路由方法、片上网络、路由节点和路由装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8059551B2 (en) * 2005-02-15 2011-11-15 Raytheon Bbn Technologies Corp. Method for source-spoofed IP packet traceback
EP2076874A4 (en) * 2006-05-13 2011-03-09 Sap Ag COHERENT ASSEMBLY OF INTERFACES DERIVED FROM A COMMERCIAL OBJECT MODEL
US8099757B2 (en) * 2007-10-15 2012-01-17 Time Warner Cable Inc. Methods and apparatus for revenue-optimized delivery of content in a network
US8065433B2 (en) * 2009-01-09 2011-11-22 Microsoft Corporation Hybrid butterfly cube architecture for modular data centers
WO2011077897A1 (ja) * 2009-12-21 2011-06-30 日本電気株式会社 経路計算方法、経路計算装置、通信システム

Similar Documents

Publication Publication Date Title
JP5936793B2 (ja) 全体的なレイテンシを最小限に抑え、相互接続コストを削減するために、自動接続socs ipコアをノードに相互接続する方法
JP2016510549A5 (enExample)
US9158882B2 (en) Automatic pipelining of NoC channels to meet timing and/or performance
JP6060316B2 (ja) NoCを構成するための方法及びシステム並びにコンピュータ可読記憶媒体
US9529400B1 (en) Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
JP6216454B2 (ja) ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション
US9185023B2 (en) Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
US9160627B2 (en) Multiple heterogeneous NoC layers
US10547514B2 (en) Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
US20140211622A1 (en) Creating multiple noc layers for isolation or avoiding noc traffic congestion
US20180183727A1 (en) Traffic mapping of a network on chip through machine learning
US10313269B2 (en) System and method for network on chip construction through machine learning
US10298485B2 (en) Systems and methods for NoC construction
US10419300B2 (en) Cost management against requirements for the generation of a NoC
US9864728B2 (en) Automatic generation of physically aware aggregation/distribution networks
US9762474B2 (en) Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)
US20180198682A1 (en) Strategies for NoC Construction Using Machine Learning