JP6216454B2 - ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション - Google Patents
ネットワークオンチップアーキテクチャにおけるシステムレベルシミュレーション Download PDFInfo
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- 238000004088 simulation Methods 0.000 title claims description 56
- 238000000034 method Methods 0.000 claims description 16
- 239000003795 chemical substances by application Substances 0.000 description 111
- 244000025221 Humulus lupulus Species 0.000 description 19
- 230000006399 behavior Effects 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 11
- 238000004891 communication Methods 0.000 description 8
- 235000008694 Humulus lupulus Nutrition 0.000 description 6
- 230000015654 memory Effects 0.000 description 6
- 230000004044 response Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000002457 bidirectional effect Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 235000006878 Humulus lupulus var neomexicanus Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010606 normalization Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000009809 Humulus lupulus var lupuloides Nutrition 0.000 description 1
- 235000009800 Humulus lupulus var pubescens Nutrition 0.000 description 1
- 235000009808 Humulus lupulus var. lupulus Nutrition 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 235000019800 disodium phosphate Nutrition 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
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Description
hp2[第1のメッセージの特性及び属性を含んでいる]
待機10
hp3[第1のメッセージの特性及び属性を含んでいる]
待機20
hp2[第1のメッセージの特性及び属性を含んでいる]
hp4[第1のメッセージの特性及び属性を含んでいる]
待機20
上述のhp1に関するトレースファイルは、hp2への2つのトランザクション、hp3への1つのトランザクション及びhp4への1つのトランザクションを示している。当該hp2への2つのトランザクションは同一のトランザクションであり得るか、またはhp2への共通の第1のメッセージを有する異なったトランザクションであり得る。さらに、上述のトレースファイルは、hp2への第1のトランザクションとhp3へのトランザクションとの間に10単位の待機時間を示しており、hp2への第2のトランザクションとhp4へのトランザクションとの間には待機時間は無い。理解されるように、任意の所定のトランザクションの第1のメッセージの待機時間及び特性/属性は、監視されるべきNoCインターコネクトの所望の挙動に基づいて常時変更され得る。さらに、トランザクションの第1のメッセージ及びそれに続く他のメッセージの特性も事前に定義され得、トレースファイルに含まれることを回避している。さらに、以下にさらに詳細に説明するように、トランザクションの第1のメッセージのみの代わりに、トレースファイルは、全てのメッセージシーケンスと共にそのレート/値/サイズ/その他の属性も含み得る。
その後、806において、更新されたかまたは新しく生成されたトレースファイルが、シミュレーションを行うために、かつトランザクションシーケンス内のエントリに基づいたトランザクションシーケンスの実行を開始するために使用され得る。807において、シミュレーションの各々が実行されたかまたはシミュレーションの組み合わせが実行された後に性能レポートが生成され、NoCインターコネクトの性能の分析が促進される。
Claims (10)
- コンピュータにおいて複数のトランザクションを用いてネットワークオンチップ(NoC)インターコネクトのシミュレーションを実行するステップであって、前記複数のトランザクションの各々は1または複数のメッセージのシーケンスを含み、かつ前記1または複数のメッセージの各々は送信元及び送信先エージェントのうちの少なくとも1つに関する表示を含んでいるステップと、
前記1または複数のメッセージのシーケンス内の最初のメッセージ送信先ノードに基づいて前記複数のトランザクションの各々に関する前記1または複数のメッセージのシーケンス内の後続のメッセージを生成するステップと、を含み、
前記後続のメッセージは前記1または複数のメッセージの送信先ノードの各々において生成されることを特徴とする方法。 - 請求項1に記載の方法であって、前記1または複数のメッセージの各々は、レート、優先度、値、メッセージデータサイズ、遅延及びインターバルの少なくとも1つに関する表示を含んでおり、メッセージは、前記レート、前記優先度、前記値、前記メッセージデータサイズ、前記遅延及び前記インターバルに基づいて前記シミュレーションを実行するために使用されることを特徴とする方法。
- 請求項2に記載の方法であって、前記1または複数のメッセージは、レートに関する表示を含み、前記レートは前記シミュレーションの間のメッセージの各々の選択確率の表示を含んでいることを特徴とする方法。
- 請求項1に記載の方法であって、前記エージェントの各々から生ずる前記複数のトランザクションシーケンスの各々に基づいて前記エージェントの各々に関するトレースファイルを生成するステップをさらに含み、前記トレースファイルは前記複数のトランザクションシーケンスの各々内の前記1または複数のメッセージのサブセットを含むことを特徴とする方法。
- 請求項1に記載の方法であって、前記シミュレーションに基づいて前記NoCインターコネクトの性能レポートを生成するステップをさらに含むことを特徴とする方法。
- 複数のトランザクションを使用してネットワークオンチップ(NoC)インターコネクトのシミュレーションを実行するステップであって、前記複数のトランザクションシーケンスの各々が1または複数のメッセージのシーケンスを含み、前記1または複数のメッセージの各々は送信元及び送信先エージェントのうちの少なくとも1つに関する表示を含むステップと、
前記1または複数のメッセージのシーケンス内の最初のメッセージ送信先ノードに基づいて前記複数のトランザクションの各々に関する前記1または複数のメッセージのシーケンス内の後続のメッセージを生成するステップと、を実行するプロセッサを含むサーバであって、
前記後続のメッセージは、前記1または複数のメッセージの送信先ノードの各々において生成されることを特徴とするサーバ。 - 請求項6に記載のサーバであって、前記1または複数のメッセージの各々は、レート、優先度、値、メッセージデータサイズ、遅延及びインターバルの少なくとも1つに関する表示を含んでおり、メッセージは、前記レート、前記優先度、前記値、前記メッセージデータサイズ、前記遅延及び前記インターバルに基づいて前記シミュレーションを実行するために使用されることを特徴とするサーバ。
- 請求項7に記載のサーバであって、前記1または複数のメッセージの各々は、レートに関する表示を含み、前記レートは、前記シミュレーションの間のメッセージの各々の選択確率の表示を含んでいることを特徴とするサーバ。
- 請求項6に記載のサーバであって、前記プロセッサは、前記エージェントの各々から生ずる前記複数のトランザクションシーケンスの各々に基づいて前記エージェントの各々に関するトレースファイルを生成し、前記トレースファイルは前記複数のトランザクションシーケンスの各々に関する前記1または複数のメッセージの表示を含むことを特徴とするサーバ。
- 請求項6に記載のサーバであって、前記プロセッサは、さらに、前記シミュレーションに基づいて前記NoCインターコネクトの性能レポートを生成することを特徴とするサーバ。
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US13/951,098 | 2013-07-25 | ||
US13/951,098 US9471726B2 (en) | 2013-07-25 | 2013-07-25 | System level simulation in network on chip architecture |
PCT/US2014/048190 WO2015013609A1 (en) | 2013-07-25 | 2014-07-25 | System level simulation in network on chip architecture |
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JP2016527636A JP2016527636A (ja) | 2016-09-08 |
JP2016527636A5 JP2016527636A5 (ja) | 2017-07-27 |
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Also Published As
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US20150032437A1 (en) | 2015-01-29 |
KR102285138B1 (ko) | 2021-08-05 |
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US10496770B2 (en) | 2019-12-03 |
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