KR101830762B1 - 전체적 대기 시간이 최소화되고 인터커넥트 비용이 감소하도록 노드들을 상호연결하는 soc ip 코어 자동 연결 방법 - Google Patents

전체적 대기 시간이 최소화되고 인터커넥트 비용이 감소하도록 노드들을 상호연결하는 soc ip 코어 자동 연결 방법 Download PDF

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KR101830762B1
KR101830762B1 KR1020157023266A KR20157023266A KR101830762B1 KR 101830762 B1 KR101830762 B1 KR 101830762B1 KR 1020157023266 A KR1020157023266 A KR 1020157023266A KR 20157023266 A KR20157023266 A KR 20157023266A KR 101830762 B1 KR101830762 B1 KR 101830762B1
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살리에쉬 쿠말
에릭 노리쥬
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넷스피드 시스템즈
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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
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    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
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    • G—PHYSICS
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KR1020157023266A 2013-02-27 2014-01-17 전체적 대기 시간이 최소화되고 인터커넥트 비용이 감소하도록 노드들을 상호연결하는 soc ip 코어 자동 연결 방법 Expired - Fee Related KR101830762B1 (ko)

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US201313779618A 2013-02-27 2013-02-27
US13/779,618 2013-02-27
US13/961,809 US8667439B1 (en) 2013-02-27 2013-08-07 Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost
US13/961,809 2013-08-07
PCT/US2014/012012 WO2014133684A1 (en) 2013-02-27 2014-01-17 Automatically connecting socs ip cores to interconnect nodes to minimize global latency and reduce interconnect cost

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KR20150122150A (ko) 2015-10-30
US8667439B1 (en) 2014-03-04
WO2014133684A1 (en) 2014-09-04
JP2016510549A (ja) 2016-04-07

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