JP6211186B2 - Ｄｒａｍサブアレイレベル自律リフレッシュメモリコントローラの最適化 - Google Patents

Ｄｒａｍサブアレイレベル自律リフレッシュメモリコントローラの最適化 Download PDF

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JP6211186B2
JP6211186B2 JP2016525343A JP2016525343A JP6211186B2 JP 6211186 B2 JP6211186 B2 JP 6211186B2 JP 2016525343 A JP2016525343 A JP 2016525343A JP 2016525343 A JP2016525343 A JP 2016525343A JP 6211186 B2 JP6211186 B2 JP 6211186B2
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refresh
row
dram
open
dram bank
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JP2016526750A5 (enExample
JP2016526750A (ja
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ディープティ・ヴィジャヤラクシミ・シュリラマギリ
ジュンウォン・スー
シアンユ・ドン
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
JP2016525343A 2013-07-12 2014-05-20 Ｄｒａｍサブアレイレベル自律リフレッシュメモリコントローラの最適化 Expired - Fee Related JP6211186B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361845818P 2013-07-12 2013-07-12
US61/845,818 2013-07-12
US14/148,515 2014-01-06
US14/148,515 US9524771B2 (en) 2013-07-12 2014-01-06 DRAM sub-array level autonomic refresh memory controller optimization
PCT/US2014/038845 WO2015005975A1 (en) 2013-07-12 2014-05-20 Dram sub-array level autonomic refresh memory controller optimization

Publications (3)

Publication Number Publication Date
JP2016526750A JP2016526750A (ja) 2016-09-05
JP2016526750A5 JP2016526750A5 (enExample) 2017-03-02
JP6211186B2 true JP6211186B2 (ja) 2017-10-11

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JP2016525343A Expired - Fee Related JP6211186B2 (ja) 2013-07-12 2014-05-20 Ｄｒａｍサブアレイレベル自律リフレッシュメモリコントローラの最適化

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Country Link
US (1) US9524771B2 (enExample)
EP (1) EP3020046A1 (enExample)
JP (1) JP6211186B2 (enExample)
KR (1) KR101763312B1 (enExample)
CN (1) CN105378847B (enExample)
WO (1) WO2015005975A1 (enExample)

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US11544168B2 (en) 2017-10-30 2023-01-03 SK Hynix Inc. Memory system
KR102414047B1 (ko) 2017-10-30 2022-06-29 에스케이하이닉스 주식회사 통합 메모리 디바이스 및 그의 동작 방법
US11017833B2 (en) 2018-05-24 2021-05-25 Micron Technology, Inc. Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling
US10573370B2 (en) 2018-07-02 2020-02-25 Micron Technology, Inc. Apparatus and methods for triggering row hammer address sampling
KR102578002B1 (ko) * 2018-07-03 2023-09-14 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
US10636476B2 (en) * 2018-11-01 2020-04-28 Intel Corporation Row hammer mitigation with randomization of target row selection
WO2020117686A1 (en) 2018-12-03 2020-06-11 Micron Technology, Inc. Semiconductor device performing row hammer refresh operation
CN117198356A (zh) 2018-12-21 2023-12-08 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10957377B2 (en) 2018-12-26 2021-03-23 Micron Technology, Inc. Apparatuses and methods for distributed targeted refresh operations
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US11227649B2 (en) * 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US10978132B2 (en) 2019-06-05 2021-04-13 Micron Technology, Inc. Apparatuses and methods for staggered timing of skipped refresh operations
US11023171B2 (en) 2019-07-17 2021-06-01 Micron Technology, Inc. Performing a refresh operation based on a write to read time difference
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) * 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
CN111158585B (zh) * 2019-11-27 2023-08-01 核芯互联科技(青岛)有限公司 一种内存控制器刷新优化方法、装置、设备和存储介质
US11309010B2 (en) 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
CN114255799B (zh) * 2020-09-22 2023-10-17 长鑫存储技术有限公司 存储器数据刷新方法及其控制器、存储器
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US12308069B2 (en) * 2020-10-26 2025-05-20 Qualcomm Incorporated DRAM with quick random row refresh for rowhammer mitigation
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Also Published As

Publication number Publication date
CN105378847A (zh) 2016-03-02
CN105378847B (zh) 2018-06-12
KR101763312B1 (ko) 2017-07-31
US20150016203A1 (en) 2015-01-15
KR20160030542A (ko) 2016-03-18
JP2016526750A (ja) 2016-09-05
EP3020046A1 (en) 2016-05-18
US9524771B2 (en) 2016-12-20
WO2015005975A1 (en) 2015-01-15

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