JP6082284B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

Info

Publication number
JP6082284B2
JP6082284B2 JP2013051537A JP2013051537A JP6082284B2 JP 6082284 B2 JP6082284 B2 JP 6082284B2 JP 2013051537 A JP2013051537 A JP 2013051537A JP 2013051537 A JP2013051537 A JP 2013051537A JP 6082284 B2 JP6082284 B2 JP 6082284B2
Authority
JP
Japan
Prior art keywords
metal layer
aluminum oxide
oxide substrate
connection pad
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013051537A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014179411A5 (enExample
JP2014179411A (ja
Inventor
堀内　道夫
道夫 堀内
亮 深澤
亮 深澤
勇一 松田
勇一 松田
徳武　安衛
安衛 徳武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013051537A priority Critical patent/JP6082284B2/ja
Priority to US14/202,220 priority patent/US9204544B2/en
Publication of JP2014179411A publication Critical patent/JP2014179411A/ja
Publication of JP2014179411A5 publication Critical patent/JP2014179411A5/ja
Application granted granted Critical
Publication of JP6082284B2 publication Critical patent/JP6082284B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2013051537A 2013-03-14 2013-03-14 配線基板及びその製造方法 Expired - Fee Related JP6082284B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013051537A JP6082284B2 (ja) 2013-03-14 2013-03-14 配線基板及びその製造方法
US14/202,220 US9204544B2 (en) 2013-03-14 2014-03-10 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013051537A JP6082284B2 (ja) 2013-03-14 2013-03-14 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2014179411A JP2014179411A (ja) 2014-09-25
JP2014179411A5 JP2014179411A5 (enExample) 2016-01-21
JP6082284B2 true JP6082284B2 (ja) 2017-02-15

Family

ID=51522422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013051537A Expired - Fee Related JP6082284B2 (ja) 2013-03-14 2013-03-14 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US9204544B2 (enExample)
JP (1) JP6082284B2 (enExample)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942400A (en) * 1990-02-09 1990-07-17 General Electric Company Analog to digital converter with multilayer printed circuit mounting
JP3014503B2 (ja) * 1991-08-05 2000-02-28 日本特殊陶業株式会社 集積回路用パッケージ
JP2002289998A (ja) * 2001-03-23 2002-10-04 Citizen Watch Co Ltd 回路基板とその製造方法
US6828513B2 (en) * 2002-04-30 2004-12-07 Texas Instruments Incorporated Electrical connector pad assembly for printed circuit board
JP2004273480A (ja) * 2003-03-05 2004-09-30 Sony Corp 配線基板およびその製造方法および半導体装置
US7583513B2 (en) * 2003-09-23 2009-09-01 Intel Corporation Apparatus for providing an integrated printed circuit board registration coupon
JP4654942B2 (ja) * 2006-02-28 2011-03-23 ミネベア株式会社 面状照明装置
JP5344667B2 (ja) 2007-12-18 2013-11-20 太陽誘電株式会社 回路基板およびその製造方法並びに回路モジュール
JP5385682B2 (ja) * 2009-05-19 2014-01-08 新光電気工業株式会社 電子部品の実装構造
JP2011014612A (ja) * 2009-06-30 2011-01-20 Ibiden Co Ltd 配線基板及び配線基板の製造方法
JP2011151185A (ja) * 2010-01-21 2011-08-04 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
US8870579B1 (en) * 2011-01-14 2014-10-28 Paricon Technologies Corporation Thermally and electrically enhanced elastomeric conductive materials

Also Published As

Publication number Publication date
US20140262465A1 (en) 2014-09-18
US9204544B2 (en) 2015-12-01
JP2014179411A (ja) 2014-09-25

Similar Documents

Publication Publication Date Title
US8324513B2 (en) Wiring substrate and semiconductor apparatus including the wiring substrate
TWI504318B (zh) 印刷電路板及製造其之方法
US9693458B2 (en) Printed wiring board, method for manufacturing printed wiring board and package-on-package
US9307643B2 (en) Substrate with built-in electronic component and method for manufacturing substrate with built-in electronic component
JP6210777B2 (ja) バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法
KR20060061227A (ko) 회로 기판의 제조 방법 및 전자부품 실장 구조체의 제조방법
TW201601262A (zh) 中介層、半導體裝置、中介層的製造方法及半導體裝置的製造方法
CN105704926B (zh) 电子模块的制备方法以及电子模块
KR101835782B1 (ko) 박막 커패시터의 제조 방법, 집적 회로 탑재 기판 및 당해 기판을 구비한 반도체 장치
JP6282425B2 (ja) 配線基板の製造方法
JP2015198094A (ja) インターポーザ、半導体装置、およびそれらの製造方法
WO2016114133A1 (ja) インターポーザ、半導体装置、およびそれらの製造方法
JP2017005081A (ja) インターポーザ、半導体装置、およびそれらの製造方法
JP4227973B2 (ja) 基板、電子部品、及び、これらの製造方法
JP6082284B2 (ja) 配線基板及びその製造方法
KR102141102B1 (ko) 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
JP2007081100A (ja) 配線基板およびその製造方法
JP5980554B2 (ja) 電気的接続部材、検査方法及び電気的接続部材の製造方法
US20150027977A1 (en) Method of manufacturing wiring board
JP6533089B2 (ja) 配線基板
JP5154963B2 (ja) 配線基板の製造方法
JP2019041031A (ja) 配線基板
JP5680589B2 (ja) 配線基板
JP2010278032A (ja) 表面実装型コンデンサ
JP2014179411A5 (enExample)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151125

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160929

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161011

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161109

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170110

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170120

R150 Certificate of patent or registration of utility model

Ref document number: 6082284

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees