JP5999376B2 - Device mounting substrate, semiconductor module, and device mounting substrate manufacturing method - Google Patents

Device mounting substrate, semiconductor module, and device mounting substrate manufacturing method Download PDF

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Publication number
JP5999376B2
JP5999376B2 JP2013535885A JP2013535885A JP5999376B2 JP 5999376 B2 JP5999376 B2 JP 5999376B2 JP 2013535885 A JP2013535885 A JP 2013535885A JP 2013535885 A JP2013535885 A JP 2013535885A JP 5999376 B2 JP5999376 B2 JP 5999376B2
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oxide film
substrate
thickness
insulating resin
resin layer
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JPWO2013046617A1 (en
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泰浩 小原
泰浩 小原
正幸 長松
正幸 長松
幸太郎 出口
幸太郎 出口
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Description

本発明は、素子搭載用基板、半導体モジュールおよび素子搭載用基板の製造方法に関する。   The present invention relates to an element mounting substrate, a semiconductor module, and a method for manufacturing the element mounting substrate.

パワー系半導体素子の発熱を放熱するためには、絶縁層として放熱特性に優れたセラミクス材料を用いることが望ましいが、セラミクス基板はコストが非常に高い。制御系半導体素子はパワー系半導体素子よりも発熱が小さいため、パワー系半導体素子と制御系半導体素子とを高価なセラミクス基板の上に搭載することはオーバースペックであるばかりか、パワー系半導体素子と制御系半導体素子と熱伝導が良好なセラミクス基板の上に混載するとパワー系半導体素子で生じた熱が制御系半導体素子に伝播することにより、制御系半導体素子が高温となり、制御系半導体素子が暴走するという問題が生じる。このような課題を解決する手段として、絶縁樹脂にセラミクスフィラーを充填した絶縁樹脂層が特許文献１に記載されている。   In order to dissipate heat generated by the power semiconductor element, it is desirable to use a ceramic material having excellent heat dissipation characteristics as the insulating layer, but the ceramic substrate is very expensive. Since the control system semiconductor element generates less heat than the power system semiconductor element, mounting the power system semiconductor element and the control system semiconductor element on an expensive ceramic substrate is not only an overspec, but also with the power system semiconductor element. When mixed with a control system semiconductor element and a ceramic substrate with good thermal conductivity, heat generated in the power system semiconductor element propagates to the control system semiconductor element, causing the control system semiconductor element to reach a high temperature and causing the control system semiconductor element to run out of control. Problem arises. As means for solving such a problem, Patent Document 1 discloses an insulating resin layer in which an insulating resin is filled with a ceramic filler.

特開２００３−３０３９４０号公報JP 2003-303940 A 特開平５−１９１００１号公報Japanese Patent Laid-Open No. 5-191001 特開２００８−１５９６４７号公報JP 2008-159647 A

特許文献１にも記載されている通り、フィラーを充填した絶縁層で放熱特性と絶縁耐圧特性とを両立させることは困難な技術である。   As described in Patent Document 1, it is difficult to achieve both heat dissipation characteristics and dielectric strength characteristics with an insulating layer filled with a filler.

本発明はこうした課題に鑑みてなされたものであり、その目的は、発熱量の多い半導体素子であるパワー系半導体素子と発熱量の少ない半導体素子である制御系半導体素子とが混載されている素子搭載用基板において、パワー系半導体素子搭載部で必要とされる放熱特性および絶縁耐圧特性を満足するとともに、パワー系半導体素子の発熱が制御系半導体素子に伝播することを抑制することができる技術の提供にある。ここで、パワー系半導体素子にはたとえばパワーＭＯＳＦＥＴ、ＩＧＢＴ、などのパワートランジスタやLED素子、制御系半導体素子にはたとえばゲートドライブＩＣや照度センサを用いることができる。   The present invention has been made in view of such problems, and an object thereof is an element in which a power semiconductor element that is a semiconductor element that generates a large amount of heat and a control semiconductor element that is a semiconductor element that generates a small amount of heat are mounted together. In the mounting substrate, a technology capable of satisfying the heat radiation characteristics and the withstand voltage characteristics required in the power semiconductor element mounting portion and suppressing the heat generated by the power semiconductor element from propagating to the control semiconductor element. On offer. Here, for example, a power transistor or an LED element such as a power MOSFET or IGBT can be used as the power semiconductor element, and a gate drive IC or an illuminance sensor can be used as the control semiconductor element.

本発明のある態様は、素子搭載用基板である。当該素子搭載用基板は、金属基板と、金属基板の表面が酸化されてなる酸化膜と、金属基板の一方の主表面側の酸化膜上に設けられた絶縁樹脂層と、絶縁樹脂層上に設けられた配線層と、を備え、少なくとも一部の前記酸化膜の膜厚が他の部分の前記酸化膜の膜厚よりも厚いことを特徴とする。   One embodiment of the present invention is an element mounting substrate. The element mounting substrate includes a metal substrate, an oxide film formed by oxidizing the surface of the metal substrate, an insulating resin layer provided on an oxide film on one main surface side of the metal substrate, and an insulating resin layer. And a wiring layer provided, wherein at least a part of the oxide film is thicker than another part of the oxide film.

本発明の他の態様は、半導体モジュールである。当該半導体モジュールは、上述した態様の素子搭載用基板と、当該素子搭載用基板の配線層が形成された側の主表面上に搭載され、配線層と電気的に接続された半導体素子と、を備えたことを特徴とする。   Another embodiment of the present invention is a semiconductor module. The semiconductor module includes an element mounting substrate of the above-described aspect and a semiconductor element mounted on the main surface of the element mounting substrate on the side where the wiring layer is formed and electrically connected to the wiring layer. It is characterized by having.

本発明のさらに他の態様は、素子搭載用基板の製造方法である。当該素子搭載用基板の製造方法は、金属基板の所定領域に突起部を形成する工程と、金属基板に形成された突起部の表面を粗化する工程と、金属基板の表面に酸化処理を施して酸化膜を形成する工程と、酸化膜上に絶縁樹脂層を積層する工程と、絶縁樹脂層上に金属層を積層し、当該金属層を選択的に除去して配線層を形成する工程と、を含むことを特徴とする。   Yet another embodiment of the present invention is a method for manufacturing an element mounting substrate. The element mounting substrate manufacturing method includes a step of forming a protrusion in a predetermined region of a metal substrate, a step of roughening the surface of the protrusion formed on the metal substrate, and an oxidation treatment on the surface of the metal substrate. Forming an oxide film, laminating an insulating resin layer on the oxide film, laminating a metal layer on the insulating resin layer, and selectively removing the metal layer to form a wiring layer; , Including.

本発明によれば、発熱量の少ない半導体素子である制御系半導体素子の温度上昇を引き起こすことなく、発熱量の多い半導体素子であるパワー系半導体素子の絶縁耐圧と放熱性の両方を確保できる。   According to the present invention, it is possible to ensure both the withstand voltage and heat dissipation of a power semiconductor element that is a semiconductor element with a large amount of heat generation without causing a temperature rise of the control system semiconductor element that is a semiconductor element with a small amount of heat generation.

実施の形態１に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。2 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to Embodiment 1. FIG. 図２（Ａ）〜図２（Ｄ）は、実施の形態１に係る素子搭載用基板および半導体モジュールの製造方法を説明するための工程模式図である。2A to 2D are process schematic diagrams for explaining a method for manufacturing the element mounting substrate and the semiconductor module according to the first embodiment. 図３（Ａ）〜図３（Ｃ）は、実施の形態１に係る素子搭載用基板および半導体モジュールの製造方法を説明するための工程模式図である。3A to 3C are process schematic diagrams for explaining a method for manufacturing the element mounting substrate and the semiconductor module according to the first embodiment. 図４（Ａ）〜図４（Ｂ）は、実施の形態１に係る素子搭載用基板および半導体モジュールの製造方法を説明するための工程模式図である。4A to 4B are process schematic diagrams for explaining a method for manufacturing the element mounting substrate and the semiconductor module according to the first embodiment. 実施の形態２に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to Embodiment 2. FIG. 図６（Ａ）〜図２（Ｃ）は、実施の形態２に係る素子搭載用基板および半導体モジュールの製造方法を説明するための工程模式図である。6A to 2C are process schematic diagrams for explaining a method for manufacturing the element mounting substrate and the semiconductor module according to the second embodiment. 実施の形態３に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。FIG. 6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to a third embodiment.

以下、本発明の実施の形態を図面を参照して説明する。なお、すべての図面において、同様な構成要素、部材、処理には同様の符号を付し、適宜説明を省略する。また、実施の形態は、発明を限定するものではなく例示であって、実施の形態に記述されるすべての特徴やその組み合わせは、必ずしも発明の本質的なものであるとは限らない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, similar components, members, and processes are denoted by the same reference numerals, and description thereof is omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

（実施の形態１）
図１は、実施の形態１に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。本実施の形態に係る半導体モジュール１は、素子搭載用基板１００と、素子搭載用基板１００の一方の主表面上に搭載された半導体素子２００，２１０を備える。半導体素子２００は、例えばトランジスタ、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）等のパワー系半導体素子である。半導体素子２１０は、例えば制御ＩＣ等の制御系半導体素子である。(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to the first embodiment. The semiconductor module 1 according to the present embodiment includes an element mounting substrate 100 and semiconductor elements 200 and 210 mounted on one main surface of the element mounting substrate 100. The semiconductor element 200 is a power semiconductor element such as a transistor, an IGBT (Insulated Gate Bipolar Transistor), or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor element 210 is a control semiconductor element such as a control IC, for example.

素子搭載用基板１００は、金属基板１１０と、酸化膜１２０と、絶縁樹脂層１３０と、配線層１４０とを備える。   The element mounting substrate 100 includes a metal substrate 110, an oxide film 120, an insulating resin layer 130, and a wiring layer 140.

金属基板１１０は、アルミニウム、アルミニウム合金などの熱伝導性が良好な金属で構成された基板である。本実施の形態では、金属基板１１０はアルミニウム基板である。金属基板１１０の厚さは、例えば０．５ｍｍ〜２ｍｍである。   The metal substrate 110 is a substrate made of a metal having good thermal conductivity such as aluminum or an aluminum alloy. In the present embodiment, metal substrate 110 is an aluminum substrate. The thickness of the metal substrate 110 is, for example, 0.5 mm to 2 mm.

酸化膜１２０は、金属基板１１０の表面が酸化されてなる絶縁性の膜である。本実施の形態では、酸化膜１２０は、酸化アルミニウム（アルミナ）で構成されている。酸化膜１２０は、金属基板１１０の上面および下面を被覆している。素子搭載用基板１００の主表面を平面視したときに、半導体素子２００と重畳する領域、言い換えると半導体素子２００の下部において金属基板１１０の配線層１４０が設けられた側の主表面（金属基板１１０の上面）を被覆する酸化膜１２０（以下、この領域を酸化膜１２０ａと呼んで他の部分と区別する）の膜厚Ｈ１が当該領域の周囲の酸化膜１２０の膜厚Ｈ２より厚い。本実施の形態では、酸化膜１２０ａは半導体素子２００と重畳する領域全体に形成されているが、酸化膜１２０ａは半導体素子２００と重畳する領域の一部に形成されていてもよい。また、酸化膜１２０ａは半導体素子２００と重畳しない領域の一部を含んで形成されてもよい。   The oxide film 120 is an insulating film formed by oxidizing the surface of the metal substrate 110. In the present embodiment, oxide film 120 is made of aluminum oxide (alumina). The oxide film 120 covers the upper and lower surfaces of the metal substrate 110. When the main surface of the element mounting substrate 100 is viewed in plan, the main surface on the side where the wiring layer 140 of the metal substrate 110 is provided in the region overlapping with the semiconductor element 200, in other words, the lower part of the semiconductor element 200 (metal substrate 110 The thickness H1 of the oxide film 120 (hereinafter referred to as the oxide film 120a and distinguished from other portions) covering the upper surface of the oxide film 120 is thicker than the thickness H2 of the oxide film 120 around the region. In this embodiment, the oxide film 120 a is formed over the entire region overlapping with the semiconductor element 200, but the oxide film 120 a may be formed over part of the region overlapping with the semiconductor element 200. In addition, the oxide film 120 a may be formed to include a part of a region that does not overlap with the semiconductor element 200.

酸化膜１２０ａの膜厚Ｈ１は、酸化膜１２０ａを除く酸化膜１２０の膜厚Ｈ２に対して、例えば１．０２倍から２倍である。   The film thickness H1 of the oxide film 120a is, for example, 1.02 to 2 times the film thickness H2 of the oxide film 120 excluding the oxide film 120a.

金属基板１１０の一方の主表面側の酸化膜１２０上には、絶縁樹脂層１３０が設けられている。絶縁樹脂層１３０は、酸化膜１２０の上面上に積層されている。絶縁樹脂層１３０としては、例えばＢＴレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂が例示される。素子搭載用基板１００の放熱性向上の観点から、絶縁樹脂層１３０は高熱伝導性を有することが望ましい。このため、絶縁樹脂層１３０は、アルミナ、窒化アルミニウム、シリカ、などを高熱伝導性フィラーとして含有することが好ましい。これにより、特にパワー系半導体素子である半導体素子２００で発生した熱を効率的に放熱することができる。   An insulating resin layer 130 is provided on the oxide film 120 on one main surface side of the metal substrate 110. The insulating resin layer 130 is stacked on the upper surface of the oxide film 120. Examples of the insulating resin layer 130 include melamine derivatives such as BT resin, thermosetting resins such as liquid crystal polymers, epoxy resins, PPE resins, polyimide resins, fluororesins, phenol resins, and polyamide bismaleimides. From the viewpoint of improving the heat dissipation of the element mounting substrate 100, the insulating resin layer 130 desirably has high thermal conductivity. For this reason, the insulating resin layer 130 preferably contains alumina, aluminum nitride, silica, or the like as a highly thermally conductive filler. Thereby, especially the heat generated in the semiconductor element 200 which is a power semiconductor element can be radiated efficiently.

しかし、絶縁樹脂層１３０の厚さは、例えば、５０μｍ〜２５０μｍである。上述したように、酸化膜１２０ａの膜厚が周囲より厚くなっている分だけ、半導体素子２００の下部における絶縁樹脂層１３０の膜厚Ｈ３は、半導体素子２１０の下部における絶縁樹脂層１３０の膜厚Ｈ４より薄くなっている。   However, the thickness of the insulating resin layer 130 is, for example, 50 μm to 250 μm. As described above, the thickness H3 of the insulating resin layer 130 in the lower portion of the semiconductor element 200 is equivalent to the thickness of the insulating resin layer 130 in the lower portion of the semiconductor element 210 by the amount that the oxide film 120a is thicker than the surroundings. It is thinner than H4.

絶縁樹脂層１３０上には、配線層１４０が設けられている。配線層１４０は、例えば銅で構成され、所定の配線パターン形状を有する。配線層１４０の厚さは、例えば１０μｍ〜１５０μｍである。   A wiring layer 140 is provided on the insulating resin layer 130. The wiring layer 140 is made of copper, for example, and has a predetermined wiring pattern shape. The thickness of the wiring layer 140 is, for example, 10 μm to 150 μm.

素子搭載用基板１００の配線層１４０が形成された側の主表面上には、半導体素子２００，２１０が搭載されている。半導体素子２００，２１０は、下面側の素子電極（図示せず）が、たとえばはんだ１５０を介して配線層１４０（電極）と電気的に接続されている。はんだの換わりに金属ペースト、もしくは接着剤などを用いてもよい。また、半導体素子２００，２１０の上面側の素子電極（図示せず）は、それぞれ、たとえばアルミニウム線１５２により配線層１４０にワイヤボンディング接続されている。アルミニウム線の換わりに銅線や金線などを用いてもよい。なお、本実施の形態では、半導体素子２１０の上面側の素子電極の一つに接続されたアルミニウム線１５２と、半導体素子２００の上面側の素子電極の一つに接続されたアルミニウム線１５２とが配線層１４０の一部にともに接続されている。例えば、半導体素子２００の動作を制御するための制御信号が半導体素子２１０から半導体素子２００に送信され、半導体素子２００は当該制御信号にしたがってスイッチング動作を行う。   Semiconductor elements 200 and 210 are mounted on the main surface of the element mounting substrate 100 on the side where the wiring layer 140 is formed. In the semiconductor elements 200 and 210, element electrodes (not shown) on the lower surface side are electrically connected to the wiring layer 140 (electrodes) via solder 150, for example. A metal paste or an adhesive may be used instead of solder. In addition, element electrodes (not shown) on the upper surface side of the semiconductor elements 200 and 210 are connected to the wiring layer 140 by, for example, an aluminum wire 152 by wire bonding. A copper wire or a gold wire may be used instead of the aluminum wire. In the present embodiment, an aluminum wire 152 connected to one of the element electrodes on the upper surface side of the semiconductor element 210 and an aluminum wire 152 connected to one of the element electrodes on the upper surface side of the semiconductor element 200 are provided. Both are connected to a part of the wiring layer 140. For example, a control signal for controlling the operation of the semiconductor element 200 is transmitted from the semiconductor element 210 to the semiconductor element 200, and the semiconductor element 200 performs a switching operation according to the control signal.

（素子搭載用基板および半導体モジュールの製造方法）
実施の形態１に係る素子搭載用基板を含む半導体モジュールの製造方法について、図２（Ａ）〜図２（Ｄ）、図３（Ａ）〜図３（Ｃ）および図４（Ａ）〜図４（Ｂ）を参照して説明する。(Element mounting substrate and semiconductor module manufacturing method)
2A to FIG. 2D, FIG. 3A to FIG. 3C, and FIG. 4A to FIG. 4 regarding a method for manufacturing a semiconductor module including the element mounting substrate according to the first embodiment. This will be described with reference to 4 (B).

まず、図２（Ａ）に示すように、アルミニウムを主材料とする金属板１０９を用意する。金属板１０９は、個々の金属基板１１０に打ち抜き加工される前の大板サイズであり、例えば１００ｍｍ〜１０００ｍｍ四方の大きさである。続いて、図２（Ｂ）に示すように、上述した半導体素子２００の搭載予定領域に複数の突起部１１１を形成する。突起部１１１の高さは、例えば、０．１〜０．２ｍｍである。突起部１１１を形成する手法は特に限定されないが、例えば、プレスによる金型加工が挙げられる。   First, as shown in FIG. 2A, a metal plate 109 containing aluminum as a main material is prepared. The metal plate 109 has a large plate size before being punched into individual metal substrates 110, and has a size of, for example, 100 mm to 1000 mm square. Subsequently, as shown in FIG. 2B, a plurality of protrusions 111 are formed in the above-described region where the semiconductor element 200 is to be mounted. The height of the protrusion 111 is, for example, 0.1 to 0.2 mm. Although the method of forming the protrusion 111 is not particularly limited, for example, die processing by a press can be mentioned.

次に、図２（Ｃ）に示すように、金属板１０９を例えば硫酸溶液４００中に浸漬して、金属板１０９の表面にエッチング処理（スライトエッチング）を施す。金属板１０９に形成された突起部１１１には金属板１０９の凹凸加工の際に大きな加工歪みが発生し、結晶にダメージが加わる。そのため、突起部１１１には、金属板１０９の他の領域に比べて微小な結晶粒が多く形成される。したがって、金属板１０９の表面にエッチング処理を施すと、突起部１１１の表面に他の領域に比べてより微細な凹凸が形成される。   Next, as shown in FIG. 2C, the metal plate 109 is immersed in, for example, a sulfuric acid solution 400, and the surface of the metal plate 109 is subjected to an etching process (slight etching). The protrusion 111 formed on the metal plate 109 undergoes a large processing distortion during the uneven processing of the metal plate 109, and damages the crystal. Therefore, a lot of fine crystal grains are formed in the protrusion 111 as compared with other regions of the metal plate 109. Therefore, when the surface of the metal plate 109 is subjected to an etching process, finer irregularities are formed on the surface of the protrusion 111 than in other regions.

次に、金属板１０９の表面に酸化処理を施して酸化膜１２０を形成する。本実施の形態では、図２（Ｄ）に示すように、電源（図示せず）の正極に接続した金属板１０９を、例えばシュウ酸溶液４１０に浸漬する。また、電源の負極に接続した陰極端子４２０を金属板１０９の両主表面側にそれぞれ所定の間隔で対向配置し、シュウ酸溶液４１０に浸漬する。そして、金属板１０９に陽極酸化処理を施して、金属板１０９の表面に酸化アルミニウムからなる酸化皮膜を形成する。なお、金属板１０９の酸化処理は、中性またはアルカリ性の処理液中で陽極としての金属板１０９と陰極との間に交流を印加し、プラズマ放電（マイクロアーク）を発生させることで金属板１０９の表面を酸化するプラズマ酸化処理により行ってもよい。   Next, an oxidation process is performed on the surface of the metal plate 109 to form an oxide film 120. In this embodiment, as shown in FIG. 2D, a metal plate 109 connected to the positive electrode of a power source (not shown) is immersed in, for example, an oxalic acid solution 410. Further, the cathode terminal 420 connected to the negative electrode of the power source is disposed to face both main surface sides of the metal plate 109 at predetermined intervals, and is immersed in the oxalic acid solution 410. Then, the metal plate 109 is anodized to form an oxide film made of aluminum oxide on the surface of the metal plate 109. In the oxidation treatment of the metal plate 109, an alternating current is applied between the metal plate 109 as the anode and the cathode in a neutral or alkaline treatment solution to generate plasma discharge (micro arc), thereby generating the metal plate 109. You may carry out by the plasma oxidation process which oxidizes the surface of this.

金属板１０９の酸化処理によって、金属板１０９の表層が酸化膜１２０となる。その結果、図３（Ａ）に示すように、金属板１０９の表面が酸化膜１２０で被覆された状態となる。上述のように、金属板１０９は、突起部１１１の表面に他の領域に比べてより微細な凹凸が形成されている。したがって、突起部１１１が他の領域に比べてより酸化されやすい。そのため、突起部１１１が形成された領域には、他の領域よりも膜厚の厚い酸化膜１２０ａが形成される。   By the oxidation treatment of the metal plate 109, the surface layer of the metal plate 109 becomes the oxide film 120. As a result, the surface of the metal plate 109 is covered with the oxide film 120 as shown in FIG. As described above, the metal plate 109 is provided with finer irregularities on the surface of the protrusion 111 than in other regions. Therefore, the protrusion 111 is more easily oxidized than other regions. Therefore, an oxide film 120a having a larger film thickness than other regions is formed in the region where the protrusion 111 is formed.

次に、図３（Ｂ）に示すように、金属板１０９の上面側に設けられた酸化膜１２０上に、絶縁樹脂フィルムからなる絶縁樹脂層１３０を配置する。また、絶縁樹脂層１３０の上方に銅箔等の金属箔１４１を配置する。そして、プレス装置を用いて、金属基板１１０、絶縁樹脂層１３０および金属箔１４１を圧着する。   Next, as shown in FIG. 3B, an insulating resin layer 130 made of an insulating resin film is disposed on the oxide film 120 provided on the upper surface side of the metal plate 109. Further, a metal foil 141 such as a copper foil is disposed above the insulating resin layer 130. Then, the metal substrate 110, the insulating resin layer 130, and the metal foil 141 are pressure-bonded using a press device.

次に、図３（Ｃ）に示すように、周知のフォトリソグラフィ法およびエッチング法により、金属箔１４１を選択的に除去し、所定パターンの配線層１４０を形成する。   Next, as shown in FIG. 3C, the metal foil 141 is selectively removed by a known photolithography method and etching method to form a wiring layer 140 having a predetermined pattern.

続いて、図４（Ａ）に示すように、打ち抜き加工または切断加工により、素子搭載用基板１００に個片化する。以上の工程により、本実施の形態に係る素子搭載用基板１００が形成される。   Subsequently, as shown in FIG. 4A, the element mounting substrate 100 is separated into pieces by punching or cutting. Through the above steps, the element mounting substrate 100 according to the present embodiment is formed.

次に、図４（Ｂ）に示すように、配線層１４０上にはんだ１５０を介して半導体素子２００，２１０を搭載する。また、ワイヤボンディング法を用いて、半導体素子２００，２１０の上面側の素子電極をアルミニウム線１５２を介して配線層１４０の所定領域に電気的に接続する。以上の工程により、本実施の形態に係る半導体モジュール１が形成される。   Next, as shown in FIG. 4B, the semiconductor elements 200 and 210 are mounted on the wiring layer 140 via the solder 150. In addition, the element electrodes on the upper surface side of the semiconductor elements 200 and 210 are electrically connected to a predetermined region of the wiring layer 140 through the aluminum wire 152 by using a wire bonding method. Through the above steps, the semiconductor module 1 according to the present embodiment is formed.

以上説明したように、局所的に酸化膜１２０の膜厚を厚くすることで、熱伝導および絶縁耐圧が周囲に比べて高い領域を形成することができる。この領域の上方に発熱源となる半導体素子２００を搭載することにより、半導体素子２００の下部の放熱性と絶縁耐圧の両方を確保することができる。一方、発熱量が相対的に少ない半導体素子２１０の下部では、絶縁樹脂層１３０の厚さが半導体素子２００の下部の絶縁樹脂層１３０に比べて厚くなっている。このため、半導体素子２００で生じた熱が金属基板１１０を伝導し、さらに、半導体素子２１０に伝導することが抑制されている。したがって、半導体素子２００が発熱しても、金属基板１１０を介して半導体素子２１０が温度上昇しにくくなっている。この結果、半導体素子２１０の動作信頼性を向上させることができる。   As described above, by locally increasing the thickness of the oxide film 120, it is possible to form a region having higher heat conduction and dielectric strength than the surroundings. By mounting the semiconductor element 200 serving as a heat source above this region, it is possible to ensure both heat dissipation and dielectric strength in the lower part of the semiconductor element 200. On the other hand, in the lower part of the semiconductor element 210 that generates a relatively small amount of heat, the insulating resin layer 130 is thicker than the insulating resin layer 130 in the lower part of the semiconductor element 200. For this reason, heat generated in the semiconductor element 200 is prevented from being conducted through the metal substrate 110 and further to the semiconductor element 210. Therefore, even if the semiconductor element 200 generates heat, the temperature of the semiconductor element 210 is hardly increased through the metal substrate 110. As a result, the operational reliability of the semiconductor element 210 can be improved.

また、本実施の形態に係る半導体モジュール１は、上述した素子搭載用基板１００に半導体素子２００（パワー系半導体素子）および半導体素子２１０（制御系半導体素子）を搭載することにより、制御系半導体素子の温度上昇を引き起こすことなく、パワー系半導体素子の絶縁耐圧と放熱性の両方を確保している。このため、半導体モジュール１の動作信頼性の向上を図ることができる。   In addition, the semiconductor module 1 according to the present embodiment has a control system semiconductor element by mounting the semiconductor element 200 (power system semiconductor element) and the semiconductor element 210 (control system semiconductor element) on the element mounting substrate 100 described above. Thus, both the withstand voltage and heat dissipation of the power semiconductor element are ensured without causing a temperature rise. For this reason, the operational reliability of the semiconductor module 1 can be improved.

（実施の形態２）
図５は、実施の形態２に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。先に示した実施の形態との相違点について、以下に述べる。この実施の形態では、酸化膜１２０の膜厚が他の部分より厚い部分の表面が、他の部分の表面と同じか、もしくは他の部分の表面よりも金属基板１１０側に位置することを特徴とする。(Embodiment 2)
FIG. 5 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to the second embodiment. Differences from the above-described embodiment will be described below. In this embodiment, the surface of the part where the thickness of the oxide film 120 is thicker than the other part is the same as the surface of the other part, or is located closer to the metal substrate 110 than the surface of the other part. And

（素子搭載用基板および半導体モジュールの製造方法）
実施の形態２に係る素子搭載用基板を含む半導体モジュールの製造方法について、実施の形態１に係る素子搭載用基板を含む半導体モジュールの製造方法との相違点に関して、図６（Ａ）〜図６（Ｃ）を参照して説明する。(Element mounting substrate and semiconductor module manufacturing method)
Regarding the manufacturing method of the semiconductor module including the element mounting substrate according to the second embodiment, with respect to the difference from the manufacturing method of the semiconductor module including the element mounting substrate according to the first embodiment, FIG. A description will be given with reference to (C).

まず、図６（Ａ）に示すように、アルミウムを主材料とする金属板１０９を用意する。金属板１０９は、個々の金属基板１１０に打ち抜き加工される前の大板サイズであり、例えば１００ｍｍ〜１０００ｍｍ四方の大きさである。   First, as shown in FIG. 6A, a metal plate 109 mainly made of aluminum is prepared. The metal plate 109 has a large plate size before being punched into individual metal substrates 110, and has a size of, for example, 100 mm to 1000 mm square.

続いて、図６（Ｂ）に示すように、上述した半導体素子２００の搭載予定領域に複数の突起部１１１を形成する。突起部１１１の高さは例えば、０．１〜０．２ｍｍである。この時、突起部１１１の先端は突起部１１１の形成されない金属板１０９の表面に対して、金属板１０９側に位置する。突起部１１１を形成する手法は特に限定されないが、例えば、プレスによる金型加工が挙げられる。   Subsequently, as shown in FIG. 6B, a plurality of protrusions 111 are formed in the above-described region where the semiconductor element 200 is to be mounted. The height of the protrusion 111 is, for example, 0.1 to 0.2 mm. At this time, the tip of the protrusion 111 is positioned on the metal plate 109 side with respect to the surface of the metal plate 109 on which the protrusion 111 is not formed. Although the method of forming the protrusion 111 is not particularly limited, for example, die processing by a press can be mentioned.

以降、図６（Ｃ）に示すように、実施の形態１と同様の方法で金属板１０９の表層に酸化膜１２０を形成する。   Thereafter, as shown in FIG. 6C, an oxide film 120 is formed on the surface layer of the metal plate 109 in the same manner as in the first embodiment.

図６（Ｂ）に示した、突起部１１１の先端が突起部１１１の形成されない金属板１０９の表面に対して金属板１０９側に位置するような金属板１０９を用いることにより、図６（Ｃ）に示すような酸化膜１２０の膜厚が他の部分より厚い部分、すなわち酸化膜１２０ａの表面が、他の部分の表面と同じか、もしくは他の部分の表面よりも金属板１０９側に位置する金属板１０９を形成することができる。金属１０９は、打ち抜き加工などの個片化工程により図５に示す金属基板１１０となる。   By using the metal plate 109 shown in FIG. 6B in which the tip of the protrusion 111 is positioned on the metal plate 109 side with respect to the surface of the metal plate 109 on which the protrusion 111 is not formed, FIG. ) Where the thickness of the oxide film 120 is thicker than the other portions, that is, the surface of the oxide film 120a is the same as the surface of the other portions, or is located closer to the metal plate 109 than the surface of the other portions. The metal plate 109 to be formed can be formed. The metal 109 becomes a metal substrate 110 shown in FIG. 5 by an individualization process such as punching.

以上、説明したように、突起部１１１の先端が突起部１１１の形成されない金属基板１１０の表面に対して、金属基板１１０側に位置するように金属基板１１０に突起部１１１を設け、局所的に酸化膜１２０の膜厚を厚くすることで、酸化膜１２０の膜厚が他の部分より厚い部分である酸化膜１２０ａの表面が、他の部分の表面と同じか、もしくは他の部分の表面よりも金属基板１１０側に位置する金属基板１１０を形成することができる。   As described above, the protrusion 111 is provided on the metal substrate 110 so that the tip of the protrusion 111 is located on the metal substrate 110 side with respect to the surface of the metal substrate 110 on which the protrusion 111 is not formed. By increasing the film thickness of the oxide film 120, the surface of the oxide film 120a, which is a part where the film thickness of the oxide film 120 is thicker than the other part, is the same as the surface of the other part or more than the surface of the other part. Also, the metal substrate 110 positioned on the metal substrate 110 side can be formed.

酸化膜１２０ａの表面が、他の部分表面と同じか、もしくは他の部分の表面よりも金属基板１１０側に位置することにより、酸化膜１２０ａでは酸化膜１２０の膜が厚い分、他の部分に対して絶縁耐圧を高くすることが可能となる。また、配線層１４０側の絶縁樹脂層１３０の表面を平面にした場合に、酸化膜１２０ａでは、酸化膜１２０上の絶縁樹脂層１３０の膜厚を厚くすることが可能になり絶縁耐圧を高くすることが可能となる。以上のことにより、金属基板１１０の絶縁耐圧を向上し、絶縁破壊を抑制することが可能となることから、信頼性を向上することができる。   Since the surface of the oxide film 120a is the same as the surface of the other part, or is positioned closer to the metal substrate 110 than the surface of the other part, the oxide film 120 is thicker in the oxide film 120a, so On the other hand, the withstand voltage can be increased. Further, when the surface of the insulating resin layer 130 on the wiring layer 140 side is made flat, the oxide film 120a can increase the thickness of the insulating resin layer 130 on the oxide film 120 and increase the withstand voltage. It becomes possible. As described above, since the dielectric breakdown voltage of the metal substrate 110 can be improved and dielectric breakdown can be suppressed, reliability can be improved.

（実施の形態３）
図７は、実施の形態３に係る素子搭載用基板を含む半導体モジュールの概略構成を示す断面模式図である。図７において、半導体素子４００は青色ＬＥＤ素子、半導体素子４０１は緑色ＬＥＤ素子、半導体素子４０２は赤色ＬＥＤ素子、半導体素子４０３は白色ＬＥＤ素子である。半導体素子４１０はＬＥＤ素子を制御するために用いられる照度センサであり、半導体モジュール３００はＬＥＤモジュールである。それぞれのＬＥＤ素子は、素子ごとに分離された酸化膜１２０の膜厚が周囲より厚い部分１２０ａ１〜１２０ａ４に搭載されている。このことにより、ＬＥＤ素子の発熱が個々に分離されるので隣り合ったＬＥＤへ熱が伝わりにくく、隣り合ったＬＥＤの発熱によるＬＥＤ動作特性の影響を抑制することが可能となる。たとえば、周辺のＬＥＤの発熱により周囲温度が上昇すると光度が低下する赤色 ＬＥＤの光度低下を本構造では抑制することが可能である。また、熱に弱い照度センサを熱的に分離しつつＬＥＤ素子と同一基板に搭載することができるので、ＬＥＤモジュールの小型化が可能となる。(Embodiment 3)
FIG. 7 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module including an element mounting substrate according to the third embodiment. In FIG. 7, the semiconductor element 400 is a blue LED element, the semiconductor element 401 is a green LED element, the semiconductor element 402 is a red LED element, and the semiconductor element 403 is a white LED element. The semiconductor element 410 is an illuminance sensor used for controlling the LED element, and the semiconductor module 300 is an LED module. Each LED element is mounted on a portion 120a1 to 120a4 in which the oxide film 120 separated for each element is thicker than its surroundings. As a result, the heat generation of the LED elements is individually separated, so that heat is not easily transmitted to the adjacent LEDs, and the influence of the LED operating characteristics due to the heat generation of the adjacent LEDs can be suppressed. For example, in this structure, it is possible to suppress a decrease in luminous intensity of a red LED in which the luminous intensity decreases when the ambient temperature rises due to heat generated by the peripheral LEDs. In addition, since the illuminance sensor that is vulnerable to heat can be mounted on the same substrate as the LED element while being thermally separated, the LED module can be miniaturized.

図７には、それぞれのＬＥＤ素子が素子毎に分離された膜厚の厚い酸化膜１２０ａ１〜１２０ａ４の上方に搭載された形態を開示したが、複数のＬＥＤが素子毎に分離されていない（同一の）膜厚の厚い酸化膜、たとえば酸化膜１２０ａ１の上方に搭載されてもよい。この形態によると、個々に分離された場合と比較して放熱性の良い膜厚の厚い酸化膜１２０ａ１が大面積に形成され、モジュール全体としての放熱性が向上する効果がある。同種のＬＥＤを複数個搭載する場合には、より放熱効果が高い本形態が適している。   FIG. 7 discloses a mode in which each LED element is mounted above the thick oxide films 120a1 to 120a4 separated for each element, but a plurality of LEDs are not separated for each element (same The oxide film may be mounted above the oxide film 120a1. According to this embodiment, the thick oxide film 120a1 having a good heat dissipation property as compared with the case of being separated individually is formed in a large area, and there is an effect that the heat dissipation property of the entire module is improved. In the case where a plurality of LEDs of the same type are mounted, this embodiment having a higher heat dissipation effect is suitable.

また、図７には、ＬＥＤ素子を４つ搭載した例を示したが、ＬＥＤモジュールに搭載されるＬＥＤ素子の種類の組み合わせ及び個数はこれに限らない。また、ＬＥＤモジュールには、バリスタなどの受動素子が搭載されていてもよい。膜厚の厚い酸化膜１２０ａ１〜１２０ａ４をＬＥＤ毎に分離する形態および１つの膜厚の厚い酸化膜上に複数のＬＥＤを搭載する形態を開示したが、例えば上記のような青色／緑色／赤色／白色の各ＬＥＤを搭載したＬＥＤモジュールにおいて、赤色ＬＥＤに相当する酸化膜のみを分離し、青色／緑色／白色の各ＬＥＤは同一の厚膜酸化膜上に搭載してもよい。   Moreover, although the example which mounted four LED elements was shown in FIG. 7, the combination and number of the kind of LED element mounted in an LED module are not restricted to this. Moreover, passive elements, such as a varistor, may be mounted in the LED module. Although a mode in which the thick oxide films 120a1 to 120a4 are separated for each LED and a mode in which a plurality of LEDs are mounted on one thick oxide film have been disclosed, for example, blue / green / red / In an LED module in which each white LED is mounted, only the oxide film corresponding to the red LED may be separated, and each blue / green / white LED may be mounted on the same thick film oxide film.

本発明は、上述した実施の形態や変形例に限定されるものではなく、当業者の知識に基づいて各種の設計変更等のさらなる変形を加えることも可能であり、そのような変形が加えられた実施形態も本発明の範囲に含まれ得るものである。   The present invention is not limited to the above-described embodiments and modifications, and various modifications such as various design changes can be added based on the knowledge of those skilled in the art, and such modifications are added. Such embodiments can also be included in the scope of the present invention.

なお、本実施の形態に係る発明は、以下に記載する項目によって特定されてもよい。   The invention according to the present embodiment may be specified by the items described below.

［項目１］
金属基板と、
前記金属基板の表面が酸化されてなる酸化膜と、
前記金属基板の一方の主表面側の前記酸化膜上に設けられた絶縁樹脂層と、
前記絶縁樹脂層上に設けられた配線層と、を備え、
少なくとも一部の前記酸化膜の膜厚が他の部分の前記酸化膜の膜厚よりも厚いことを特徴とする素子搭載用基板。[Item 1]
A metal substrate;
An oxide film formed by oxidizing the surface of the metal substrate;
An insulating resin layer provided on the oxide film on one main surface side of the metal substrate;
A wiring layer provided on the insulating resin layer,
An element mounting substrate, wherein the thickness of at least a part of the oxide film is thicker than that of the other part of the oxide film.

［項目２］
前記酸化膜の膜厚が他の部分より厚い部分が発熱源となる半導体素子が搭載される搭載予定領域である項目１に記載の素子搭載用基板。[Item 2]
Item 2. The element mounting substrate according to Item 1, wherein a portion where the thickness of the oxide film is thicker than other portions is a region to be mounted on which a semiconductor element serving as a heat source is mounted.

［項目３］
前記酸化膜の膜厚が周囲より厚い部分の上に設けられた前記絶縁樹脂層の膜厚が他の部分の前記絶縁樹脂層の膜厚より薄い部分を有する項目１または２に記載の素子搭載用基板。[Item 3]
3. The element mounting according to item 1 or 2, wherein the insulating resin layer provided on a portion where the thickness of the oxide film is thicker than the surroundings has a portion where the thickness of the insulating resin layer is thinner than that of the other portion. Substrate.

［項目４］
前記酸化膜の膜厚が他の部分より厚い部分の表面が、他の部分の表面と同じか、もしくは他の部分の表面よりも金属基板側に位置する項目１または２に記載の素子搭載用基板。[Item 4]
3. The element mounting according to item 1 or 2, wherein a surface of a portion where the film thickness of the oxide film is thicker than that of the other portion is the same as the surface of the other portion, or is located closer to the metal substrate than the surface of the other portion. substrate.

［項目５］
前記酸化膜の膜厚が他より厚い部分において、前記金属基板の一方の主表面に凹凸が形成されている項目１乃至４のいずれか１項に記載の素子搭載用基板。[Item 5]
5. The element mounting substrate according to any one of items 1 to 4, wherein an unevenness is formed on one main surface of the metal substrate in a portion where the film thickness of the oxide film is thicker than the others.

［項目６］
請求項１乃至５のいずれか１項にに記載の素子搭載用基板と、
前記素子搭載用基板の前記配線層が形成された側の主表面上に搭載され、前記配線層と電気的に接続された半導体素子と、
を備えたことを特徴とする半導体モジュール。[Item 6]
The element mounting substrate according to any one of claims 1 to 5,
A semiconductor element mounted on the main surface of the element mounting substrate on which the wiring layer is formed and electrically connected to the wiring layer;
A semiconductor module comprising:

［項目７］
金属基板の所定領域に突起部を形成する工程と、
前記金属基板の表面に酸化処理を施して酸化膜を形成する工程と、
前記酸化膜上に絶縁樹脂層を積層する工程と、
前記絶縁樹脂層上に金属層を積層し、当該金属層を選択的に除去して配線層を形成する工程と、
を含むことを特徴とする素子搭載用基板の製造方法。[Item 7]
Forming a protrusion in a predetermined region of the metal substrate;
Forming an oxide film by oxidizing the surface of the metal substrate;
Laminating an insulating resin layer on the oxide film;
Laminating a metal layer on the insulating resin layer and selectively removing the metal layer to form a wiring layer;
A method for manufacturing an element mounting board, comprising:

［項目８］
前記酸化処理は、陽極酸化処理である項目７に記載の素子搭載用基板の製造方法。[Item 8]
8. The element mounting substrate manufacturing method according to item 7, wherein the oxidation treatment is an anodic oxidation treatment.

１ 半導体モジュール、１００ 素子搭載用基板、１０９ 金属板、１１０ 金属基板、１１１ 突起部、１２０ 酸化膜、１３０ 絶縁樹脂層、１４０ 配線層、１４１ 金属箔、２００，２１０ 半導体素子。 DESCRIPTION OF SYMBOLS 1 Semiconductor module, 100 element mounting substrate, 109 metal plate, 110 metal substrate, 111 protrusion part, 120 oxide film, 130 insulating resin layer, 140 wiring layer, 141 metal foil, 200,210 semiconductor element.

本発明は、素子搭載用基板、半導体モジュールおよび素子搭載用基板の製造方法に利用される。   The present invention is used in an element mounting substrate, a semiconductor module, and a method for manufacturing an element mounting substrate.

Claims (7)

金属基板と、
前記金属基板の表面が酸化されてなる酸化膜と、
前記金属基板の一方の主表面側の前記酸化膜上に設けられた絶縁樹脂層と、
前記絶縁樹脂層上に設けられた配線層と、を備え、
少なくとも一部の前記酸化膜の膜厚が他の部分の前記酸化膜の膜厚よりも厚く、
前記酸化膜の膜厚が他より厚い部分において、前記金属基板の一方の主表面に凹凸が形成されていることを特徴とする素子搭載用基板。 A metal substrate;
An oxide film formed by oxidizing the surface of the metal substrate;
An insulating resin layer provided on the oxide film on one main surface side of the metal substrate;
A wiring layer provided on the insulating resin layer,
Thickness of at least a portion of the oxide film rather thickness than the thickness of the oxide film of the other part,
An element mounting substrate, wherein an unevenness is formed on one main surface of the metal substrate in a portion where the thickness of the oxide film is thicker than the others . 発熱量の異なる複数個の半導体素子の搭載に用いられ、
前記酸化膜の膜厚が他の部分より厚い部分が前記複数個の半導体素子のうち、発熱量が相対的に大きい半導体素子が搭載される搭載予定領域である請求項１に記載の素子搭載用基板。 Used for mounting multiple semiconductor elements with different calorific values,
2. The element mounting area according to claim 1, wherein a portion where the film thickness of the oxide film is thicker than other portions is a mounting region in which a semiconductor element having a relatively large calorific value is mounted among the plurality of semiconductor elements. substrate. 前記酸化膜の膜厚が周囲より厚い部分の上に設けられた前記絶縁樹脂層の膜厚が他の部分の前記絶縁樹脂層の膜厚より薄い部分を有する請求項１または２に記載の素子搭載用基板。   3. The element according to claim 1, wherein a film thickness of the insulating resin layer provided on a portion where the film thickness of the oxide film is thicker than a surrounding area has a portion thinner than a film thickness of the insulating resin layer in another portion. Mounting board. 前記酸化膜の膜厚が他の部分より厚い部分の表面が、他の部分の表面と同じか、もしくは他の部分の表面よりも金属基板側に位置する請求項１または２に記載の素子搭載用基板。   3. The element mounting according to claim 1, wherein a surface of a portion where the film thickness of the oxide film is thicker than that of another portion is the same as a surface of the other portion, or is located closer to the metal substrate than a surface of the other portion. Substrate. 請求項１乃至４のいずれか１項に記載の素子搭載用基板と、
前記素子搭載用基板の前記配線層が形成された側の主表面上に搭載され、前記配線層と電気的に接続された半導体素子と、
を備えたことを特徴とする半導体モジュール。 A device mounting board mounting serial to any one of claims 1 to 4,
A semiconductor element mounted on the main surface of the element mounting substrate on which the wiring layer is formed and electrically connected to the wiring layer;
A semiconductor module comprising: 金属基板の所定領域に突起部を形成する工程と、
前記金属基板の表面に酸化処理を施して、前記突起部が形成された領域の膜厚が他の領域の膜厚よりも厚い酸化膜を形成する工程と、
前記酸化膜上に絶縁樹脂層を積層する工程と、
前記絶縁樹脂層上に金属層を積層し、当該金属層を選択的に除去して配線層を形成する工程と、
を含むことを特徴とする素子搭載用基板の製造方法。 Forming a protrusion in a predetermined region of the metal substrate;
Performing an oxidation treatment on the surface of the metal substrate to form an oxide film in which the thickness of the region where the protrusion is formed is thicker than the thickness of the other region ;
Laminating an insulating resin layer on the oxide film;
Laminating a metal layer on the insulating resin layer and selectively removing the metal layer to form a wiring layer;
A method for manufacturing an element mounting board, comprising: 前記酸化処理は、陽極酸化処理である請求項６に記載の素子搭載用基板の製造方法。 The method for manufacturing an element mounting substrate according to claim 6 , wherein the oxidation treatment is an anodic oxidation treatment.
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