JP2008205083A - Semiconductor device and strap for extracting electrode - Google Patents

Semiconductor device and strap for extracting electrode Download PDF

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Publication number
JP2008205083A
JP2008205083A JP2007037695A JP2007037695A JP2008205083A JP 2008205083 A JP2008205083 A JP 2008205083A JP 2007037695 A JP2007037695 A JP 2007037695A JP 2007037695 A JP2007037695 A JP 2007037695A JP 2008205083 A JP2008205083 A JP 2008205083A
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conductor
lead
semiconductor device
electrode
semiconductor element
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Yoshihiro Yamaguchi
好広 山口
Yusuke Kawaguchi
雄介 川口
Miwako Akiyama
誠和子 秋山
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Toshiba Corp
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Toshiba Corp
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Priority to JP2007037695A priority Critical patent/JP2008205083A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device enabling a switching operation at a high speed by reducing a parasitic inductance and a strap for an extracting electrode. <P>SOLUTION: The semiconductor device has a first lead, a second lead, a semiconductor element mounted on the first lead and the extracting electrode connecting the semiconductor element and the second lead. In the semiconductor device, the extracting electrode has a first conductor electrically connecting the semiconductor element and the second lead, a second conductor electrically insulated from the first conductor and an insulating layer formed between the first conductor and the second conductor. Such a semiconductor device is provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置および取出し電極用ストラップに関し、詳しくは、主電極からの取出し電極を改良した半導体装置および取出し電極用ストラップに関する。   The present invention relates to a semiconductor device and an extraction electrode strap, and more particularly to a semiconductor device and an extraction electrode strap with an improved extraction electrode from a main electrode.

パワーＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field Effect Transistor）などの半導体装置は、リードフレームにＭＯＳＦＥＴなどの半導体素子がマウントされ、ゲートが反対側のリードフレームにワイヤー・ボンディングされ、ソースが反対側のリードフレームにリボン状の取出し電極（アルミストラップ）で接続された構造を有する。このようなパワーＭＯＳＦＥＴのドレイン・ソース端子間の寄生インダクタンスは、ほぼアルミストラップの大きさで決定され、大きくするほど寄生インダクタンスは小さくなる。
しかし、アルミストラップの大きさは、チップサイズで決められるため、寄生インダクタンスの低減には限度があった。 A semiconductor device such as a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has a lead frame on which a semiconductor element such as a MOSFET is mounted, a gate is wire-bonded to the opposite lead frame, and a source is the opposite lead frame. And a ribbon-shaped extraction electrode (aluminum strap). The parasitic inductance between the drain and source terminals of such a power MOSFET is substantially determined by the size of the aluminum strap, and the parasitic inductance decreases as the power MOSFET increases.
However, since the size of the aluminum strap is determined by the chip size, there is a limit to reducing the parasitic inductance.

なお、単位長さ当りのインダクタンス値の大きい配線を折り返し構造とし、インダクタンス値の大きい配線に対し別の層に渦電流パターンを形成するようにしたプラズマディスプレイが開示されている（例えば、特許文献１参照）。
また、金属ストラップを半導体チップにボンディングするストラップボンディング方法が開示されている（例えば、特許文献２参照）。
特開２００１−３５８４１２号公報 特開２００６−３２８７３号公報 In addition, a plasma display is disclosed in which a wiring having a large inductance value per unit length has a folded structure and an eddy current pattern is formed in another layer with respect to the wiring having a large inductance value (for example, Patent Document 1). reference).
Also, a strap bonding method for bonding a metal strap to a semiconductor chip is disclosed (for example, see Patent Document 2).
JP 2001-358411 A JP 2006-32873 A

本発明の目的は、寄生インダクタンスを低減させて、高速スイッチング動作を可能とした半導体装置及び取出し電極用ストラップを提供することにある。   An object of the present invention is to provide a semiconductor device and a lead-out electrode strap which can reduce the parasitic inductance and enable high-speed switching operation.

本発明の一態様によれば、第１のリードと、第２のリードと、前記第１のリードにマウントされた半導体素子と、前記半導体素子と前記第２のリードとを接続する取り出し電極と、を備え、前記取り出し電極は、前記半導体素子と前記第２のリードとを電気的に接続する第１の導体と、前記第１の導体と電気的に絶縁された第２の導体と、前記第１の導体と前記第２の導体との間に設けられた絶縁層と、を有することを特徴とする半導体装置が提供される。   According to one aspect of the present invention, a first lead, a second lead, a semiconductor element mounted on the first lead, and an extraction electrode that connects the semiconductor element and the second lead The extraction electrode includes a first conductor that electrically connects the semiconductor element and the second lead, a second conductor that is electrically insulated from the first conductor, and the There is provided a semiconductor device comprising an insulating layer provided between a first conductor and the second conductor.

また、本発明の他の一態様によれば、第１の主面に設けられた第１の電極と、前記第１の主面に対向する第２の主面に設けられた第２の電極と、を有する半導体素子と、前記第１の電極に一端が接続された第１のリードと、前記第１のリードの他端と、前記第２の電極と、を露出させつつ前記半導体素子と前記第１のリードとを覆う絶縁体と、前記絶縁体を介して前記第１のリードの前記一端と対向する導体と、を備えたことを特徴とする半導体装置が提供される。   According to another aspect of the present invention, the first electrode provided on the first main surface and the second electrode provided on the second main surface facing the first main surface A semiconductor element including: a first lead having one end connected to the first electrode; the other end of the first lead; and the second electrode. There is provided a semiconductor device comprising: an insulator that covers the first lead; and a conductor that faces the one end of the first lead with the insulator interposed therebetween.

また、本発明の他の一態様によれば、半導体素子とリードとを接続する取出し電極用ストラップであって、少なくとも一対の金属リボンテープが絶縁層を挟んで積層されたことを特徴とする取出し電極用ストラップが提供される。   According to another aspect of the present invention, there is provided an extraction electrode strap for connecting a semiconductor element and a lead, wherein at least a pair of metal ribbon tapes are stacked with an insulating layer interposed therebetween. An electrode strap is provided.

本発明によれば、寄生インダクタンスを低減させて、高速スイッチング動作を可能とした半導体装置及び取出し電極用ストラップを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the parasitic inductance can be reduced and the semiconductor device and extraction electrode strap which enabled high-speed switching operation can be provided.

以下、本発明の半導体装置の実施形態を図面に基いて説明する。
図１は、本発明の第１実施形態の半導体装置の要部構成を表す斜視図であり、 図２は、図１のII−II線断面図である。 Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the drawings.
FIG. 1 is a perspective view illustrating a configuration of a main part of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG.

この半導体装置１０は、半導体素子としてパワーＭＯＳＦＥＴを使用した例を示しており、ＭＯＳＦＥＴ１３の上面にはソース電極１３Ｓおよびゲート電極１３Ｇが設けられ、下面にはドレイン電極１３Ｄが設けられている。この半導体装置１０は、互いに対向する第１のリードフレーム１１および第２のリードフレーム１２を有し、第１のリードフレーム１１にＭＯＳＦＥＴ１３を半田または導電性接着剤でマウントすることにより、ＭＯＳＦＥＴ１３のドレイン電極１３Ｄとドレイン端子１４とが電気的に接続されている。ＭＯＳＦＥＴ１３のゲート電極１３Ｇとゲート端子１５とはボンディングワイヤ１６で接続されている。さらに、ＭＯＳＦＥＴ１３のソース電極１３Ｓと第２のリードフレーム１２とが取出し電極２０で接続され、ソース電極１３Ｓとソース端子１７が電気的に接続されている。   This semiconductor device 10 shows an example in which a power MOSFET is used as a semiconductor element. A source electrode 13S and a gate electrode 13G are provided on the upper surface of the MOSFET 13, and a drain electrode 13D is provided on the lower surface. The semiconductor device 10 has a first lead frame 11 and a second lead frame 12 facing each other, and the MOSFET 13 is mounted on the first lead frame 11 with solder or a conductive adhesive, so that the drain of the MOSFET 13 can be obtained. The electrode 13D and the drain terminal 14 are electrically connected. The gate electrode 13G of the MOSFET 13 and the gate terminal 15 are connected by a bonding wire 16. Further, the source electrode 13S of the MOSFET 13 and the second lead frame 12 are connected by the extraction electrode 20, and the source electrode 13S and the source terminal 17 are electrically connected.

取出し電極２０は、下層の第１の導体２１と上層の第２の導体２２とが絶縁層２３を介して積層された構成を有する。各導体２１、２２は、例えばアルミニウムや銅の薄板であり、絶縁層２３の材料としては例えば電気絶縁性の樹脂を用いることができる。そのような樹脂としては、例えば、ポリイミド、エポキシ樹脂、フェノール樹脂、シリコーン樹脂、シリコンゴム、ポリエチレン、ポリ塩化ビニル、ナイロン、ポリカーボネート、フッ素樹脂、カプトンをはじめとした各種のものを用いることができる。また、樹脂以外にも、例えばシリケートガラスやその他酸化物や窒化物などの無機材料を用いてもよい。
この取出し電極２０は、両端に段落ちした接続部２０ａ、２０ｂが形成された側面略凸形状の成型品である。そして、第１の導体２１の一端の接続部２０ａはＭＯＳＦＥＴ１３のソース電極に接続され、他端の接続部２０ｂは第２のリードフレーム１２に接続されている。第２の導体２２はフローティング状態になっている。ＭＯＳＦＥＴ１３および取出し電極２０はモールド樹脂２５により封止されて、半導体装置１０のパッケージを構成している。なお、図１においては、モールド樹脂２５を省略して表した。 The extraction electrode 20 has a configuration in which a lower first conductor 21 and an upper second conductor 22 are laminated via an insulating layer 23. Each of the conductors 21 and 22 is, for example, a thin plate made of aluminum or copper. Examples of such a resin include various resins including polyimide, epoxy resin, phenol resin, silicone resin, silicon rubber, polyethylene, polyvinyl chloride, nylon, polycarbonate, fluororesin, and Kapton. In addition to the resin, for example, silicate glass or other inorganic materials such as oxides and nitrides may be used.
The extraction electrode 20 is a molded product having a substantially convex shape on the side surface in which connecting portions 20a and 20b are formed at both ends. The connection portion 20 a at one end of the first conductor 21 is connected to the source electrode of the MOSFET 13, and the connection portion 20 b at the other end is connected to the second lead frame 12. The second conductor 22 is in a floating state. The MOSFET 13 and the extraction electrode 20 are sealed with a mold resin 25 to constitute a package of the semiconductor device 10. In FIG. 1, the mold resin 25 is omitted.

ＭＯＳＦＥＴ１３がオンすると、図２に示すように、矢印Ａの方向、すなわち、ソース電極１３Ｓからソース端子１５方向の電流が第１の導体２１を流れる。そうすると、相互誘導作用により第２の導体２２に矢印Ｂで示すような逆向きの誘導電流（渦電流）が流れる。この誘電電流による相互インダクタンスによって、第１の導体２１の実効インダクタンスが減少する。このインダクタンスが減少する効果は、絶縁層２３の厚さが薄いほど良く、後に詳述するように１００マイクロメータ以下とすることが望ましい。
このように取り出し電極２０の寄生インダクタンスを低減することにより、半導体装置のスイッチング速度を向上させることができる。つまり、高速動作が可能な半導体装置を提供できる。また同時に、本実施形態によれば、半導体装置のターンオンロスを抑制できる。
図３は、ＭＯＳＦＥＴ１３の取出し電極２０のインダクタンス（ｎＨ）とターンオンロス（Ｊ：ジュール）との関係を計算により求めた結果を表すグラフ図である。なお、ターンオンロスは、ドレイン・ソース間の電流×電圧を時間積分することにより求めた。
図３において、直線Ａは電流を５アンペア、直線Ｂは電流を２０アンペアとしたときのインダクタンスとターンオンロスとの関係を示す。図３から明らかなように、インダクタンスが小さいほどターンオンロスが小さくなる。したがって、積層構造によりインダクタンスの低下を図った取出し電極２０を設けた本実施形態の半導体装置は、ターンオンロスを低下させることができる。 When the MOSFET 13 is turned on, a current in the direction of arrow A, that is, in the direction from the source electrode 13S to the source terminal 15 flows through the first conductor 21, as shown in FIG. Then, a reverse induced current (eddy current) as indicated by an arrow B flows through the second conductor 22 by the mutual induction action. Due to the mutual inductance due to the dielectric current, the effective inductance of the first conductor 21 is reduced. The effect of reducing the inductance is better as the insulating layer 23 is thinner, and it is desirable that the inductance be 100 micrometers or less as described in detail later.
In this way, by reducing the parasitic inductance of the extraction electrode 20, the switching speed of the semiconductor device can be improved. That is, a semiconductor device capable of high-speed operation can be provided. At the same time, according to the present embodiment, the turn-on loss of the semiconductor device can be suppressed.
FIG. 3 is a graph showing the result of calculating the relationship between the inductance (nH) of the extraction electrode 20 of the MOSFET 13 and the turn-on loss (J: Joule). The turn-on loss was obtained by time integration of drain-source current × voltage.
In FIG. 3, the straight line A shows the relationship between the inductance and the turn-on loss when the current is 5 amperes and the straight line B is 20 amperes. As is clear from FIG. 3, the smaller the inductance, the smaller the turn-on loss. Therefore, the turn-on loss can be reduced in the semiconductor device of this embodiment provided with the extraction electrode 20 in which the inductance is reduced by the laminated structure.

第１の導体２１と第２の導体２２を絶縁層２３を介して積層した配線構造においては、両導体２１、２２間の間隔が小さくなるほど配線インダクタンスが小さくなる。そして、導体２１、２２間の間隔が１００マイクロメータを下回ると、配線インダクタンスは概ね一定となる。例えば、導体２１、２２間の間隔が１０ｍｍで配線インダクタンスが約０．５ｎＨ（ナノヘンリー）であるとすると、間隔を１００マイクロメータにするとインダクタンスは約０．０５ｎＨとなり、約１０分の１に低下する。そして、導体２１、２２の間隔をこれ以下に狭めても配線インダクタンスはほぼ横ばい、すなわち０．０５ｎＨ程度である。したがって、導体間の間隔は１００マイクロメータ以下とすることが望ましい。   In the wiring structure in which the first conductor 21 and the second conductor 22 are laminated via the insulating layer 23, the wiring inductance decreases as the distance between the two conductors 21 and 22 decreases. And if the space | interval between the conductors 21 and 22 is less than 100 micrometers, wiring inductance will become substantially constant. For example, if the spacing between the conductors 21 and 22 is 10 mm and the wiring inductance is about 0.5 nH (nanohenry), the inductance becomes about 0.05 nH when the spacing is set to 100 micrometers, which is reduced to about 1/10. To do. And even if the space | interval of the conductors 21 and 22 is narrowed below this, a wiring inductance is substantially flat, ie, about 0.05 nH. Therefore, it is desirable that the distance between the conductors be 100 micrometers or less.

図４は、本発明の第２実施形態の半導体装置の要部構成を表す断面図であり、図１のII−II線断面に対応する断面図である。
本実施形態では、第２の導体２２を第１実施形態のものよりも短くし、第２の導体２２の端部を第１の導体２１の接続部２０ａ、２０ｂよりも内端寄りに設けている。本実施形態では、第１の導体２１の接続部２０ａ、２０ｂの上部には絶縁層２３および第１の導体２２が除去されている構造であるので、接続部２０ａ、２０ｂを超音波ボンディングや熱圧着あるいは半田付け等によりＭＯＳＦＥＴのソース電極に接続しても、絶縁層２３が破壊（または溶融）して導体２０ａと導体２０ｂとが接触するおそれがない。その結果として、相互誘導作用による寄生インダクタンスの低減効果を確実に得ることができる。 FIG. 4 is a cross-sectional view showing a main part configuration of a semiconductor device according to the second embodiment of the present invention, and is a cross-sectional view corresponding to a cross section taken along line II-II in FIG.
In the present embodiment, the second conductor 22 is made shorter than that of the first embodiment, and the end portion of the second conductor 22 is provided closer to the inner end than the connection portions 20a and 20b of the first conductor 21. Yes. In the present embodiment, since the insulating layer 23 and the first conductor 22 are removed from the upper portions of the connection portions 20a and 20b of the first conductor 21, the connection portions 20a and 20b are connected by ultrasonic bonding or heat. Even if it is connected to the source electrode of the MOSFET by crimping or soldering, there is no possibility that the insulating layer 23 is broken (or melted) and the conductor 20a and the conductor 20b come into contact with each other. As a result, it is possible to reliably obtain the effect of reducing the parasitic inductance due to the mutual induction action.

図５は、本発明の第３実施形態の半導体装置の要部構成を表す断面図であり、図１のII−II線断面に対応する断面図である。
本実施形態では、第２の導体２２を絶縁層２３を介して第１の導体２１の上部に積層するとともに、第２の導体２２に対向するように、第１の導体２１の下面に絶縁層２８を介して第３の導体２９を設けている。つまり、第１の導体２１の上下にそれぞれ絶縁層２３、２８を挟んで導体２２、２９が設けられている。 FIG. 5 is a cross-sectional view showing a main part configuration of a semiconductor device according to the third embodiment of the present invention, and is a cross-sectional view corresponding to a cross section taken along line II-II in FIG.
In the present embodiment, the second conductor 22 is laminated on the upper portion of the first conductor 21 via the insulating layer 23, and the insulating layer is formed on the lower surface of the first conductor 21 so as to face the second conductor 22. A third conductor 29 is provided via 28. That is, the conductors 22 and 29 are provided above and below the first conductor 21 with the insulating layers 23 and 28 interposed therebetween, respectively.

このようにすると、第１の導体２１にソース電流を流した時に、第２の導体２２と第３の導体２９の両方で相互誘導作用による誘導電流が流れ、その相互インダクタンスにより第１の導体２１に発生する磁束を打ち消すことができる。   In this way, when a source current is passed through the first conductor 21, an induced current due to mutual induction flows in both the second conductor 22 and the third conductor 29, and the first conductor 21 is caused by the mutual inductance. It is possible to cancel the magnetic flux generated in the.

図６は、本発明の第４実施形態の半導体装置の要部構成を表す断面図であり、図１のII−II線断面に対応する断面図である。
本実施形態では、第２の導体２２をモールド樹脂２５の表面に露出させ、放熱板２６としても機能させる。すなわち、絶縁層２３の上面を平坦面とし、この上に第２の導体２２を積層する。第２の導体２２の面積を大きくし、また厚みも比較的大きくすると、放熱効果が向上する。こうすることにより、寄生インダクタンスの低減効果と、放熱効果の両方を得ることができる。第１実施形態に関して前述したように、相互誘導電流による寄生インダクタンス低減効果を得るためには、絶縁層２３の厚さは薄いほど良く、数μｍ〜数十μｍにすることが望ましい。絶縁層２３がこの程度の厚みである場合には、熱伝導の損失も低減し、ＭＯＳＦＥＴ１３において発生した熱を第１の導体２１から絶縁層２３を介して第２の導体２２に効率的に放出させることが可能となる。 FIG. 6 is a cross-sectional view showing a main part configuration of a semiconductor device according to the fourth embodiment of the present invention, and is a cross-sectional view corresponding to a cross section taken along line II-II in FIG.
In the present embodiment, the second conductor 22 is exposed on the surface of the mold resin 25 and functions as the heat sink 26. That is, the upper surface of the insulating layer 23 is a flat surface, and the second conductor 22 is laminated thereon. When the area of the second conductor 22 is increased and the thickness is relatively increased, the heat dissipation effect is improved. By doing so, it is possible to obtain both a parasitic inductance reduction effect and a heat dissipation effect. As described above with respect to the first embodiment, in order to obtain the effect of reducing the parasitic inductance due to the mutual induction current, the thickness of the insulating layer 23 is preferably as small as possible and is preferably several μm to several tens of μm. When the insulating layer 23 has such a thickness, the heat conduction loss is also reduced, and the heat generated in the MOSFET 13 is efficiently released from the first conductor 21 to the second conductor 22 through the insulating layer 23. It becomes possible to make it.

図７（ａ）は、本発明の第５実施形態の半導体装置の要部構成を表す斜視図であり、図７（ｂ）は、図７（ａ）のｂ−ｂ線断面図である。
本発明の第５実施形態を示す。 FIG. 7A is a perspective view showing a main part configuration of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along the line bb of FIG. 7A.
5 shows a fifth embodiment of the present invention.

第５実施形態では、第１および第２のリードフレーム１１、１２の上面および両者の間隙部分にモールド樹脂３０を設け、各リードフレーム１１、１２の下方にＭＯＳＦＥＴ１３が設けられている。ＭＯＳＦＥＴ１３のソース電極１３Ｓと第１のリードフレーム１１とが半田３１で接続され、ソース電極１３Ｓとソース端子１７が電気的に接続されている。また、ＭＯＳＦＥＴ１３のゲート電極１３Ｇと第２のリードフレーム１２とが半田３２で接続され、ゲート電極１３Ｇとゲート端子１５が電気的に接続されている。モールド樹脂３０の上面には、放熱板３３を兼ねた第２の導体２２を積層されている。本実施形態では、第１のリードフレーム１１が第１の導体を兼ねている。すなわち、ソース電流が第１のリードフレーム１１を流れると、モールド樹脂３０を介して第２の導体２２に誘導電流（渦電流）が流れる。この誘導電流による相互インダクタンスにより第１のリードフレーム１１の実効インダクタンスが低減する。   In the fifth embodiment, the mold resin 30 is provided on the upper surfaces of the first and second lead frames 11 and 12 and the gaps between them, and the MOSFET 13 is provided below the lead frames 11 and 12. The source electrode 13S of the MOSFET 13 and the first lead frame 11 are connected by the solder 31, and the source electrode 13S and the source terminal 17 are electrically connected. Further, the gate electrode 13G of the MOSFET 13 and the second lead frame 12 are connected by the solder 32, and the gate electrode 13G and the gate terminal 15 are electrically connected. On the upper surface of the mold resin 30, the second conductor 22 that also serves as the heat radiating plate 33 is laminated. In the present embodiment, the first lead frame 11 also serves as the first conductor. That is, when a source current flows through the first lead frame 11, an induced current (eddy current) flows through the second resin 22 through the mold resin 30. The effective inductance of the first lead frame 11 is reduced by the mutual inductance caused by the induced current.

またさらに、本実施形態においては、第２の導体２２が放熱板３３を兼ねることにより、ＭＯＳＦＥＴ１３において生じた熱を上方に効率的に放散させることができる。なお、ＭＯＳＦＥＴ１３は、そのドレイン電極１３Ｄが図示しない実装基板などに直接、マウントされるので、ドレイン電極１３Ｄを介して実装基板の側にも高い効率で放熱することが可能となる。   Furthermore, in the present embodiment, the second conductor 22 also serves as the heat radiating plate 33, so that the heat generated in the MOSFET 13 can be efficiently dissipated upward. Since the drain electrode 13D of the MOSFET 13 is directly mounted on a mounting substrate (not shown) or the like, it is possible to dissipate heat to the mounting substrate side through the drain electrode 13D with high efficiency.

なお、上述した各実施形態に関しては、半導体素子としてＭＯＳＦＥＴ１３を用いた具体例を説明したが、本発明はこれには限定されず、トランジスタ、ＩＧＢＴ、ダイオード、サイリスタをはじめとする各種の半導体素子を用いることができる。   In addition, regarding each embodiment mentioned above, although the specific example using MOSFET13 as a semiconductor element was demonstrated, this invention is not limited to this, Various semiconductor elements including a transistor, IGBT, a diode, a thyristor are included. Can be used.

また、取出し電極２０についても、第１の導体２１と第２の導体２２を絶縁層２３を介して積層した３層構造を例示したが、導体と絶縁層とを交互に積層させた５層以上の任意の多層構造であってよい。   The take-out electrode 20 is also exemplified by a three-layer structure in which the first conductor 21 and the second conductor 22 are laminated via the insulating layer 23, but five or more layers in which conductors and insulating layers are alternately laminated. Any multilayer structure may be used.

図８は、絶縁層２３に代えて、第１の導体２１と第２の導体２２との間に空隙３８を設けた取り出し電極を例示する断面図である。すなわち、本具体例の場合、空隙３８をもって絶縁層としている。空隙３８を設けるには、第１の導体２１と第２の導体２２の間の数箇所に絶縁層からなるスペーサ３９を配置すればよい。   FIG. 8 is a cross-sectional view illustrating an extraction electrode in which a gap 38 is provided between the first conductor 21 and the second conductor 22 instead of the insulating layer 23. That is, in this specific example, the gap 38 is used as the insulating layer. In order to provide the air gap 38, spacers 39 made of an insulating layer may be disposed at several positions between the first conductor 21 and the second conductor 22.

図９は、可撓性のあるストラップ状の取出し電極を表す斜視図である。   FIG. 9 is a perspective view showing a flexible strap-shaped extraction electrode.

図９において、２枚のアルミニウムや銅等の金属薄板からなる長尺金属リボン４０、４１を絶縁層４２を介して積層した長尺の積層導体リボンテープ４４を作成し、この積層導体リボンテープ４４を半導体装置に合わせて最適の寸法に切断することにより、取出し電極用のストラップ４５を製作する。なお、必要に応じて中央部に湾曲部４６を形成しておくことにより、モールド樹脂との密着性を向上させることができる。または、図２などに例示したように、積層導体リボンテープをプレスなどで屈曲状に成形してもよい。   In FIG. 9, a long laminated conductor ribbon tape 44 is prepared by laminating long metal ribbons 40 and 41 made of a thin metal plate such as aluminum or copper via an insulating layer 42, and this laminated conductor ribbon tape 44. Is cut into an optimum dimension according to the semiconductor device, thereby producing a strap 45 for the extraction electrode. In addition, adhesiveness with mold resin can be improved by forming the curved part 46 in the center part as needed. Alternatively, as illustrated in FIG. 2 and the like, the laminated conductor ribbon tape may be formed into a bent shape by a press or the like.

この取出し電極用ストラップ４５は、長尺の積層導体リボンテープ４４を切断することにより製作が可能であり、簡単な工程で低コストで取出し電極ストラップ４５を製造することができるとともに、半導体装置に合わせて任意の寸法に切断することができるので、汎用性に優れる。このような取出し電極用ストラップ４５を用いることにより、ストラップボンディング装置により自動ボンディングが可能になる（特許文献２参照）。   The extraction electrode strap 45 can be manufactured by cutting a long laminated conductor ribbon tape 44. The extraction electrode strap 45 can be manufactured by a simple process at a low cost, and can be manufactured in accordance with a semiconductor device. And can be cut to any size. By using such an extraction electrode strap 45, automatic bonding can be performed by a strap bonding apparatus (see Patent Document 2).

図１０は、ＭＯＳＦＥＴ１３、リードフレーム１１、１２および取出し電極２０を有する一般的な半導体装置を比較例として表した斜視図である。   FIG. 10 is a perspective view showing, as a comparative example, a general semiconductor device having the MOSFET 13, the lead frames 11, 12 and the extraction electrode 20. As shown in FIG.

同図に示すように、一般の半導体装置では、取出し電極２０は１枚の導体で構成されているため、寄生インダクタンスが大きくなる。   As shown in the figure, in a general semiconductor device, since the extraction electrode 20 is composed of a single conductor, the parasitic inductance is increased.

図１１は、上記半導体装置を使用したスイッチング回路を表す模式図である。
同図において、１はＭＯＳＦＥＴ、２は負荷、３は主電源、４はソース取出し電極の寄生インダクタンスを示している。ＭＯＳＦＥＴ１のゲートがオンするとドレイン−ソース間に電流が流れ、ソースの寄生インダクタンス４に流れる電流Ｉにより電圧Ｖが発生する。この電圧Ｖはゲート電圧を下げるように働き、このため、ゲートのオン抵抗が高くなるとともに、ゲート電圧の低下に伴ってターンオンの時間が長くなり、スイッチング損失が大きくなるという問題が生じていた。したがって、寄生インダクタンスはできるだけ小さくすることが望まれている。 FIG. 11 is a schematic diagram illustrating a switching circuit using the semiconductor device.
In the figure, 1 is a MOSFET, 2 is a load, 3 is a main power supply, and 4 is a parasitic inductance of a source extraction electrode. When the gate of the MOSFET 1 is turned on, a current flows between the drain and the source, and a voltage V is generated by the current I flowing through the parasitic inductance 4 of the source. This voltage V works to lower the gate voltage, which increases the on-resistance of the gate, lengthens the turn-on time as the gate voltage decreases, and increases the switching loss. Therefore, it is desired to reduce the parasitic inductance as much as possible.

これに対して、本実施形態によれば、上述したように、ＭＯＳＦＥＴ１３のソース電極とパッケージのソース端子１５を接続する取出し電極２０を、絶縁層２３または空隙３８を介して積層した多層構造とすることにより、誘導電流による相互インダクタンスによって配線の寄生インダクタンスの低減を図ることができる。   On the other hand, according to this embodiment, as described above, the extraction electrode 20 that connects the source electrode of the MOSFET 13 and the source terminal 15 of the package has a multilayer structure in which the insulating layer 23 or the gap 38 are stacked. Thus, the parasitic inductance of the wiring can be reduced by the mutual inductance due to the induced current.

本発明の第１実施形態に係わる半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. 図１のII−II線断面図である。It is the II-II sectional view taken on the line of FIG. 寄生インダクタンスとターンオンロスの関係を示す図である。It is a figure which shows the relationship between a parasitic inductance and turn-on loss. 本発明の第２実施形態に係わる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. 本発明の第３実施形態に係わる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. 本発明の第４実施形態に係わる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning 4th Embodiment of this invention. 本発明の第５実施形態に係わる半導体装置で、（ａ）は平面図、（ｂ）は（ａ）のｂ−ｂ線断面図である。In the semiconductor device concerning 5th Embodiment of this invention, (a) is a top view, (b) is the bb sectional view taken on the line of (a). 取出し電極の第２の構造例を示す断面図である。It is sectional drawing which shows the 2nd structural example of an extraction electrode. 取出し電極の第３の構造例を示す斜視図である。It is a perspective view which shows the 3rd structural example of an extraction electrode. 比較例の半導体装置の斜視図である。It is a perspective view of the semiconductor device of a comparative example. ＭＯＳＦＥＴを使用したスイッチング回路である。This is a switching circuit using a MOSFET.

符号の説明Explanation of symbols

１０ 半導体装置、 １１、１２ リードフレーム、 １３ 半導体素子（ＭＯＳＦＥＴ）、 １３Ｄ ドレイン電極（第２の主電極）、 １３Ｇ ゲート電極（制御電極）、 １３Ｓ ソース電極（第１の主電極）、 １４ ドレイン端子、 １５ ゲート端子、 １５ ソース端子、 １６ ボンディングワイヤ、 １７ ソース端子、 ２０ 取り出し電極、 ２０ａ、２０ｂ 接続部、 ２１、２２ 導体、 ２３ 絶縁層（絶縁層）、 ２５ モールド樹脂、 ２６ 放熱板、 ２８ 絶縁層、 ２９ 導体、 ３０ モールド樹脂、 ３１、３２ 半田、 ３３ 放熱板、 ３８ 空隙、 ３９ スペーサ、 ４０ 長尺金属リボン、 ４２ 絶縁層、 ４４ 積層導体リボンテープ、 ４５ 取出し電極用ストラップ、 ４６ 湾曲部  DESCRIPTION OF SYMBOLS 10 Semiconductor device, 11, 12 Lead frame, 13 Semiconductor element (MOSFET), 13D Drain electrode (2nd main electrode), 13G Gate electrode (control electrode), 13S Source electrode (1st main electrode), 14 Drain terminal , 15 Gate terminal, 15 Source terminal, 16 Bonding wire, 17 Source terminal, 20 Extraction electrode, 20a, 20b Connection part, 21, 22 Conductor, 23 Insulating layer (insulating layer), 25 Mold resin, 26 Heat sink, 28 Insulating Layer, 29 conductor, 30 mold resin, 31, 32 solder, 33 heat sink, 38 gap, 39 spacer, 40 long metal ribbon, 42 insulating layer, 44 laminated conductor ribbon tape, 45 lead electrode strap, 46 curved portion

Claims (5)

第１のリードと、
第２のリードと、
前記第１のリードにマウントされた半導体素子と、
前記半導体素子と前記第２のリードとを接続する取り出し電極と、
を備え、
前記取り出し電極は、前記半導体素子と前記第２のリードとを電気的に接続する第１の導体と、前記第１の導体と電気的に絶縁された第２の導体と、前記第１の導体と前記第２の導体との間に設けられた絶縁層と、を有することを特徴とする半導体装置。 The first lead,
A second lead,
A semiconductor element mounted on the first lead;
An extraction electrode connecting the semiconductor element and the second lead;
With
The extraction electrode includes a first conductor that electrically connects the semiconductor element and the second lead, a second conductor that is electrically insulated from the first conductor, and the first conductor. And an insulating layer provided between the second conductor and the semiconductor device. 前記第１の導体は、前記取り出し電極と前記半導体素子との接続部及び前記取り出し電極と前記リードとの接続部で露出していることを特徴とする半導体装置。   The semiconductor device, wherein the first conductor is exposed at a connection portion between the extraction electrode and the semiconductor element and a connection portion between the extraction electrode and the lead. 前記半導体素子を覆う封止体をさらに備え、
前記第２の導体は、前記封止体から露出してなることを特徴とする請求項１または２に記載の半導体装置。 A sealing body covering the semiconductor element;
The semiconductor device according to claim 1, wherein the second conductor is exposed from the sealing body. 第１の主面に設けられた第１の電極と、前記第１の主面に対向する第２の主面に設けられた第２の電極と、を有する半導体素子と、
前記第１の電極に一端が接続された第１のリードと、
前記第１のリードの他端と、前記第２の電極と、を露出させつつ前記半導体素子と前記第１のリードとを覆う絶縁体と、
前記絶縁体を介して前記第１のリードの前記一端と対向する導体と、
を備えたことを特徴とする半導体装置。 A semiconductor element comprising: a first electrode provided on a first main surface; and a second electrode provided on a second main surface opposite to the first main surface;
A first lead having one end connected to the first electrode;
An insulator covering the semiconductor element and the first lead while exposing the other end of the first lead and the second electrode;
A conductor facing the one end of the first lead through the insulator;
A semiconductor device comprising: 半導体素子とリードとを接続する取出し電極用ストラップであって、少なくとも一対の金属リボンテープが絶縁層を挟んで積層されたことを特徴とする取出し電極用ストラップ。   An extraction electrode strap for connecting a semiconductor element and a lead, wherein at least a pair of metal ribbon tapes are laminated with an insulating layer interposed therebetween.
JP2007037695A 2007-02-19 2007-02-19 Semiconductor device and strap for extracting electrode Pending JP2008205083A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2011159933A (en) * 2010-02-04 2011-08-18 Mitsubishi Electric Corp Power semiconductor device, and method of manufacturing same
KR20200028031A (en) * 2017-08-03 2020-03-13 제네럴 일렉트릭 컴퍼니 Electronic package with integrated interconnect structure and method for manufacturing same
JP2020205380A (en) * 2019-06-18 2020-12-24 株式会社東芝 Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159933A (en) * 2010-02-04 2011-08-18 Mitsubishi Electric Corp Power semiconductor device, and method of manufacturing same
KR20200028031A (en) * 2017-08-03 2020-03-13 제네럴 일렉트릭 컴퍼니 Electronic package with integrated interconnect structure and method for manufacturing same
JP2020529734A (en) * 2017-08-03 2020-10-08 ゼネラル・エレクトリック・カンパニイ Electronic equipment package with integrated interconnection structure and its manufacturing method
JP7343477B2 (en) 2017-08-03 2023-09-12 ゼネラル・エレクトリック・カンパニイ Electronics package with integrated interconnect structure and method for manufacturing the same
KR102622109B1 (en) * 2017-08-03 2024-01-09 제네럴 일렉트릭 컴퍼니 Electronic package with integrated interconnection structure and method for manufacturing the same
JP2020205380A (en) * 2019-06-18 2020-12-24 株式会社東芝 Semiconductor device
JP7222822B2 (en) 2019-06-18 2023-02-15 株式会社東芝 semiconductor equipment
US11688711B2 (en) 2019-06-18 2023-06-27 Kabushiki Kaisha Toshiba Semiconductor device having second connector that overlaps a part of first connector

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