JP5953574B2 - 基板・製品基板組み合わせ体を製造する方法 - Google Patents
基板・製品基板組み合わせ体を製造する方法 Download PDFInfo
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- JP5953574B2 JP5953574B2 JP2015516479A JP2015516479A JP5953574B2 JP 5953574 B2 JP5953574 B2 JP 5953574B2 JP 2015516479 A JP2015516479 A JP 2015516479A JP 2015516479 A JP2015516479 A JP 2015516479A JP 5953574 B2 JP5953574 B2 JP 5953574B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Description
・出発材料
・正確なジオメトリ:製品をできるだけ精密に所望の厚さとなるように研削し、研磨することができるように、例えば1μmよりも小さい僅かなTTV(Total Thickness Variation)が必要である。
・テンポラリーボンディングの後からの分離を可能とする前処理。
・キャリア基板上で裏面薄化されるウェハのプラズマ処理を行う場合、偏心性がプラズマの不均一な放電を引き起こす。生じた放電(電界密度が高いことにより生じる絶縁破壊−アーク放電)は、製品及びプラズマ処理室を損傷する恐れがある。製品基板よりも小さい若しくは製品基板と同じ大きさのキャリア基板を使用する可能性により、プラズマプロセス及びスパッタプロセスで特別な利点が得られる。
・いわゆるスキャナ及びステッパでリソグラフィ露光する際に、調整が不十分なボンディング対は十分正確に負荷されない。ボンディング対の基準合わせ(予備位置合わせ)は外輪郭に基づき行われる。しかしながら(著しく)大きなキャリア基板の外輪郭は、キャリア基板と製品基板の両外輪郭の調整が正確でないならば、若しくは製品基板の外輪郭が使用できないならば、製品基板上のベンチマークの位置に対応しない。従ってベンチマークは顕微鏡の「捕捉範囲」にはなく、手間をかけて探さなければならない。これは、このシステムの時間的損失、処理量的損失、生産性損失に通じる。
2,2´ 基板
2a,2a´ 段部
2k,2k´ 載置縁
2o 接触面
3 接触手段
4 キャリア基板受容体
5,5´ キャリア基板
2u,5u 周縁
5o 支持面
6 回転手段
7 キャリアユニット
8 調節装置
9 ベースプレート
10 ガイドエレメント
11 距離測定エレメント
12 測定手段
13,13´,13´´,13´´´ 光学機器
14 接着層
15,15´ スキャンユニット
16 機能ユニット
d1,d2,d3,dk 平均直径
dR 平均リング幅
D1 厚さ
Claims (4)
- 面状の基板(2,2´)の接触面(2o)を、前記基板(2,2´)の補強材として働くキャリア基板(5,5´)の支持面(5o)に対して位置合わせし、接触させ、ボンディングすることにより基板・製品基板組み合わせ体を製造する方法であって、前記接触の際に前記基板(2,2´)は、前記キャリア基板(5,5´)の平均直径d2よりも大きな平均直径d1を有しており、前記基板(2,2´)を前記接触後に裏面薄化し、前記直径d1を、前記基板(2,2´)の周輪郭(2u)における前記基板(2,2´)の横断面の形状に基づいてd1<=d2となるように減じる方法において、
前記キャリア基板(5,5´)は、前記基板(2,2´)よりも小さい縁半径を有していることを特徴とする、基板・製品基板組み合わせ体を製造する方法。 - 前記基板(2,2´)は、縁半径を設けることにより、かつ/又は前記周輪郭(2u)の戻し切削により形成されたリング状の段部(2a,2a´)を有している、請求項1記載の方法。
- 前記段部(2a,2a´)は、前記d1とd2の差の1/2に相当するリング幅dRを有する、請求項2記載の方法。
- 前記裏面薄化の際に、前記基板(2,2´)の厚さD1を、前記段部(2a,2a´)まで、または該段部(2a,2a´)を越えるまで減じる、請求項2又は3記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2012/061117 WO2013185804A1 (de) | 2012-06-12 | 2012-06-12 | Substrat-produktsubstrat-kombination sowie vorrichtung und verfahren zur herstellung einer substrat-produktsubstrat-kombination |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015523724A JP2015523724A (ja) | 2015-08-13 |
JP5953574B2 true JP5953574B2 (ja) | 2016-07-20 |
Family
ID=46395595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2015516479A Active JP5953574B2 (ja) | 2012-06-12 | 2012-06-12 | 基板・製品基板組み合わせ体を製造する方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9343348B2 (ja) |
EP (1) | EP2859581B1 (ja) |
JP (1) | JP5953574B2 (ja) |
KR (1) | KR102012538B1 (ja) |
CN (1) | CN104662652B (ja) |
SG (1) | SG2014012934A (ja) |
WO (1) | WO2013185804A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6298723B2 (ja) * | 2014-06-13 | 2018-03-20 | 株式会社ディスコ | 貼り合わせウェーハ形成方法 |
US10354905B2 (en) * | 2015-03-11 | 2019-07-16 | Nv Bekaert Sa | Carrier for temporary bonded wafers |
CN110383446A (zh) * | 2017-03-16 | 2019-10-25 | Ev 集团 E·索尔纳有限责任公司 | 用于接合至少三个衬底的方法 |
US10388535B1 (en) * | 2018-05-25 | 2019-08-20 | Powertech Technology Inc. | Wafer processing method with full edge trimming |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10335195A (ja) * | 1997-05-27 | 1998-12-18 | Mitsubishi Materials Shilicon Corp | 張り合わせ基板の製造方法 |
EP0989616A3 (en) * | 1998-09-22 | 2006-05-10 | Canon Kabushiki Kaisha | Method and apparatus for producing photoelectric conversion device |
JP2000164565A (ja) | 1998-11-26 | 2000-06-16 | Sony Corp | 半導体製造装置 |
JP3515917B2 (ja) | 1998-12-01 | 2004-04-05 | シャープ株式会社 | 半導体装置の製造方法 |
JP3303294B2 (ja) * | 1999-06-11 | 2002-07-15 | 株式会社東京精密 | 半導体保護テープの切断方法 |
US6520844B2 (en) | 2000-08-04 | 2003-02-18 | Sharp Kabushiki Kaisha | Method of thinning semiconductor wafer capable of preventing its front from being contaminated and back grinding device for semiconductor wafers |
JP2005026413A (ja) | 2003-07-01 | 2005-01-27 | Renesas Technology Corp | 半導体ウエハ、半導体素子およびその製造方法 |
JP4415588B2 (ja) * | 2003-08-28 | 2010-02-17 | 株式会社Sumco | 剥離ウェーハの再生処理方法 |
DE102004007060B3 (de) * | 2004-02-13 | 2005-07-07 | Thallner, Erich, Dipl.-Ing. | Vorrichtung und Verfahren zum Verbinden von Wafern |
JP4306540B2 (ja) * | 2004-06-09 | 2009-08-05 | セイコーエプソン株式会社 | 半導体基板の薄型加工方法 |
JP2006100406A (ja) * | 2004-09-28 | 2006-04-13 | Toshiba Ceramics Co Ltd | Soiウェーハの製造方法 |
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
JP4613709B2 (ja) * | 2005-06-24 | 2011-01-19 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7371663B2 (en) * | 2005-07-06 | 2008-05-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional IC device and alignment methods of IC device substrates |
EP1775757B1 (de) * | 2005-10-13 | 2012-10-03 | Thallner, Erich, Dipl.-Ing. | Verfahren zum Bonden von Wafern |
-
2012
- 2012-06-12 KR KR1020147034494A patent/KR102012538B1/ko active IP Right Grant
- 2012-06-12 CN CN201280073963.3A patent/CN104662652B/zh active Active
- 2012-06-12 WO PCT/EP2012/061117 patent/WO2013185804A1/de active Application Filing
- 2012-06-12 EP EP12730184.4A patent/EP2859581B1/de active Active
- 2012-06-12 US US14/407,199 patent/US9343348B2/en active Active
- 2012-06-12 JP JP2015516479A patent/JP5953574B2/ja active Active
- 2012-06-12 SG SG2014012934A patent/SG2014012934A/en unknown
Also Published As
Publication number | Publication date |
---|---|
KR20150023360A (ko) | 2015-03-05 |
US9343348B2 (en) | 2016-05-17 |
EP2859581A1 (de) | 2015-04-15 |
US20150170953A1 (en) | 2015-06-18 |
CN104662652A (zh) | 2015-05-27 |
JP2015523724A (ja) | 2015-08-13 |
CN104662652B (zh) | 2016-12-28 |
EP2859581B1 (de) | 2016-02-24 |
WO2013185804A1 (de) | 2013-12-19 |
SG2014012934A (en) | 2014-09-26 |
KR102012538B1 (ko) | 2019-08-20 |
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