JP5907697B2 - 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 - Google Patents

配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 Download PDF

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Publication number
JP5907697B2
JP5907697B2 JP2011245103A JP2011245103A JP5907697B2 JP 5907697 B2 JP5907697 B2 JP 5907697B2 JP 2011245103 A JP2011245103 A JP 2011245103A JP 2011245103 A JP2011245103 A JP 2011245103A JP 5907697 B2 JP5907697 B2 JP 5907697B2
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Prior art keywords
conductive film
film
transparent conductive
wiring
upper conductive
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JP2011245103A
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Japanese (ja)
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JP2013101232A (ja
JP2013101232A5 (enExample
Inventor
慎吾 永野
慎吾 永野
武志 島村
武志 島村
徳仁 外
徳仁 外
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2011245103A priority Critical patent/JP5907697B2/ja
Priority to US13/653,333 priority patent/US8928122B2/en
Priority to CN201210446168.6A priority patent/CN103105711B/zh
Publication of JP2013101232A publication Critical patent/JP2013101232A/ja
Publication of JP2013101232A5 publication Critical patent/JP2013101232A5/ja
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011245103A 2011-11-09 2011-11-09 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 Active JP5907697B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011245103A JP5907697B2 (ja) 2011-11-09 2011-11-09 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置
US13/653,333 US8928122B2 (en) 2011-11-09 2012-10-16 Wiring structure, thin film transistor array substrate including the same, and display device
CN201210446168.6A CN103105711B (zh) 2011-11-09 2012-11-09 布线构造和具备其的薄膜晶体管阵列基板以及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011245103A JP5907697B2 (ja) 2011-11-09 2011-11-09 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置

Publications (3)

Publication Number Publication Date
JP2013101232A JP2013101232A (ja) 2013-05-23
JP2013101232A5 JP2013101232A5 (enExample) 2014-12-04
JP5907697B2 true JP5907697B2 (ja) 2016-04-26

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JP2011245103A Active JP5907697B2 (ja) 2011-11-09 2011-11-09 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置

Country Status (3)

Country Link
US (1) US8928122B2 (enExample)
JP (1) JP5907697B2 (enExample)
CN (1) CN103105711B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5520897B2 (ja) * 2011-08-11 2014-06-11 株式会社ジャパンディスプレイ 液晶表示装置
JP2015012048A (ja) 2013-06-27 2015-01-19 三菱電機株式会社 アクティブマトリクス基板およびその製造方法
JP6278633B2 (ja) * 2013-07-26 2018-02-14 三菱電機株式会社 薄膜トランジスタアレイ基板およびその製造方法、並びに、液晶表示装置およびその製造方法
JP6405196B2 (ja) * 2013-12-18 2018-10-17 キヤノン株式会社 半導体装置の製造方法
CN106575062B (zh) * 2014-08-07 2019-11-08 夏普株式会社 有源矩阵基板及其制造方法
US9927658B2 (en) * 2014-08-07 2018-03-27 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal panel, and method for manufacturing active matrix substrate
WO2016021319A1 (ja) * 2014-08-07 2016-02-11 シャープ株式会社 アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法
CN109313871A (zh) * 2016-06-28 2019-02-05 夏普株式会社 有源矩阵基板、光闸基板、显示装置、有源矩阵基板的制造方法
TWI625847B (zh) * 2016-09-09 2018-06-01 友達光電股份有限公司 畫素結構及其製作方法
US10866472B2 (en) * 2016-09-14 2020-12-15 Sharp Kabushiki Kaisha Mounting substrate and display panel
JP6978243B2 (ja) * 2017-07-26 2021-12-08 三菱電機株式会社 アレイ基板と当該アレイ基板を有する液晶表示装置
CN208422916U (zh) 2018-08-07 2019-01-22 京东方科技集团股份有限公司 阵列基板及显示装置
JP7680240B2 (ja) * 2021-03-30 2025-05-20 ローム株式会社 半導体装置
CN115793337B (zh) * 2022-12-19 2025-08-08 福州京东方光电科技有限公司 一种显示基板及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3281167B2 (ja) * 1994-03-17 2002-05-13 富士通株式会社 薄膜トランジスタの製造方法
JP2555987B2 (ja) 1994-06-23 1996-11-20 日本電気株式会社 アクティブマトリクス基板
KR100276442B1 (ko) * 1998-02-20 2000-12-15 구본준 액정표시장치 제조방법 및 그 제조방법에 의한 액정표시장치
JP3288637B2 (ja) * 1998-08-28 2002-06-04 富士通株式会社 Ｉｔｏ膜接続構造、ｔｆｔ基板及びその製造方法
TW460731B (en) * 1999-09-03 2001-10-21 Ind Tech Res Inst Electrode structure and production method of wide viewing angle LCD
JP5408829B2 (ja) * 1999-12-28 2014-02-05 ゲットナー・ファンデーション・エルエルシー アクティブマトリックス基板の製造方法
KR100482468B1 (ko) 2000-10-10 2005-04-14 비오이 하이디스 테크놀로지 주식회사 프린지 필드 구동 액정 표시 장치
KR100695303B1 (ko) * 2000-10-31 2007-03-14 삼성전자주식회사 제어 신호부 및 그 제조 방법과 이를 포함하는 액정 표시장치 및 그 제조 방법
JP4974500B2 (ja) * 2004-09-15 2012-07-11 株式会社半導体エネルギー研究所 半導体装置、モジュール及び電子機器
JP4916770B2 (ja) * 2006-05-22 2012-04-18 三菱電機株式会社 液晶表示装置、及びその製造方法
JP4321557B2 (ja) 2006-07-06 2009-08-26 エプソンイメージングデバイス株式会社 電気光学装置、電気光学装置の製造方法及び電子機器
US8228273B2 (en) * 2006-08-02 2012-07-24 Sharp Kabushiki Kaisha Active matrix substrate and display device having the same
CN100452363C (zh) * 2006-08-16 2009-01-14 友达光电股份有限公司 薄膜晶体管阵列基板的制作方法
US8218116B2 (en) 2007-08-01 2012-07-10 Sony Corporation Liquid crystal display panel and manufacturing method thereof
JP5154298B2 (ja) 2007-08-01 2013-02-27 株式会社ジャパンディスプレイウェスト 液晶表示パネル、その製造方法
JP2009117620A (ja) * 2007-11-07 2009-05-28 Casio Comput Co Ltd 画像読取装置およびその製造方法
JP5646162B2 (ja) 2009-01-23 2014-12-24 三菱電機株式会社 薄膜トランジスタアレイ基板、その製造方法、及び液晶表示装置
JP5671948B2 (ja) 2010-11-04 2015-02-18 三菱電機株式会社 薄膜トランジスタアレイ基板、及び液晶表示装置

Also Published As

Publication number Publication date
JP2013101232A (ja) 2013-05-23
CN103105711A (zh) 2013-05-15
CN103105711B (zh) 2016-04-06
US20130113109A1 (en) 2013-05-09
US8928122B2 (en) 2015-01-06

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