JP5872320B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5872320B2 JP5872320B2 JP2012038596A JP2012038596A JP5872320B2 JP 5872320 B2 JP5872320 B2 JP 5872320B2 JP 2012038596 A JP2012038596 A JP 2012038596A JP 2012038596 A JP2012038596 A JP 2012038596A JP 5872320 B2 JP5872320 B2 JP 5872320B2
- Authority
- JP
- Japan
- Prior art keywords
- island
- resin package
- lead
- groove
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 59
- 239000011347 resin Substances 0.000 claims description 77
- 229920005989 resin Polymers 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 21
- 238000007789 sealing Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
2 樹脂パッケージ
3 側面
5 リード
6 アイランドの端部領域
9 アイランド
11 半導体チップ
13 溝
20 プリフォーム材
22 凹部
26 ダイシング領域
28 貫通孔
Claims (4)
- アイランドと、
前記アイランドの近傍に配置されるリードと、
前記アイランドの一主面上に固着材を介して配置される半導体チップと、
前記アイランド、前記リード及び前記半導体チップを被覆する樹脂封止体とを有し、
前記アイランドの一主面側には、少なくとも前記半導体チップの固着領域と前記樹脂封止体の一側面との間に溝が形成され、前記溝は、前記アイランドの一主面と対向する他の主面まで貫通しない溝であり、前記アイランドは前記樹脂封止体の一側面から露出し、
前記半導体チップの端部は、前記樹脂封止体の一側面から露出する前記リードの前記樹脂封止体内側の端部よりも前記樹脂封止体の一側面側へと配置されることを特徴とする半導体装置。 - 前記溝よりも前記樹脂封止体の一側面側の前記アイランドは、前記一側面に対して凹凸形状に加工されることを特徴とする請求項1に記載の半導体装置。
- 前記凹凸形状に加工され、前記樹脂封止体の一側面から露出するアイランドは、リードとして用いられることを特徴とする請求項2に記載の半導体装置。
- 前記アイランドは、それぞれ分離した複数の搭載領域に区分され、前記樹脂封止体の側面から露出する前記搭載領域には、前記溝が形成されることを特徴とする請求項2または請求項3に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012038596A JP5872320B2 (ja) | 2012-02-24 | 2012-02-24 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012038596A JP5872320B2 (ja) | 2012-02-24 | 2012-02-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013175551A JP2013175551A (ja) | 2013-09-05 |
JP5872320B2 true JP5872320B2 (ja) | 2016-03-01 |
Family
ID=49268223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012038596A Active JP5872320B2 (ja) | 2012-02-24 | 2012-02-24 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5872320B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6228490B2 (ja) * | 2014-03-04 | 2017-11-08 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4985048U (ja) * | 1972-11-10 | 1974-07-23 | ||
JPS6052635U (ja) * | 1983-09-20 | 1985-04-13 | 大日本印刷株式会社 | リ−ドフレ−ム |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2004200561A (ja) * | 2002-12-20 | 2004-07-15 | Rohm Co Ltd | 電子部品用リードフレーム |
JP2011199148A (ja) * | 2010-03-23 | 2011-10-06 | Sanken Electric Co Ltd | 半導体装置 |
-
2012
- 2012-02-24 JP JP2012038596A patent/JP5872320B2/ja active Active
Also Published As
Publication number | Publication date |
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JP2013175551A (ja) | 2013-09-05 |
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