JP5857956B2 - Device mounting substrate and manufacturing method thereof - Google Patents

Device mounting substrate and manufacturing method thereof Download PDF

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JP5857956B2
JP5857956B2 JP2012513824A JP2012513824A JP5857956B2 JP 5857956 B2 JP5857956 B2 JP 5857956B2 JP 2012513824 A JP2012513824 A JP 2012513824A JP 2012513824 A JP2012513824 A JP 2012513824A JP 5857956 B2 JP5857956 B2 JP 5857956B2
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thick film
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conductor layer
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element mounting
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JPWO2011138949A1 (en
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勝寿 中山
勝寿 中山
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AGC Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Description

本発明は、素子搭載用基板とその製造方法とに係り、特に、耐硫化性に優れた素子搭載用基板と、その素子搭載用基板を製造するための製造方法に関する。   The present invention relates to an element mounting substrate and a manufacturing method thereof, and more particularly to an element mounting substrate having excellent resistance to sulfidation and a manufacturing method for manufacturing the element mounting substrate.

近年、電子機器の高密度実装化や処理速度の高速化に伴い、素子搭載用基板として、低誘電率で低配線抵抗という優れた特徴を有する低温焼成セラミックス基板(LTCC基板)が使用されている。また、発光ダイオード(LED)のような発光素子を搭載するための基板として、耐候性、光取り出し効率、放熱性等の各特性を満足させることが可能なLTCC基板の使用が検討されている。   In recent years, low-temperature fired ceramic substrates (LTCC substrates) having an excellent feature of low dielectric constant and low wiring resistance are used as device mounting substrates with high-density mounting of electronic devices and high processing speed. . In addition, use of an LTCC substrate capable of satisfying various characteristics such as weather resistance, light extraction efficiency, and heat dissipation as a substrate for mounting a light emitting element such as a light emitting diode (LED) has been studied.

LTCC基板は、通常のセラミックスの焼成温度より低い800〜1000℃程度の温度で焼成されるものであり、ガラスとセラミックスフィラー(例えば、アルミナフィラーやジルコニアフィラー)とからなるグリーンシートを所定の枚数重ね合わせ、熱圧着により一体化した後、焼成することにより製造されている。   The LTCC substrate is fired at a temperature of about 800 to 1000 ° C. which is lower than the firing temperature of normal ceramics, and a predetermined number of green sheets made of glass and ceramic filler (for example, alumina filler or zirconia filler) are stacked. These are manufactured by firing after being integrated by thermocompression bonding.

このようなLTCC基板の表面には、接続端子(電極)として、銀や銅のような導体金属を主体とするペーストを焼成してなる厚膜導体層が形成されている。厚膜導体層の表面には、ワイヤボンディング性、密着強度、耐候性等を良好にするために、例えばニッケルメッキ膜と金メッキ膜とを積層したメッキ層(ニッケル/金メッキ層)が形成されている。このようなメッキ層を形成することで、特に耐硫化性を向上させることができ、空気中等の硫黄分との反応による厚膜導体層の変色を抑制できる(例えば、特許文献1、2参照)。   On the surface of such an LTCC substrate, a thick film conductor layer formed by firing a paste mainly composed of a conductor metal such as silver or copper is formed as a connection terminal (electrode). On the surface of the thick film conductor layer, for example, a plating layer (nickel / gold plating layer) in which a nickel plating film and a gold plating film are laminated is formed in order to improve wire bonding properties, adhesion strength, weather resistance, and the like. . By forming such a plating layer, it is possible to particularly improve the resistance to sulfidation, and to suppress discoloration of the thick film conductor layer due to a reaction with sulfur in the air or the like (for example, see Patent Documents 1 and 2). .

ところで、厚膜導体層は通常5〜15μm程度の厚さを有しており、この上に形成されるメッキ層、特にニッケルメッキ膜の厚みは5〜15μm程度とされている。しかしながら、ニッケルメッキ膜の厚さを正確に制御することは難しく、想定外に厚く形成される場合がある。ニッケルメッキ膜の厚さが通常より厚くなり、例えば20μmに近くなると、厚膜導体層に過度な引張応力が加えられ、厚膜導体層の端部がLTCC基板から剥がれることがある。そのような剥がれが生じると、LTCC基板と厚膜導体層との隙間に水分が侵入し、厚膜導体層中の銀が端部を伝うようにしてメッキ層の表面、特に最表面の金メッキ膜上に拡散する。   By the way, the thick film conductor layer usually has a thickness of about 5 to 15 μm, and the thickness of the plating layer formed thereon, particularly the nickel plating film, is about 5 to 15 μm. However, it is difficult to accurately control the thickness of the nickel plating film, and it may be formed unexpectedly thick. When the thickness of the nickel plating film becomes thicker than usual, for example, close to 20 μm, an excessive tensile stress is applied to the thick film conductor layer, and the end of the thick film conductor layer may be peeled off from the LTCC substrate. When such peeling occurs, moisture enters the gap between the LTCC substrate and the thick film conductor layer, so that the silver in the thick film conductor layer is transmitted to the end portion, and the surface of the plating layer, particularly the outermost gold plating film Spreads up.

そして、このような状態で硫化性環境に置かれた場合には、最表面の金メッキ膜上に拡散した銀が硫化され、ワイヤボンディング性等が低下するおそれがあった。また、金メッキ膜の表面が黒色化することで反射率の低下が生じるため、発光素子等の搭載用基板として好ましくなかった。   When placed in a sulfide environment in such a state, the silver diffused on the gold plating film on the outermost surface is sulfided, and there is a possibility that the wire bonding property and the like are deteriorated. Further, since the surface of the gold plating film is blackened, the reflectance is lowered, which is not preferable as a mounting substrate for a light emitting element or the like.

なお、ワイヤボンディング性を損なわずに、焼成の際の寸法精度を向上させるために、最外層にAg系導体ペーストの印刷層(未焼成の厚膜導体層)を有する未焼成の低温焼成セラミック基板の両面に、焼成温度(800〜1000℃)では焼結しないアルミナグリーンシート(拘束焼成用グリーンシート)を圧着し、この状態で基板および厚膜導体層を同時焼成した後アルミナグリーンシートの残存物を研磨して取り除き、こうして形成された厚膜導体層の荒れた表面にメッキ皮膜を形成したLTCC配線基板が提案されている(例えば、特許文献3、4参照)。   An unfired low-temperature fired ceramic substrate having a printed layer of an Ag-based conductor paste (unfired thick film conductor layer) as the outermost layer in order to improve dimensional accuracy during firing without impairing wire bonding properties An alumina green sheet (green sheet for restraint firing) that is not sintered at a firing temperature (800 to 1000 ° C.) is pressure-bonded to both sides of the substrate, and the substrate and the thick film conductor layer are simultaneously fired in this state, and then the alumina green sheet remains. An LTCC wiring board has been proposed in which a plating film is formed on the rough surface of the thick-film conductor layer thus formed (see, for example, Patent Documents 3 and 4).

しかしながら、特許文献3、4に記載されたLTCC配線基板では、拘束焼成用のアルミナグリーンシートで両面を挟んで加圧しているため、未焼成の厚膜導体層を厚さ全体に亘って未焼成の低温焼成セラミック基板に押し込むことが難しい。そのため、特許文献3、4のLTCC配線基板では、厚膜導体層が完全には低温焼成セラミック基板内に埋め込まれておらず、メッキ膜の応力に起因する厚膜導体層端部の剥がれを十分に防止することができず、耐硫化性が不十分であった。また、厚膜導体層の表面は、拘束焼成用グリーンシート残存物の除去によって荒れた状態となっているため、メッキ処理後のワイヤボンディング性に劣るという問題があった。   However, in the LTCC wiring board described in Patent Documents 3 and 4, since both sides are pressed with an alumina green sheet for restraint firing, the unfired thick film conductor layer is not fired over the entire thickness. It is difficult to push into a low-temperature fired ceramic substrate. Therefore, in the LTCC wiring boards of Patent Documents 3 and 4, the thick film conductor layer is not completely embedded in the low-temperature fired ceramic substrate, and the end of the thick film conductor layer is sufficiently peeled off due to the stress of the plating film. The sulfidation resistance was insufficient. Moreover, since the surface of the thick film conductor layer is in a rough state due to the removal of the restraint firing green sheet residue, there is a problem that the wire bonding property after the plating process is inferior.

実公平2−36278号公報Japanese Utility Model Publication No. 2-36278 特開2002−314230号公報JP 2002-314230 A 特許第4123278号公報Japanese Patent No. 4123278 特開2008−235911号公報参照See Japanese Patent Application Laid-Open No. 2008-235911

本発明は、上記課題を解決するためになされたものであって、厚膜導体層端部の剥がれが防止され、耐硫化性に優れた素子搭載用基板の提供を目的とする。また、本発明は、このような耐硫化性に優れた素子搭載用基板を得るための製造方法の提供を目的とする。   The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide an element mounting substrate which is prevented from peeling off at the end of a thick film conductor layer and has excellent sulfidation resistance. Another object of the present invention is to provide a manufacturing method for obtaining such an element mounting substrate having excellent resistance to sulfidation.

本発明の素子搭載用基板は、低温焼成セラミックス基板と、前記低温焼成セラミックス基板の少なくとも一方の主面に形成された銀を主体とする金属からなる厚膜導体層であり、平滑な表面を有し、かつ該表面が前記低温焼成セラミックス基板の前記主面と略同じ高さになるように埋め込まれた厚膜導体層と、前記厚膜導体層の上に形成された導電性金属のメッキ層とを有し、前記厚膜導体層が、0.3μm以下の表面粗さ(Ra)であることを特徴とする。 The element mounting substrate of the present invention is a low-temperature fired ceramic substrate and a thick-film conductor layer mainly made of silver and formed on at least one main surface of the low-temperature fired ceramic substrate, and has a smooth surface. And a thick-film conductor layer embedded so that the surface is substantially the same height as the main surface of the low-temperature fired ceramic substrate, and a conductive metal plating layer formed on the thick-film conductor layer possess the door, the thick film conductor layer, characterized in that a 0.3μm less surface roughness (Ra).

本発明の素子搭載用基板において、前記厚膜導体層の表面と前記低温焼成セラミックス基板の前記主面との高さの差は2μm以下であることが好ましい。また、前記メッキ層は、ニッケル−金メッキ層であることが好ましい。   In the element mounting substrate of the present invention, the difference in height between the surface of the thick film conductor layer and the main surface of the low-temperature fired ceramic substrate is preferably 2 μm or less. The plating layer is preferably a nickel-gold plating layer.

本発明の素子搭載用基板の製造方法は、前記記載の本発明の素子搭載用基板を製造する方法であって、ガラス粉末とセラミックスフィラーとを含むガラスセラミックス組成物からなる未焼成基板の少なくとも一方の主面に、銀を主体とする金属のペーストからなる未焼成厚膜導体層を形成する工程と、前記未焼成厚膜導体層の上に平滑な押圧面を有する加圧板を配置し、この加圧板を介して前記未焼成厚膜導体層を厚さ方向に押圧して、該未焼成厚膜導体層の表面が前記未焼成基板の前記主面と略同じ高さになるまで前記未焼成基板に押し込む工程と、前記未焼成厚膜導体層が押し込まれた前記未焼成基板を、前記未焼成厚膜導体層とともに加熱・焼成する工程と、前記焼成された厚膜導体層の表面に導電性金属からなるメッキ層を形成する工程とを有することを特徴とする。 The method for manufacturing an element mounting substrate of the present invention is a method for manufacturing the element mounting substrate of the present invention described above, and is at least one of an unsintered substrate made of a glass ceramic composition containing glass powder and a ceramic filler. A step of forming an unfired thick film conductor layer made of a metal paste mainly composed of silver, and a pressure plate having a smooth pressing surface on the unfired thick film conductor layer. The unfired thick film conductor layer is pressed in the thickness direction through a pressure plate, and the unfired until the surface of the unfired thick film conductor layer becomes substantially the same height as the main surface of the unfired substrate. A step of pushing into the substrate, a step of heating and firing the unfired substrate with the unfired thick film conductor layer together with the unfired thick film conductor layer, and a conductive surface on the surface of the fired thick film conductor layer. A plating layer made of conductive metal And having a degree.

本発明によれば、低温焼成セラミックス基板の少なくとも一方の主面に形成された厚膜導体層を、該層の表面が前記低温焼成セラミックス基板の前記主面と略同じ高さになるように埋め込み形成することで、低温焼成セラミックス基板からの厚膜導体層の剥がれを防止し、耐硫化性に優れた素子搭載用基板とできる。   According to the present invention, the thick film conductor layer formed on at least one main surface of the low-temperature fired ceramic substrate is embedded so that the surface of the layer is substantially the same height as the main surface of the low-temperature fired ceramic substrate. By forming, the peeling of the thick film conductor layer from the low-temperature fired ceramic substrate can be prevented, and an element mounting substrate having excellent sulfidation resistance can be obtained.

本発明の素子搭載用基板の一例を示す平面図である。It is a top view which shows an example of the element mounting substrate of this invention. 図1に示す素子搭載用基板のX−X線断面図である。It is XX sectional drawing of the element mounting board | substrate shown in FIG. 図2の一部を拡大して示す拡大断面図である。It is an expanded sectional view which expands and shows a part of FIG. 本発明の素子搭載用基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the element mounting substrate of this invention.

以下、本発明について図面を参照して説明する。   The present invention will be described below with reference to the drawings.

図1は、本発明の素子搭載用基板1の一例を示す平面図である。また、図2は、図1に示す素子搭載用基板1のX−X線断面図であり、図3は、図2の一部を拡大して示す拡大断面図である。   FIG. 1 is a plan view showing an example of the element mounting substrate 1 of the present invention. 2 is a sectional view taken along line XX of the element mounting substrate 1 shown in FIG. 1, and FIG. 3 is an enlarged sectional view showing a part of FIG.

本発明の素子搭載用基板1は、ガラス粉末とセラミックスフィラーとを含むガラスセラミックス組成物の焼結体からなる低温焼成セラミックス基板(LTCC基板)2を有している。LTCC基板2の一方の主面は、半導体素子、例えばLED素子のような発光素子が搭載される搭載面2aとなっている。なお、LTCC基板2の形状、厚さ、大きさ等は必ずしも制限されるものではない。また、LTCC基板2の搭載面2a側には、中央部を囲み内側が例えば円形状となる側壁(図示を省略。)が設けられていてもよい。   The element mounting substrate 1 of the present invention has a low-temperature fired ceramic substrate (LTCC substrate) 2 made of a sintered body of a glass ceramic composition containing glass powder and a ceramic filler. One main surface of the LTCC substrate 2 is a mounting surface 2a on which a semiconductor element, for example, a light emitting element such as an LED element is mounted. The shape, thickness, size, etc. of the LTCC substrate 2 are not necessarily limited. Further, on the mounting surface 2a side of the LTCC substrate 2, there may be provided a side wall (not shown) that surrounds the central portion and has an inner shape, for example, a circular shape.

搭載面2aには、銀を主体とする金属から構成され、半導体素子との接続端子(電極)となる厚膜導体層3が形成されている。この厚膜導体層3は凹凸がない平滑(平坦)な表面を有し、かつその表面がLTCC基板2の搭載面2aと略同じ高さになるようにLTCC基板2に埋め込まれている。なお、本明細書において、略同じ高さとは、高さの差が好ましくは10μm以下、より好ましくは5μm以下であることをいう。厚膜導体層3の表面がLTCC基板2の搭載面2aとは、どちらが高くてもよいが、両者は全く同じ高さ、すなわち面一であることが好ましい。なかでも、厚膜導体層3の表面がLTCC基板2の搭載面2aより上にあり、かつ高さの差(段差)(h)が好ましくは2μm以下、より好ましくは1μm以下であれば、厚膜導体層3の剥がれを防止する効果を十分に挙げることができる。高さの差が2μmを超えると、メッキ膜4に引張応力が加わるために厚膜導体層3の剥がれを起こしやすくなる。また、厚膜導体層3の表面がLTCC基板2の搭載面2aより下にあると、メッキ膜4の表面に段差が発生してしまい、ワイヤボンディング不良などを生じるおそれがある。   On the mounting surface 2a, a thick film conductor layer 3 made of a metal mainly composed of silver and serving as a connection terminal (electrode) with a semiconductor element is formed. The thick film conductor layer 3 is embedded in the LTCC substrate 2 so as to have a smooth (flat) surface with no irregularities and to have a surface that is substantially the same height as the mounting surface 2 a of the LTCC substrate 2. In the present specification, “substantially the same height” means that the difference in height is preferably 10 μm or less, more preferably 5 μm or less. The surface of the thick film conductor layer 3 may be either higher than the mounting surface 2a of the LTCC substrate 2, but it is preferable that both of them are the same height, that is, flush with each other. In particular, if the surface of the thick film conductor layer 3 is above the mounting surface 2a of the LTCC substrate 2 and the height difference (step) (h) is preferably 2 μm or less, more preferably 1 μm or less, the thickness The effect of preventing the film conductor layer 3 from peeling off can be sufficiently mentioned. If the difference in height exceeds 2 μm, a tensile stress is applied to the plating film 4, so that the thick film conductor layer 3 is easily peeled off. Further, if the surface of the thick film conductor layer 3 is below the mounting surface 2a of the LTCC substrate 2, a step is generated on the surface of the plating film 4, which may cause a wire bonding failure.

厚膜導体層3は、後述するように、金属のペーストをスクリーン印刷等で印刷し、加圧して基板内に押し込みながら焼成することで形成されている。厚膜導体層3の表面粗さ(算術平均粗さ)Raは、0.3μm以下が好ましく、0.2μm以下とすることがより好ましい。Raは、JIS B 0601:1982により求められる。Raが0.3μmを超えると、メッキ処理を施した後部分的に薄膜の箇所が発生してしまい、メッキによる皮膜効果が小さくなり、耐候性試験で厚膜導体層3が劣化してしまうおそれがある。   As will be described later, the thick-film conductor layer 3 is formed by printing a metal paste by screen printing or the like, pressurizing it and firing it into the substrate. The surface roughness (arithmetic mean roughness) Ra of the thick film conductor layer 3 is preferably 0.3 μm or less, and more preferably 0.2 μm or less. Ra is calculated | required by JISB0601: 1982. When Ra exceeds 0.3 μm, a thin film portion is partially generated after the plating process is performed, the film effect by plating is reduced, and the thick film conductor layer 3 may be deteriorated in the weather resistance test. There is.

このようにLTCC基板2に埋め込まれた厚膜導体層3の表面に、導電性金属からなるメッキ層4が形成されている。メッキ層4は、図示しないが、例えば厚膜導体層3の表面を覆うニッケルメッキ膜と、このニッケルメッキ膜の表面を覆う金メッキ膜とから構成されており、厚膜導体層3のLTCC基板2から露出した表面を隙間なく覆っている。   Thus, the plating layer 4 made of a conductive metal is formed on the surface of the thick film conductor layer 3 embedded in the LTCC substrate 2. Although not shown, the plating layer 4 is composed of, for example, a nickel plating film that covers the surface of the thick film conductor layer 3 and a gold plating film that covers the surface of the nickel plating film, and the LTCC substrate 2 of the thick film conductor layer 3. The exposed surface is covered with no gaps.

一方、LTCC基板2の搭載面2aと反対側の非搭載面2bには、外部接続用の接続端子(電極)となる厚膜導体層3が形成されている。この厚膜導体層3も、前記した搭載面2a側の厚膜導体層3と同様に、平滑な表面を有し、かつその表面がLTCC基板2の非搭載面2bと略同じ高さになるようにLTCC基板2に埋め込まれている。また、この厚膜導体層3のLTCC基板2から露出した表面にも、導電性金属からなるメッキ層4が形成されている。非搭載面2b側の厚膜導体層3およびメッキ層4は、それぞれ搭載面2a側の厚膜導体層3およびメッキ層4と同様の材料からなるものとできる。   On the other hand, on the non-mounting surface 2b opposite to the mounting surface 2a of the LTCC substrate 2, a thick film conductor layer 3 serving as a connection terminal (electrode) for external connection is formed. This thick film conductor layer 3 also has a smooth surface, and the surface thereof is substantially the same height as the non-mounting surface 2b of the LTCC substrate 2, as is the case with the thick film conductor layer 3 on the mounting surface 2a side. As shown in FIG. A plating layer 4 made of a conductive metal is also formed on the surface of the thick film conductor layer 3 exposed from the LTCC substrate 2. The thick film conductor layer 3 and the plating layer 4 on the non-mounting surface 2b side can be made of the same material as the thick film conductor layer 3 and the plating layer 4 on the mounting surface 2a side, respectively.

さらに、LTCC基板2の内部には、搭載面2aの素子接続用の接続端子と非搭載面2bの外部接続用の接続端子とを電気的に接続する貫通導体5が設けられている。貫通導体5は、搭載面2aや非搭載面2bに形成される厚膜導体層3と同様の材料からなるものとできる。   Further, a through conductor 5 is provided inside the LTCC substrate 2 to electrically connect a connection terminal for element connection on the mounting surface 2a and a connection terminal for external connection on the non-mounting surface 2b. The through conductor 5 can be made of the same material as the thick film conductor layer 3 formed on the mounting surface 2a and the non-mounting surface 2b.

このような素子搭載用基板1によれば、厚膜導体層3がLTCC基板2に埋め込まれているので、メッキ層4特にニッケルメッキ膜が想定外に厚く形成され、その結果厚膜導体層3に過度な引張応力が加えられる場合であっても、厚膜導体層3端部のLTCC基板2からの剥がれを防止できる。これにより、厚膜導体層3を構成する銀がメッキ層4表面へ銀イオンの状態で拡散することを抑制し、硫化性環境下での硫化を防止できる。したがって、ワイヤボンディング性等が良好であり、また発光素子を搭載する場合に必要とされる反射率についても良好な素子搭載用基板1を得ることができる。   According to such an element mounting substrate 1, since the thick film conductor layer 3 is embedded in the LTCC substrate 2, the plating layer 4, particularly the nickel plating film, is formed unexpectedly thick, and as a result, the thick film conductor layer 3. Even when excessive tensile stress is applied to the thick film conductor layer 3, it is possible to prevent the end portion of the thick film conductor layer 3 from peeling off from the LTCC substrate 2. Thereby, it can suppress that the silver which comprises the thick film conductor layer 3 diffuses in the state of silver ion to the plating layer 4 surface, and can prevent sulfidation in a sulfide environment. Therefore, it is possible to obtain an element mounting substrate 1 that has good wire bonding properties and the like and that has a good reflectance required when mounting a light emitting element.

本発明の素子搭載用基板1は、LTCC基板2の少なくとも搭載面2aに形成された厚膜導体層3が、LTCC基板2に埋め込まれていることを特徴としている。非搭載面2b側の厚膜導体層3については、必ずしもLTCC基板2に埋め込まれている必要はなく、非搭載面2b上に形成されていてもよいが、LTCC基板2の両面側で厚膜導体層3がLTCC基板2に埋め込まれた構造とすることで、より耐硫化性を良好とできる。   The element mounting substrate 1 of the present invention is characterized in that a thick film conductor layer 3 formed on at least the mounting surface 2 a of the LTCC substrate 2 is embedded in the LTCC substrate 2. The thick film conductor layer 3 on the non-mounting surface 2b side does not necessarily need to be embedded in the LTCC substrate 2 and may be formed on the non-mounting surface 2b. By adopting a structure in which the conductor layer 3 is embedded in the LTCC substrate 2, the sulfidation resistance can be further improved.

次に、本発明の素子搭載用基板1の製造方法について説明する。図4(a)および(b)は、本発明の製造における加圧・焼成工程を説明するための素子搭載用基板1の断面図である。図4および以下の記載では、素子搭載用基板1の製造に用いる部材について、この部材が最終的に構成する素子搭載用基板1の部材と同一の符号を付して説明する。   Next, the manufacturing method of the element mounting substrate 1 of the present invention will be described. 4 (a) and 4 (b) are cross-sectional views of the element mounting substrate 1 for explaining the pressurizing / firing process in the production of the present invention. In FIG. 4 and the following description, members used for manufacturing the element mounting substrate 1 will be described with the same reference numerals as the members of the element mounting substrate 1 that is finally formed by this member.

本発明の素子搭載用基板1の製造方法は、ガラス粉末とセラミックスフィラーとを含むガラスセラミックス組成物からなる未焼成基板2を製造し、その搭載面2aおよび非搭載面2bにそれぞれ銀を主体とする金属のペーストからなる未焼成厚膜導体層3を形成する工程(未焼成基板製造工程)と、これらの未焼成厚膜導体層3が形成された未焼成基板2の両面に、平滑(平坦)な押圧面を有する1対の加圧板6を、それぞれの押圧面が対応する未焼成厚膜導体層3の表面に当接するように配置し、これらの加圧板6を介して未焼成厚膜導体層3を厚さ方向に押圧して未焼成基板2に押し込み、その状態で加熱・焼成する工程(加圧・焼成工程)と、基板に埋め込まれた厚膜導体層3の露出面に導電性金属からなるメッキ層4を形成する工程(メッキ工程)とを有する。   The manufacturing method of the element mounting substrate 1 of the present invention is to manufacture an unfired substrate 2 made of a glass ceramic composition containing glass powder and a ceramic filler, and the mounting surface 2a and the non-mounting surface 2b are mainly composed of silver. Smooth (flat) on the both sides of the unfired thick film conductor layer 3 formed with the step of forming the unfired thick film conductor layer 3 made of a metal paste (unfired substrate manufacturing process) ) A pair of pressure plates 6 having pressing surfaces are arranged so that each pressing surface comes into contact with the surface of the corresponding unfired thick film conductor layer 3, and the unfired thick film is interposed through these pressure plates 6. The conductor layer 3 is pressed in the thickness direction and pressed into the unfired substrate 2, and heated and fired in that state (pressure and firing step), and the exposed surface of the thick film conductor layer 3 embedded in the substrate is electrically conductive. For forming the plating layer 4 made of conductive metal Having a plating process) and.

未焼成基板製造工程では、まず未焼成基板2となるグリーンシートを形成する。グリーンシートは、ガラス粉末とセラミックスフィラーとを含むガラスセラミックス組成物に、バインダー、必要に応じて可塑剤、溶剤等を添加してスラリーを調製し、これをドクターブレード法等によりシート状に成形し、乾燥させることで製造できる。   In the green substrate manufacturing process, first, a green sheet to be the green substrate 2 is formed. The green sheet is prepared by adding a binder, and optionally a plasticizer, a solvent, etc. to a glass ceramic composition containing glass powder and a ceramic filler, and forming this into a sheet by the doctor blade method or the like. It can be manufactured by drying.

ガラス粉末は、必ずしも限定されるものではないが、ガラス転移点(Tg)が550〜700℃のものが好ましく、600〜680℃のものがより好ましい。ガラス転移点(Tg)が550℃未満の場合には、後述する脱脂が困難となるおそれがあり、700℃を超える場合には、収縮開始温度が高くなり、寸法精度が低下するおそれがある。   The glass powder is not necessarily limited, but preferably has a glass transition point (Tg) of 550 to 700 ° C, more preferably 600 to 680 ° C. When the glass transition point (Tg) is lower than 550 ° C., degreasing described later may be difficult. When the glass transition point (Tg) is higher than 700 ° C., the shrinkage start temperature is increased, and the dimensional accuracy may be decreased.

ガラス粉末としては、例えばSiOを57〜65mol%、Bを13〜18mol%、CaOを9〜23mol%、Alを3〜8mol%、KOおよびNaOから選ばれる少なくとも一方を合計で0.5〜6mol%含有するガラスの粉末が用いられる。ガラス粉末の50%粒径(D50)は0.5〜2μmが好ましく、1.0〜1.8μmがより好ましい。ガラス粉末のD50が0.5μm未満の場合、ガラス粉末が凝集しやすく、取り扱いが困難となるばかりでなく、均一に分散させることが困難となる。一方、D50が2μmを超える場合には、ガラス軟化温度の上昇や焼結不足が発生するおそれがある。なお、本件記載の粒径は、レーザ回折・散乱法により測定したものである。As the glass powder, for example, SiO 2 is selected from 57 to 65 mol%, B 2 O 3 is 13 to 18 mol%, CaO is 9 to 23 mol%, Al 2 O 3 is 3 to 8 mol%, K 2 O and Na 2 O are selected. Glass powder containing a total of at least one of 0.5 to 6 mol% is used. The glass powder has a 50% particle size (D 50 ) of preferably 0.5 to 2 μm, and more preferably 1.0 to 1.8 μm. If D 50 of the glass powder is less than 0.5 [mu] m, the glass powder is likely to agglomerate, handle not only difficult, it is difficult to uniformly disperse. On the other hand, when D 50 exceeds 2 μm, the glass softening temperature may increase or the sintering may be insufficient. In addition, the particle size described in this case is measured by a laser diffraction / scattering method.

セラミックスフィラーとしては、従来からLTCC基板の製造に用いられるものを用いることができ、例えばアルミナ粉末、ジルコニア粉末、アルミナ粉末とジルコニア粉末との混合粉末等を好適に用いることができる。セラミックスフィラーのD50は、0.5〜4μmであることが好ましい。As the ceramic filler, those conventionally used for the production of LTCC substrates can be used. For example, alumina powder, zirconia powder, mixed powder of alumina powder and zirconia powder, and the like can be suitably used. The D 50 of the ceramic filler is preferably 0.5 to 4 μm.

このようなガラス粉末とセラミックスフィラーとを、例えばガラス粉末が30〜50質量%、より好ましくは35〜40質量%であり、セラミックスフィラーが50〜70質量%、より好ましくは60〜65質量%となるように配合し、混合することによりガラスセラミックス組成物を得ることができる。また、このガラスセラミックス組成物に、バインダー、必要に応じて可塑剤、溶剤等を添加することによりスラリーを得ることができる。   Such glass powder and ceramic filler, for example, glass powder is 30 to 50% by mass, more preferably 35 to 40% by mass, and ceramic filler is 50 to 70% by mass, more preferably 60 to 65% by mass. A glass ceramic composition can be obtained by blending and mixing. Moreover, a slurry can be obtained by adding a binder and, if necessary, a plasticizer, a solvent, and the like to the glass ceramic composition.

バインダーとしては、例えばポリビニルブチラール、アクリル樹脂等を好適に用いることができる。可塑剤としては、例えばフタル酸ジブチル、フタル酸ジオクチル、フタル酸ブチルベンジル等を用いることができる。また、溶剤としては、トルエン、キシレン、ブタノール等の芳香族系またはアルコール系の有機溶剤を用いることができる。さらに、分散剤やレベリング剤を併用できる。   As the binder, for example, polyvinyl butyral, acrylic resin and the like can be suitably used. As the plasticizer, for example, dibutyl phthalate, dioctyl phthalate, butyl benzyl phthalate and the like can be used. As the solvent, aromatic or alcoholic organic solvents such as toluene, xylene and butanol can be used. Furthermore, a dispersing agent and a leveling agent can be used together.

このようにして製造したグリーンシートを、打抜き型あるいはパンチングマシーンを使用して、所定の寸法角に切断するとともに層間接続用のビアホールを打抜き形成して、未焼成基板2とする。この未焼成基板2の両面(搭載面2aおよび非搭載面2b)に、銀を主体とする金属のペーストをスクリーン印刷等の方法で印刷することにより、未焼成厚膜導体層3を形成する。また、層間接続用のビアホール内にも、銀を主体とする金属のペーストを充填することにより、未焼成貫通導体5を形成する。   The green sheet thus manufactured is cut into a predetermined dimensional angle using a punching die or a punching machine, and via holes for interlayer connection are formed by punching to form an unfired substrate 2. An unfired thick film conductor layer 3 is formed by printing a metal paste mainly composed of silver on both surfaces (mounting surface 2a and non-mounting surface 2b) of the unfired substrate 2 by a method such as screen printing. Further, the unfired through conductor 5 is formed by filling a metal paste mainly composed of silver in the via hole for interlayer connection.

金属のペーストとしては、銀を主体とする金属粉末、具体的には銀を50質量%以上含有する金属粉末に、エチルセルロース等のビヒクル、必要に応じて溶剤等を添加してペースト状としたものを用いることができる。金属粉末としては、銀粉末、銀とパラジウムとの混合粉末、銀と白金との混合粉末等が好適に用いられる。銀とパラジウムとの混合粉末の場合、好ましくは銀は90質量%以上、パラジウムは10質量%以下含有するものである。また、銀と白金との混合粉末の場合、好ましくは銀は97質量%以上、白金は3質量%以下含有するものである。なお、本発明においては、LTCC基板2に含まれるガラス成分により金属と基板との接着力を十分に確保することができ、また金属の電気抵抗値を上げないためにも、金属のペーストにはガラスフリットを配合しないことが好ましい。   As a metal paste, a metal powder mainly composed of silver, specifically, a metal powder containing 50% by mass or more of silver, and a vehicle such as ethyl cellulose, and a solvent or the like as necessary are added into a paste. Can be used. As the metal powder, silver powder, mixed powder of silver and palladium, mixed powder of silver and platinum, and the like are preferably used. In the case of a mixed powder of silver and palladium, the silver content is preferably 90% by mass or more and the palladium content is 10% by mass or less. In the case of a mixed powder of silver and platinum, preferably silver is contained in an amount of 97% by mass or more and platinum is contained in an amount of 3% by mass or less. In the present invention, the glass component contained in the LTCC substrate 2 can ensure sufficient adhesion between the metal and the substrate, and the metal paste does not increase the electrical resistance value of the metal. It is preferable not to mix glass frit.

加圧・焼成工程では、まず図4(a)に示すように、未焼成厚膜導体層3が形成された未焼成基板2の両面(搭載面2aおよび非搭載面2b)に、平滑な押圧面を有する1対の金属板6を、それぞれの押圧面が対応する未焼成厚膜導体層3の表面に当接するように配置する。なお、非搭載面2b側に配置される金属板6を、平滑な押圧面を有する基台あるいは基盤とできる。   In the pressurizing / firing step, first, as shown in FIG. 4A, smooth pressing is performed on both surfaces (the mounting surface 2a and the non-mounting surface 2b) of the unfired substrate 2 on which the unfired thick film conductor layer 3 is formed. A pair of metal plates 6 having a surface are arranged such that each pressing surface comes into contact with the surface of the corresponding unfired thick film conductor layer 3. In addition, the metal plate 6 arrange | positioned at the non-mounting surface 2b side can be used as the base or base | substrate which has a smooth press surface.

そして、これらの金属板6を介して、搭載面2a側および非搭載面2b側の未焼成厚膜導体層3をそれぞれ厚さ方向に押圧し、未焼成基板2に押し込む。このとき、金属板6の押圧面が未焼成基板2の対応する搭載面2aあるいは非搭載面2bに接するまで、未焼成厚膜導体層3を未焼成基板2内に押し込む。このような状態で加熱し、未焼成厚膜導体層3および未焼成基板2を同時に焼成する。   Then, the unfired thick film conductor layers 3 on the mounting surface 2 a side and the non-mounting surface 2 b side are pressed in the thickness direction through these metal plates 6 and pressed into the unfired substrate 2. At this time, the unfired thick film conductor layer 3 is pushed into the unfired substrate 2 until the pressing surface of the metal plate 6 contacts the corresponding mounting surface 2a or non-mounting surface 2b of the unfired substrate 2. By heating in such a state, the unfired thick film conductor layer 3 and the unfired substrate 2 are fired simultaneously.

金属板6としては、未焼成厚膜導体層3が未焼成基板2に押し込まれるに十分な加圧力である、例えば5〜30MPaを加えることができるように、十分な剛性を有し、かつ押圧面が鏡面加工等により平滑に形成されたステンレス板を使用することが好ましい。   The metal plate 6 has sufficient rigidity so that the unsintered thick film conductor layer 3 can be applied to the unsintered substrate 2, for example, 5 to 30 MPa, and is pressed. It is preferable to use a stainless steel plate having a smooth surface formed by mirror finishing or the like.

焼成工程では、このように押し込まれた未焼成厚膜導体層3を有する未焼成基板2を、例えば500〜600℃、より好ましくは530〜570℃の温度に加熱し、樹脂等のバインダーを分解し除去する脱脂を行った後、800〜1000℃、より好ましくは840〜930℃温度に加熱することで、ガラスセラミックス組成物からなる未焼成基板2を焼成するとともに、銀を主体とする金属のペーストからなる未焼成厚膜導体層3や未焼成貫通導体5を焼成して、厚膜導体層3や貫通導体5とする。こうして、図4(b)に示すように、厚膜導体層3の表面がLTCC基板2の搭載面2aおよび非搭載面2bと略同じ高さになるように埋め込まれた焼成基板が得られる。   In the firing step, the unfired substrate 2 having the unfired thick film conductor layer 3 thus pressed is heated to a temperature of, for example, 500 to 600 ° C., more preferably 530 to 570 ° C., and a binder such as a resin is decomposed. Then, after degreasing to be removed, the unfired substrate 2 made of the glass ceramic composition is fired by heating to 800 to 1000 ° C., more preferably 840 to 930 ° C. The unfired thick film conductor layer 3 and the unfired through conductor 5 made of paste are fired to form the thick film conductor layer 3 and the through conductor 5. In this way, as shown in FIG. 4B, a fired substrate is obtained in which the surface of the thick film conductor layer 3 is embedded so as to be approximately the same height as the mounting surface 2a and the non-mounting surface 2b of the LTCC substrate 2.

メッキ工程では、このようにしてLTCC基板2に埋め込まれた厚膜導体層3の露出した表面に、メッキ層4を形成する。メッキ層4は、例えばニッケルメッキを行った後、金メッキを行うことにより形成できる。ニッケルメッキは、例えばスルファミン酸ニッケル浴を使用した電解メッキによって5〜40μm、より好ましくは5〜20μmの厚さに形成する。また、金メッキは、例えばシアン化金カリウム浴を使用した電解メッキによって0.1〜1.0μm、より好ましくは0.2〜0.6μmの厚さに形成する。   In the plating step, the plating layer 4 is formed on the exposed surface of the thick film conductor layer 3 embedded in the LTCC substrate 2 in this way. The plating layer 4 can be formed by performing gold plating after nickel plating, for example. The nickel plating is formed to a thickness of 5 to 40 μm, more preferably 5 to 20 μm, for example, by electrolytic plating using a nickel sulfamate bath. The gold plating is formed to a thickness of 0.1 to 1.0 μm, more preferably 0.2 to 0.6 μm, for example, by electrolytic plating using a potassium gold cyanide bath.

こうして、厚膜導体層3がLTCC基板2に埋め込まれるとともに、厚膜導体層3のLTCC基板2から露出した表面がメッキ層4により被覆されており、耐硫化性に優れた素子搭載用基板1を製造できる。   Thus, the thick film conductor layer 3 is embedded in the LTCC substrate 2, and the surface exposed from the LTCC substrate 2 of the thick film conductor layer 3 is covered with the plating layer 4, and the element mounting substrate 1 having excellent sulfidation resistance. Can be manufactured.

以下に、本発明の実施例について記載する。   Examples of the present invention will be described below.

(実施例)
素子搭載用基板1として、図1、図2に示すものを図4に示す加圧・焼成工程を経て製造した。まず、LTCC基板2となる基板用グリーンシートを作製した。基板用グリーンシートは、SiOが60.4mol%、Bが15.6mol%、Alが6mol%、CaOが15mol%、KOが1mol%、NaOが2mol%となるように原料を配合、混合し、この原料混合物を白金ルツボに入れて1600℃で60分間溶融させた後、この溶融状態のガラスを流し出し冷却した。このガラスをアルミナ製ボールミルにより40時間粉砕してガラス粉末(D50=1.8μm)を製造した。なお、粉砕時の溶媒にはエチルアルコールを用いた。
(Example)
As the element mounting substrate 1, the substrate shown in FIGS. 1 and 2 was manufactured through the pressurization / firing process shown in FIG. 4. First, a green sheet for a substrate to be the LTCC substrate 2 was produced. The substrate green sheet is 60.4 mol% SiO 2 , 15.6 mol% B 2 O 3 , 6 mol% Al 2 O 3 , 15 mol% CaO, 1 mol% K 2 O, 2 mol% Na 2 O. The raw materials were blended and mixed so as to become, and the raw material mixture was put in a platinum crucible and melted at 1600 ° C. for 60 minutes, and then the molten glass was poured out and cooled. This glass was pulverized with an alumina ball mill for 40 hours to produce a glass powder (D 50 = 1.8 μm). In addition, ethyl alcohol was used as a solvent for pulverization.

このガラス粉末が35質量%、アルミナフィラー(昭和電工社製、商品名:AL−45H)が40質量%、ジルコニアフィラー(第一稀元素化学工業社製、商品名:HSY−3F−J)が25質量%となるように配合し、混合することによりガラスセラミックス組成物を製造した。このガラスセラミックス組成物50gに、有機溶剤(トルエン、キシレン、2−プロパノール、2−ブタノールを質量比4:2:2:1で混合したもの)15g、可塑剤(フタル酸ジ−2−エチルヘキシル)2.5g、バインダーとしてのポリビニルブチラール(デンカ社製、商品名:PVK#3000K)5g、さらに分散剤(ビックケミー社製、商品名:BYK180)0.5gを配合し、混合してスラリーを調製した。   35% by mass of this glass powder, 40% by mass of alumina filler (manufactured by Showa Denko KK, trade name: AL-45H), and zirconia filler (manufactured by Daiichi Rare Element Chemical Industries, trade name: HSY-3F-J) A glass ceramic composition was produced by blending and mixing so as to be 25% by mass. 50 g of this glass ceramic composition, 15 g of an organic solvent (toluene, xylene, 2-propanol, 2-butanol mixed at a mass ratio of 4: 2: 2: 1), plasticizer (di-2-ethylhexyl phthalate) 2.5 g of polyvinyl butyral (trade name: PVK # 3000K, manufactured by Denka Co., Ltd.) as a binder, 5 g, and 0.5 g of a dispersant (trade name: BYK180, manufactured by Big Chemie) were blended and mixed to prepare a slurry. .

このスラリーをポリエチレンテレフタレート(PET)フィルム上にドクターブレード法により塗布し、乾燥させ、焼成後の厚さが0.15mmとなる基板用グリーンシートを製造した。   This slurry was applied onto a polyethylene terephthalate (PET) film by a doctor blade method and dried to produce a green sheet for a substrate having a thickness after firing of 0.15 mm.

一方、銀を主体とする金属粉末(大研化学工業社製、商品名:S400−2)と、ビヒクルとしてのエチルセルロースとを、質量比90:10の割合で配合し、固形分が87質量%となるように溶剤としてのαテレピネオールに分散した後、磁器乳鉢中で1時間混練を行い、さらに三本ロールにて3回分散を行って金属ペーストを製造した。   On the other hand, a metal powder mainly composed of silver (manufactured by Daiken Chemical Industry Co., Ltd., trade name: S400-2) and ethyl cellulose as a vehicle are blended at a mass ratio of 90:10, and the solid content is 87% by mass. After being dispersed in α-terpineol as a solvent, a metal paste was produced by kneading for 1 hour in a porcelain mortar and further dispersing three times with three rolls.

基板用グリーンシートの貫通導体5を形成する部分に、孔空け機を用いて直径0.3mmの貫通孔を形成し、この貫通孔中にスクリーン印刷法により金属ペーストを充填して未焼成貫通導体5を形成するとともに、両面にスクリーン印刷法により金属ペーストを塗布して未焼成厚膜導体層3を形成して未焼成基板2を製造した。   A through hole having a diameter of 0.3 mm is formed in a portion where the through conductor 5 of the green sheet for substrate is formed by using a hole puncher, and a metal paste is filled into the through hole by a screen printing method to form an unfired through conductor. 5 and a metal paste was applied on both sides by screen printing to form an unfired thick film conductor layer 3 to produce an unfired substrate 2.

次いで、未焼成厚膜導体層3が形成された未焼成基板2の両面に、表面が鏡面加工された厚さ1mmのステンレス板を押し当て、厚さ方向に10MPaの圧力を加えて、未焼成厚膜導体層3を未焼成基板2内に押し込んだ。そして、圧力を解放した後、550℃で5時間保持する脱脂を行い、さらに870℃で30分間保持する焼成を行った。こうして、厚膜導体層3の表面がLTCC基板2の表面と同じ高さになるように埋め込まれた基板を製造した。   Next, a 1 mm thick stainless steel plate having a mirror-finished surface is pressed against both sides of the unfired substrate 2 on which the unfired thick film conductor layer 3 is formed, and a pressure of 10 MPa is applied in the thickness direction to unfire the unfired substrate 2. The thick film conductor layer 3 was pushed into the unfired substrate 2. Then, after releasing the pressure, degreasing was performed by holding at 550 ° C. for 5 hours, and baking was further performed at 870 ° C. for 30 minutes. In this way, a substrate in which the surface of the thick film conductor layer 3 was embedded so as to be the same height as the surface of the LTCC substrate 2 was manufactured.

その後、LTCC基板2から露出した厚膜導体層3の部分に、スルファミン酸ニッケル浴を用いた電解メッキによって7μmのニッケルメッキ膜を形成した。その表面にシアン化金カリウム浴を用いた電解メッキによって0.3μmの厚みの金メッキ膜を形成してメッキ層4を形成した。こうして素子搭載用基板1を製造した。   Thereafter, a 7 μm nickel plating film was formed on the thick film conductor layer 3 exposed from the LTCC substrate 2 by electrolytic plating using a nickel sulfamate bath. A plating layer 4 was formed by forming a gold plating film having a thickness of 0.3 μm on the surface by electrolytic plating using a potassium gold cyanide bath. In this way, the element mounting substrate 1 was manufactured.

(比較例)
実施例の素子搭載用基板の製造において、未焼成厚膜導体層3が形成された未焼成基板2を、ステンレス板により押圧することなく脱脂、焼成を行った。そして、焼成後の基板の厚膜導体層3の表面全体にメッキを行って、素子搭載用基板1を製造した。
(Comparative example)
In the manufacture of the element mounting substrate of the example, the unfired substrate 2 on which the unfired thick film conductor layer 3 was formed was degreased and fired without being pressed by a stainless steel plate. Then, the entire surface of the thick film conductor layer 3 of the fired substrate was plated to manufacture the element mounting substrate 1.

次に、実施例および比較例で製造された素子搭載用基板1に対して、JIS−C−60068−2−43に準拠する硫化試験にて100時間暴露させ、金メッキ膜の表面の硫化(黒色化)を20倍の顕微鏡により観察した。また厚膜導体層3の剥がれについては電子顕微鏡により断面を2000倍で観察した。   Next, the element mounting substrates 1 manufactured in the examples and comparative examples were exposed for 100 hours in a sulfidation test according to JIS-C-60068-2-43, and the surface of the gold plating film was sulfidized (black). Was observed with a 20 × microscope. Moreover, about peeling of the thick film conductor layer 3, the cross section was observed by 2000 times with the electron microscope.

耐硫化性試験の結果、実施例の素子搭載用基板1では厚膜導体層3端部の剥がれがなく、また、メッキ層4表面への銀イオンの拡散、および硫化が有効に抑制されていることが認められた。一方、厚膜導体層3の埋め込みを行わなかった比較例の素子搭載用基板1については、厚膜導体層3の端部のLTCC基板2からの剥がれが見られた。そして、メッキ層4の表面に銀イオンが拡散し、硫化されることが認められた。   As a result of the sulfidation resistance test, the end portion of the thick film conductor layer 3 is not peeled off in the element mounting substrate 1 of the example, and the diffusion and sulfidation of silver ions on the surface of the plating layer 4 are effectively suppressed. It was recognized that On the other hand, regarding the element mounting substrate 1 of the comparative example in which the thick film conductor layer 3 was not embedded, peeling of the end portion of the thick film conductor layer 3 from the LTCC substrate 2 was observed. It was confirmed that silver ions diffused and sulfided on the surface of the plating layer 4.

本発明により提供される、基板からの厚膜導体層の剥がれが防止され、耐硫化性に優れた素子搭載用基板は、耐候性、光取り出し効率、放熱性等の特性にすぐれるため、発光ダイオード(LED)のような発光素子の搭載基板として、広範な分野に使用される。
なお、2010年5月7日に出願された日本特許出願2010−107053号の明細書、特許請求の範囲、図面及び要約書の全内容をここに引用し、本発明の明細書の開示として、取り入れるものである。
The element mounting substrate provided by the present invention, which prevents the thick film conductor layer from peeling off from the substrate and has excellent sulfidation resistance, has excellent characteristics such as weather resistance, light extraction efficiency, and heat dissipation. As a mounting substrate for a light emitting element such as a diode (LED), it is used in a wide range of fields.
The entire contents of the specification, claims, drawings, and abstract of Japanese Patent Application No. 2010-107053 filed on May 7, 2010 are cited herein as disclosure of the specification of the present invention. Incorporated.

1…素子搭載用基板
2…LTCC基板
3…厚膜導体層
4…メッキ層
5…貫通導体
6…金属板
DESCRIPTION OF SYMBOLS 1 ... Element mounting board | substrate 2 ... LTCC board | substrate 3 ... Thick film conductor layer 4 ... Plating layer 5 ... Through-conductor 6 ... Metal plate

Claims (10)

低温焼成セラミックス基板と、
前記低温焼成セラミックス基板の少なくとも一方の主面に形成された銀を主体とする金属からなる厚膜導体層であり、平滑な表面を有し、かつ該表面が前記低温焼成セラミックス基板の前記主面と略同じ高さになるように埋め込まれた厚膜導体層と、
前記厚膜導体層の上に形成された導電性金属のメッキ層とを有し、
前記厚膜導体層が、0.3μm以下の表面粗さ(Ra)であることを特徴とする素子搭載用基板。
A low-temperature fired ceramic substrate;
A thick-film conductor layer made of a metal mainly composed of silver and formed on at least one main surface of the low-temperature fired ceramic substrate, having a smooth surface, and the surface is the main surface of the low-temperature fired ceramic substrate A thick film conductor layer embedded to be approximately the same height as,
It has a plating layer of a conductive metal formed on the thick film conductor layer,
The element mounting substrate , wherein the thick film conductor layer has a surface roughness (Ra) of 0.3 μm or less .
前記厚膜導体層の表面と前記低温焼成セラミックス基板の前記主面との高さの差が2μm以下である請求項1に記載の素子搭載用基板。   The element mounting substrate according to claim 1, wherein a difference in height between the surface of the thick film conductor layer and the main surface of the low-temperature fired ceramic substrate is 2 μm or less. 前記メッキ層は、ニッケル層とその上の金メッキ層とからなる請求項1または2に記載の素子搭載用基板。The element mounting substrate according to claim 1, wherein the plating layer includes a nickel layer and a gold plating layer thereon. 前記メッキ層が、5〜40μmの厚みのニッケルメッキ層と、0.1〜1.0μmの厚みの金メッキ層を有する請求項1〜3のいずれかに記載の素子搭載用基板。The element mounting substrate according to claim 1, wherein the plating layer has a nickel plating layer having a thickness of 5 to 40 μm and a gold plating layer having a thickness of 0.1 to 1.0 μm. 前記厚膜導体層が、低温焼成セラミックス基板の素子の搭載面に形成された請求項1〜4のいずれかに記載の素子搭載用基板。The element mounting substrate according to claim 1, wherein the thick film conductor layer is formed on an element mounting surface of a low-temperature fired ceramic substrate. 請求項1〜5のいずれかに記載の素子搭載用基板を製造する素子搭載用基板の製造方法であって、A device mounting substrate manufacturing method for manufacturing the device mounting substrate according to claim 1,
ガラス粉末とセラミックスフィラーとを含むガラスセラミックス組成物からなる未焼成基板の少なくとも一方の主面に、銀を主体とする金属のペーストからなる未焼成厚膜導体層を形成する工程と、Forming an unfired thick film conductor layer made of a metal paste mainly composed of silver on at least one principal surface of an unfired substrate made of a glass ceramic composition containing glass powder and a ceramic filler;
前記未焼成厚膜導体層の上に平滑な押圧面を有する加圧板を配置し、この加圧板を介して前記未焼成厚膜導体層を厚さ方向に押圧して、該未焼成厚膜導体層の表面が前記未焼成基板の前記主面と略同じ高さになるまで前記未焼成基板に押し込む工程と、A pressure plate having a smooth pressing surface is disposed on the unfired thick film conductor layer, and the unfired thick film conductor is pressed through the pressure plate in the thickness direction. Pressing the green substrate until the surface of the layer is substantially the same height as the main surface of the green substrate;
前記未焼成厚膜導体層が押し込まれた前記未焼成基板を、前記未焼成厚膜導体層とともに加熱・焼成する工程と、Heating and firing the unfired substrate into which the unfired thick film conductor layer has been pressed, together with the unfired thick film conductor layer;
前記焼成された厚膜導体層の表面に導電性金属からなるメッキ層を形成する工程とForming a plated layer made of a conductive metal on the surface of the fired thick film conductor layer;
を有することを特徴とする素子搭載用基板の製造方法。A method for manufacturing an element mounting substrate, comprising:
前記ガラスセラミックス組成物が、ガラス粉末を30〜50質量%、セラミックスフィラーを50〜70質量%含む請求項6に記載の素子搭載用基板の製造方法。The manufacturing method of the board | substrate for element mounting of Claim 6 in which the said glass ceramic composition contains 30-50 mass% of glass powder, and 50-70 mass% of ceramic fillers. 前記銀を主体とする金属が、銀、銀とパラジウム、または銀と白金である請求項6または7に記載の素子搭載用基板の製造方法。The method for manufacturing an element mounting substrate according to claim 6 or 7, wherein the metal mainly composed of silver is silver, silver and palladium, or silver and platinum. 前記加熱・焼成する工程が、500〜600℃の温度に加熱し、次いで、800〜1000℃の温度に加熱して焼成を行う請求項6〜8のいずれかに記載の素子搭載用基板の製造方法。The manufacturing of the element mounting substrate according to any one of claims 6 to 8, wherein the step of heating and baking is performed by heating to a temperature of 500 to 600 ° C and then heating to a temperature of 800 to 1000 ° C. Method. 前記メッキ層を形成する工程が、電解メッキによりニッケルメッキ層を形成し、その上に電解メッキにより金メッキ層を形成する請求項6〜9のいずれかに記載の素子搭載用基板の製造方法。The method for manufacturing an element mounting substrate according to any one of claims 6 to 9, wherein in the step of forming the plating layer, a nickel plating layer is formed by electrolytic plating, and a gold plating layer is formed thereon by electrolytic plating.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0840789A (en) * 1994-08-02 1996-02-13 Sumitomo Electric Ind Ltd Ceramic metallized substrate having smooth plating layer and its production
JPH10125719A (en) * 1996-10-18 1998-05-15 Sumitomo Kinzoku Electro Device:Kk Formation method of wire bonding pads
JP2001060766A (en) * 1999-08-19 2001-03-06 Sumitomo Metal Electronics Devices Inc Low-temperature firing ceramic circuit board and its manufacturing method
JP2002100877A (en) * 2000-09-21 2002-04-05 Tdk Corp Surface electrode structure of ceramics multilayer substrate and manufacturing method of surface electrode
JP2002329969A (en) * 2001-04-26 2002-11-15 Sharp Corp Method of manufacturing multilayer ceramic wiring board
JP2004034448A (en) * 2002-07-02 2004-02-05 Murata Mfg Co Ltd Method for manufacturing multi-layer ceramic substrate
JP2008124200A (en) * 2006-11-10 2008-05-29 Alps Electric Co Ltd Method for manufacturing mounting board made of ceramics, and mounting board made of ceramics

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60172360U (en) 1984-04-20 1985-11-15 株式会社精工舎 Printed board
JP4682437B2 (en) 2001-04-17 2011-05-11 パナソニック株式会社 Board device
JP4123278B2 (en) 2006-01-23 2008-07-23 株式会社村田製作所 Low temperature fired ceramic circuit board and manufacturing method thereof
JP2008235911A (en) 2008-03-26 2008-10-02 Murata Mfg Co Ltd Low-temperature fired ceramic circuit board and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0840789A (en) * 1994-08-02 1996-02-13 Sumitomo Electric Ind Ltd Ceramic metallized substrate having smooth plating layer and its production
JPH10125719A (en) * 1996-10-18 1998-05-15 Sumitomo Kinzoku Electro Device:Kk Formation method of wire bonding pads
JP2001060766A (en) * 1999-08-19 2001-03-06 Sumitomo Metal Electronics Devices Inc Low-temperature firing ceramic circuit board and its manufacturing method
JP2002100877A (en) * 2000-09-21 2002-04-05 Tdk Corp Surface electrode structure of ceramics multilayer substrate and manufacturing method of surface electrode
JP2002329969A (en) * 2001-04-26 2002-11-15 Sharp Corp Method of manufacturing multilayer ceramic wiring board
JP2004034448A (en) * 2002-07-02 2004-02-05 Murata Mfg Co Ltd Method for manufacturing multi-layer ceramic substrate
JP2008124200A (en) * 2006-11-10 2008-05-29 Alps Electric Co Ltd Method for manufacturing mounting board made of ceramics, and mounting board made of ceramics

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