JP5819027B2 - メモリアクセス遅延トレーニングのための方法および装置 - Google Patents

メモリアクセス遅延トレーニングのための方法および装置 Download PDF

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JP5819027B2
JP5819027B2 JP2015514160A JP2015514160A JP5819027B2 JP 5819027 B2 JP5819027 B2 JP 5819027B2 JP 2015514160 A JP2015514160 A JP 2015514160A JP 2015514160 A JP2015514160 A JP 2015514160A JP 5819027 B2 JP5819027 B2 JP 5819027B2
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signal
data strobe
enable signal
strobe signal
preamble
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JP2015520902A (ja
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エイ． デアース グレン
エイ． デアース グレン
アール． アンダーソン ウォーレン
アール． アンダーソン ウォーレン
ピー． カシェム アンワー
ピー． カシェム アンワー
ダブリュ． リーヴス リチャード
ダブリュ． リーヴス リチャード
プレーテ エドアルド
プレーテ エドアルド
アール． タルボット ジェラルド
アール． タルボット ジェラルド
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2015514160A 2012-05-22 2013-05-22 メモリアクセス遅延トレーニングのための方法および装置 Active JP5819027B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/477,642 US8760946B2 (en) 2012-05-22 2012-05-22 Method and apparatus for memory access delay training
US13/477,642 2012-05-22
PCT/US2013/042281 WO2013177315A1 (en) 2012-05-22 2013-05-22 Method and apparatus for memory access delay training

Publications (2)

Publication Number Publication Date
JP2015520902A JP2015520902A (ja) 2015-07-23
JP5819027B2 true JP5819027B2 (ja) 2015-11-18

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JP2015514160A Active JP5819027B2 (ja) 2012-05-22 2013-05-22 メモリアクセス遅延トレーニングのための方法および装置

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Country Link
US (1) US8760946B2 (enExample)
EP (1) EP2852898B1 (enExample)
JP (1) JP5819027B2 (enExample)
KR (1) KR101549648B1 (enExample)
CN (1) CN104335197B (enExample)
IN (1) IN2014DN10277A (enExample)
WO (1) WO2013177315A1 (enExample)

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US9190129B2 (en) * 2013-05-31 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Continuous tuning of preamble release timing in a double data-rate memory device interface
US9478268B2 (en) * 2014-06-12 2016-10-25 Qualcomm Incorporated Distributed clock synchronization
KR20160147517A (ko) 2015-06-15 2016-12-23 에스케이하이닉스 주식회사 반도체시스템
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US10749756B2 (en) 2016-06-24 2020-08-18 Advanced Micro Devices, Inc. Channel training using a replica lane
KR102536657B1 (ko) * 2016-07-12 2023-05-30 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
US10311236B2 (en) 2016-11-22 2019-06-04 Advanced Micro Devices, Inc. Secure system memory training
KR102649888B1 (ko) 2016-11-29 2024-03-22 에스케이하이닉스 주식회사 트레이닝 장치 및 이를 포함하는 반도체 시스템
KR102760070B1 (ko) * 2016-12-16 2025-01-31 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
KR102671708B1 (ko) * 2016-12-16 2024-06-04 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10545866B1 (en) * 2017-06-30 2020-01-28 Cadence Design Systems, Inc. Method and system for efficient re-determination of a data valid window
JP6890055B2 (ja) * 2017-06-30 2021-06-18 ルネサスエレクトロニクス株式会社 半導体装置
KR102273191B1 (ko) 2017-09-08 2021-07-06 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
KR102447499B1 (ko) 2017-10-19 2022-09-26 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
CN108922570B (zh) * 2018-07-13 2020-11-13 豪威科技(上海)有限公司 读dqs信号的相位偏移检测方法、训练方法、电路及系统
JP2020046918A (ja) * 2018-09-19 2020-03-26 キオクシア株式会社 記憶装置及び制御方法
KR102691395B1 (ko) * 2018-12-20 2024-08-05 에스케이하이닉스 주식회사 메모리 시스템, 메모리 시스템의 동작 방법 및 메모리 콘트롤러
US10622982B1 (en) * 2019-01-10 2020-04-14 Western Digital Technologies, Inc. Measurement, calibration and tuning of memory bus duty cycle
CN113450852B (zh) 2020-03-25 2022-04-12 长鑫存储技术有限公司 半导体存储器的训练方法及相关设备
KR102866520B1 (ko) 2020-05-06 2025-10-01 삼성전자주식회사 저장 장치 및 그것의 리트레이닝 방법
JP2022146543A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 半導体記憶装置、メモリシステム、および方法
KR102707477B1 (ko) * 2021-04-19 2024-09-19 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 클록 동기화를 위한 시스템, 신호 동기화를 제어하기 위한 방법, 및 저장 매체
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
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Publication number Publication date
IN2014DN10277A (enExample) 2015-08-07
CN104335197A (zh) 2015-02-04
JP2015520902A (ja) 2015-07-23
EP2852898A1 (en) 2015-04-01
CN104335197B (zh) 2017-04-19
US20130315014A1 (en) 2013-11-28
KR101549648B1 (ko) 2015-09-03
WO2013177315A1 (en) 2013-11-28
US8760946B2 (en) 2014-06-24
KR20140147898A (ko) 2014-12-30
EP2852898B1 (en) 2017-08-02

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