JP5791207B2 - 複数の低電力モードを有するデータプロセッサ - Google Patents

複数の低電力モードを有するデータプロセッサ Download PDF

Info

Publication number
JP5791207B2
JP5791207B2 JP2013512625A JP2013512625A JP5791207B2 JP 5791207 B2 JP5791207 B2 JP 5791207B2 JP 2013512625 A JP2013512625 A JP 2013512625A JP 2013512625 A JP2013512625 A JP 2013512625A JP 5791207 B2 JP5791207 B2 JP 5791207B2
Authority
JP
Japan
Prior art keywords
terminal
power supply
virtual
voltage
supply terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013512625A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013528300A5 (enExample
JP2013528300A (ja
Inventor
ラマラジュ、ラビンドララージ
アール． ベアーデン、デイビッド
アール． ベアーデン、デイビッド
エル． クーパー、トロイ
エル． クーパー、トロイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2013528300A publication Critical patent/JP2013528300A/ja
Publication of JP2013528300A5 publication Critical patent/JP2013528300A5/ja
Application granted granted Critical
Publication of JP5791207B2 publication Critical patent/JP5791207B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)
JP2013512625A 2010-05-25 2011-04-20 複数の低電力モードを有するデータプロセッサ Active JP5791207B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/786,916 US8489906B2 (en) 2010-05-25 2010-05-25 Data processor having multiple low power modes
US12/786,916 2010-05-25
PCT/US2011/033211 WO2011149606A2 (en) 2010-05-25 2011-04-20 Data processor having multiple low power modes

Publications (3)

Publication Number Publication Date
JP2013528300A JP2013528300A (ja) 2013-07-08
JP2013528300A5 JP2013528300A5 (enExample) 2014-05-22
JP5791207B2 true JP5791207B2 (ja) 2015-10-07

Family

ID=45004629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013512625A Active JP5791207B2 (ja) 2010-05-25 2011-04-20 複数の低電力モードを有するデータプロセッサ

Country Status (5)

Country Link
US (1) US8489906B2 (enExample)
EP (1) EP2577422B1 (enExample)
JP (1) JP5791207B2 (enExample)
CN (1) CN102906665B (enExample)
WO (1) WO2011149606A2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8527709B2 (en) * 2007-07-20 2013-09-03 Intel Corporation Technique for preserving cached information during a low power mode
DE102010044924B4 (de) * 2010-09-10 2021-09-16 Texas Instruments Deutschland Gmbh Elektronische Vorrichtung und Verfahren für diskrete lastadaptive Spannungsregelung
US8977878B2 (en) * 2011-05-19 2015-03-10 Texas Instruments Incorporated Reducing current leakage in L1 program memory
US8230247B2 (en) * 2011-12-30 2012-07-24 Intel Corporation Transferring architectural functions of a processor to a platform control hub responsive to the processor entering a deep sleep state
JP6100076B2 (ja) * 2012-05-02 2017-03-22 株式会社半導体エネルギー研究所 プロセッサ
US9405357B2 (en) * 2013-04-01 2016-08-02 Advanced Micro Devices, Inc. Distribution of power gating controls for hierarchical power domains
US9335814B2 (en) * 2013-08-28 2016-05-10 Intel Corporation Adaptively controlling low power mode operation for a cache memory
JP2015064676A (ja) * 2013-09-24 2015-04-09 株式会社東芝 情報処理装置、半導体装置、情報処理方法およびプログラム
GB2520740A (en) * 2013-11-29 2015-06-03 St Microelectronics Res & Dev Low power die
US9582068B2 (en) * 2015-02-24 2017-02-28 Qualcomm Incorporated Circuits and methods providing state information preservation during power saving operations
US10209726B2 (en) * 2016-06-10 2019-02-19 Microsoft Technology Licensing, Llc Secure input voltage adjustment in processing devices
US10228746B1 (en) * 2017-12-05 2019-03-12 Western Digital Technologies, Inc. Dynamic distributed power control circuits

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3184265B2 (ja) * 1991-10-17 2001-07-09 株式会社日立製作所 半導体集積回路装置およびその制御方法
JP4387122B2 (ja) * 1996-11-21 2009-12-16 株式会社日立製作所 低電力プロセッサ
US6021500A (en) 1997-05-07 2000-02-01 Intel Corporation Processor with sleep and deep sleep modes
JP2001053599A (ja) * 1999-08-12 2001-02-23 Nec Corp 半導体集積回路
US6785829B1 (en) 2000-06-30 2004-08-31 Intel Corporation Multiple operating frequencies in a processor
US6941480B1 (en) 2000-09-30 2005-09-06 Intel Corporation Method and apparatus for transitioning a processor state from a first performance mode to a second performance mode
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US7539878B2 (en) 2001-09-19 2009-05-26 Freescale Semiconductor, Inc. CPU powerdown method and apparatus therefor
US7080269B2 (en) 2003-05-15 2006-07-18 International Business Machines Corporation Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
US7085943B2 (en) 2003-09-26 2006-08-01 Freescale Semiconductor, Inc. Method and circuitry for controlling supply voltage in a data processing system
US7042274B2 (en) 2003-09-29 2006-05-09 Intel Corporation Regulated sleep transistor apparatus, method, and system
US6903994B1 (en) 2003-11-14 2005-06-07 Micron Technology, Inc. Device, system and method for reducing power in a memory device during standby modes
US7382178B2 (en) 2004-07-09 2008-06-03 Mosaid Technologies Corporation Systems and methods for minimizing static leakage of an integrated circuit
US7262631B2 (en) 2005-04-11 2007-08-28 Arm Limited Method and apparatus for controlling a voltage level
US7099230B1 (en) * 2005-04-15 2006-08-29 Texas Instruments Incorporated Virtual ground circuit for reducing SRAM standby power
US7522941B2 (en) 2005-05-23 2009-04-21 Broadcom Corporation Method and apparatus for reducing standby power consumption of a handheld communication system
US7657767B2 (en) * 2005-06-30 2010-02-02 Intel Corporation Cache leakage shut-off mechanism
US7271615B2 (en) * 2005-08-16 2007-09-18 Novelics, Llc Integrated circuits with reduced leakage current
JP2007104572A (ja) * 2005-10-07 2007-04-19 Sony Corp 半導体装置
JP2007150761A (ja) * 2005-11-28 2007-06-14 Oki Electric Ind Co Ltd 半導体集積回路及びリーク電流低減方法
KR100735677B1 (ko) * 2005-12-28 2007-07-04 삼성전자주식회사 스탠바이 전류 저감 회로 및 이를 구비한 반도체 메모리장치
JP4819870B2 (ja) * 2006-02-24 2011-11-24 ルネサスエレクトロニクス株式会社 半導体装置
US7385435B2 (en) 2006-06-29 2008-06-10 Intel Corporation Programmable power gating circuit
DE102007002150A1 (de) * 2007-01-15 2008-07-31 Infineon Technologies Ag Konzept zur Reduktion von Leckströmen von integrierten Schaltungen mit wenigstens einem Transistor
US7583126B2 (en) * 2007-05-24 2009-09-01 Nvidia Corporation Apparatus and method for preventing current leakage when a low voltage domain is powered down
US7808856B2 (en) 2007-06-20 2010-10-05 International Business Machines Corporation Method to reduce leakage of a SRAM-array
JP5011168B2 (ja) * 2008-03-04 2012-08-29 日本電信電話株式会社 仮想視点画像生成方法、仮想視点画像生成装置、仮想視点画像生成プログラムおよびそのプログラムを記録したコンピュータ読み取り可能な記録媒体
JP5374120B2 (ja) 2008-11-14 2013-12-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Also Published As

Publication number Publication date
EP2577422A2 (en) 2013-04-10
JP2013528300A (ja) 2013-07-08
EP2577422A4 (en) 2016-08-10
US20110296211A1 (en) 2011-12-01
EP2577422B1 (en) 2018-07-11
CN102906665B (zh) 2015-07-29
WO2011149606A2 (en) 2011-12-01
CN102906665A (zh) 2013-01-30
WO2011149606A3 (en) 2012-02-02
US8489906B2 (en) 2013-07-16

Similar Documents

Publication Publication Date Title
JP5791207B2 (ja) 複数の低電力モードを有するデータプロセッサ
Yamaoka et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
CN102844817B (zh) 在正常操作模式及rta模式中操作存储器的方法和集成电路
US7583121B2 (en) Flip-flop having logic state retention during a power down mode and method therefor
US9189052B2 (en) Voltage regulation for data retention in a volatile memory
US10536139B2 (en) Charge-saving power-gate apparatus and method
US20050135162A1 (en) Method and apparatus to clamp SRAM supply voltage
KR101293528B1 (ko) 듀얼-기술 트랜지스터들을 사용한 저누설 고성능 정적 랜덤 액세스 메모리 셀
US20040105299A1 (en) Storage array such as a SRAM with reduced power requirements
US20090189636A1 (en) Circuit having logic state retention during power-down and method therefor
US20120106285A1 (en) Circuits and methods for reducing minimum supply for register file cells
US7196960B2 (en) Semiconductor integrated circuit
CN103650052B (zh) 用于存储器的电路和方法
US8319548B2 (en) Integrated circuit having low power mode voltage regulator
US8723592B2 (en) Adjustable body bias circuit
US7345947B2 (en) Memory array leakage reduction circuit and method
US8566620B2 (en) Data processing having multiple low power modes and method therefor
US8743647B2 (en) Static read only memory device which consumes low stand-by leakage current
US20080030224A1 (en) Logic with state retentive sleep mode
US20160148657A1 (en) A non-volatile semiconductor memory device with temporary data retention cells and control method thereof
US7010706B2 (en) Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential
Yokoyama et al. 40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65° C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications
US20040174762A1 (en) Deep power down switch for memory device
US20080037354A1 (en) Word line voltage control circuit for memory devices

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140407

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140407

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150317

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150615

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150707

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150803

R150 Certificate of patent or registration of utility model

Ref document number: 5791207

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250