JP5684697B2 - クリッピング回路、差動増幅回路および増幅回路 - Google Patents
クリッピング回路、差動増幅回路および増幅回路 Download PDFInfo
- Publication number
- JP5684697B2 JP5684697B2 JP2011276243A JP2011276243A JP5684697B2 JP 5684697 B2 JP5684697 B2 JP 5684697B2 JP 2011276243 A JP2011276243 A JP 2011276243A JP 2011276243 A JP2011276243 A JP 2011276243A JP 5684697 B2 JP5684697 B2 JP 5684697B2
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- signal
- circuit
- clipping
- voltage
- amplifier
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- 230000003321 amplification Effects 0.000 claims description 11
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/06—Volume compression or expansion in amplifiers having semiconductor devices
- H03G7/08—Volume compression or expansion in amplifiers having semiconductor devices incorporating negative feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/66—Clipping circuitry being present in an amplifier, i.e. the shape of the signal being modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45481—Indexing scheme relating to differential amplifiers the CSC comprising only a direct connection to the supply voltage, no other components being present
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
NMOSトランジスタMa1、Ma2のバイアス電圧が閾値以下の場合には、増幅素子としてのNMOSトランジスタMa1、Ma2と、クリッピング素子としてのNMOSトランジスタMc1,Mc2のバイアス供給を共通化することで構成を簡易にできる。両者のバイアス点を別途設定する必要がある場合には、容量結合などを用いてDCカットし、別々にバイアス電圧を供給すればよい(図2参照)。
Claims (5)
- クリッピング対象としての差動信号を形成する第1および第2信号のうち前記第1信号を受ける第1入力端子と、
前記第2信号を受ける第2入力端子と、
制御端子が前記第2入力端子に電気的に接続され、一端が前記第1入力端子に接続され、他端が基準電圧に接続され、閾値を有する第1可変抵抗素子と、
制御端子が前記第1入力端子に電気的に接続され、一端が前記第2入力端子に接続され、他端が前記基準電圧に接続され、前記閾値を有する第2可変抵抗素子と、
前記第1可変抵抗素子の制御端子に前記閾値よりも低いバイアス電圧を与える第1バイアス印加手段と、
前記第2可変抵抗素子の制御端子に前記閾値よりも低いバイアス電圧を与える第2バイアス印加手段と、
を備えたクリッピング回路。 - 請求項1に記載のクリッピング回路と、
前記第1入力端子の電圧に応じた信号を増幅して出力する第1増幅素子と、
前記第2入力端子の電圧に応じた信号を増幅して出力する第2増幅素子と、
を備えた差動増幅回路。 - 前記第1可変抵抗素子、前記第2可変抵抗素子、前記第1増幅素子および前記第2増幅素子は、同一の製造プロセスにより製造されたデバイスである
ことを特徴とする請求項2に記載の差動増幅回路。 - 増幅対象となる差動信号を第1差動信号および第2差動信号に分割する電力分割部と、
前記第1差動信号を増幅するメインアンプと、
前記第2差動信号を増幅する、請求項2または3にしたがった差動増幅回路を含むサブアンプと、
前記メインアンプの出力と前記サブアンプの出力を合成する電力合成部と
を備えた差動ドハティ電力増幅器。 - 前記第1の可変抵抗素子、前記第2の可変抵抗素子、前記第1増幅素子および前記第2増幅素子は、同型の半導体素子であることを特徴とする請求項2に記載の差動増幅回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011276243A JP5684697B2 (ja) | 2011-12-16 | 2011-12-16 | クリッピング回路、差動増幅回路および増幅回路 |
US13/709,574 US8860509B2 (en) | 2011-12-16 | 2012-12-10 | Clipping circuit, differential amplifying circuit, and amplifying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011276243A JP5684697B2 (ja) | 2011-12-16 | 2011-12-16 | クリッピング回路、差動増幅回路および増幅回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013128173A JP2013128173A (ja) | 2013-06-27 |
JP5684697B2 true JP5684697B2 (ja) | 2015-03-18 |
Family
ID=48609539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011276243A Expired - Fee Related JP5684697B2 (ja) | 2011-12-16 | 2011-12-16 | クリッピング回路、差動増幅回路および増幅回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8860509B2 (ja) |
JP (1) | JP5684697B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9071202B2 (en) * | 2013-10-18 | 2015-06-30 | Alcatel Lucent | Doherty amplifier with peak branch RF conditioning |
JPWO2023063316A1 (ja) * | 2021-10-13 | 2023-04-20 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357156A (en) * | 1992-07-10 | 1994-10-18 | Lattice Semiconductor Corporation | Active clamp circuit scheme for CMOS devices |
JPH1188065A (ja) * | 1997-09-11 | 1999-03-30 | Mitsubishi Electric Corp | 半導体増幅回路 |
US6580321B1 (en) * | 2001-08-24 | 2003-06-17 | Anadigics, Inc. | Active clamping circuit for power amplifiers |
JP3966016B2 (ja) * | 2002-02-26 | 2007-08-29 | 株式会社デンソー | クランプ回路 |
JP3850399B2 (ja) * | 2003-09-10 | 2006-11-29 | ローム株式会社 | 半導体集積回路装置 |
JP4142059B2 (ja) * | 2006-04-11 | 2008-08-27 | 日本バーブラウン株式会社 | 積分回路 |
JP2008154286A (ja) * | 2008-03-17 | 2008-07-03 | Hitachi Kokusai Electric Inc | ドハティ増幅器 |
-
2011
- 2011-12-16 JP JP2011276243A patent/JP5684697B2/ja not_active Expired - Fee Related
-
2012
- 2012-12-10 US US13/709,574 patent/US8860509B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8860509B2 (en) | 2014-10-14 |
US20130154745A1 (en) | 2013-06-20 |
JP2013128173A (ja) | 2013-06-27 |
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