JP5651178B2 - 集積回路スイッチ、設計構造体及びその製造方法 - Google Patents
集積回路スイッチ、設計構造体及びその製造方法 Download PDFInfo
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- JP5651178B2 JP5651178B2 JP2012526823A JP2012526823A JP5651178B2 JP 5651178 B2 JP5651178 B2 JP 5651178B2 JP 2012526823 A JP2012526823 A JP 2012526823A JP 2012526823 A JP2012526823 A JP 2012526823A JP 5651178 B2 JP5651178 B2 JP 5651178B2
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- mems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0035—Constitution or structural means for controlling the movement of the flexible or deformable elements
- B81B3/004—Angular deflection
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/0015—Cantilevers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00277—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H1/00—Contacts
- H01H1/0036—Switches making use of microelectromechanical systems [MEMS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/01—Switches
- B81B2201/012—Switches characterised by the shape
- B81B2201/014—Switches characterised by the shape having a cantilever fixed on one side connected to one or more dimples
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0136—Growing or depositing of a covering layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0145—Hermetically sealing an opening in the lid
Description
図19は、好ましくは設計プロセス910によって処理される入力設計構造体920を含む、複数のこのような設計構造体を例示する。設計構造体920は、設計プロセス910によって生成され、処理され、ハードウェア・デバイスの論理的に等価な機能的表現を生じる、論理シミュレーション設計構造体とすることができる。設計構造体920はさらに、或いは代替的に、設計プロセス910によって処理されたときに、ハードウェア・デバイスの物理的構造の機能的表現を生成するデータ及び/又はプログラム命令を含むこともできる。機能的及び/又は構造的設計特徴のどちらを表現するのであれ、設計構造体920は、コア開発者/設計者によって実施されるような電子的コンピュータ支援設計(ECAD)を用いて生成することができる。機械可読データ伝送、ゲートアレイ、又はストレージ媒体上でコード化された場合、設計プロセス910内の1つ又は複数のハードウェア及び/又はソフトウェア・モジュールによって、設計構造体920にアクセスし、これを処理して、図1−図18に示されるもののような電子コンポーネント、回路、電子若しくは論理モジュール、装置、デバイス、又はシステムをシミュレーションするか、又は他の方法で機能的に表現することができる。そのため、設計構造体920は、設計又はシミュレーション・データ処理システムによって処理されたときに、回路又は他のレベルのハードウェア論理設計を機能的にシミュレーションするか、又は他の方法で表現する、人間及び/又は機械可読のソースコード、コンパイルされた構造体、及びコンピュータ実行可能コード構造体を含む、ファイル又は他のデータ構造体を含むことができる。このようなデータ構造体は、ハードウェア記述言語(HDL)設計エンティティ、又は、Verilog及びVHDLのような低レベルHDL設計言語、及び/又は、C若しくはC++のような高レベル設計言語に適合する及び/又はこれと互換性のある他のデータ構造体を含むことができる。
12、18、20、24、28、52:配線(配線層)
14:SiN層
28a:下部コンタクト電極(配線)
28b:強制電極(配線)
28c:強制電極(配線)
30:金の薄層
32、36、48:犠牲材料
32a:タブ
34:カンチレバー梁
38:キャップ
40:開口部
42:SiN材料
44:犠牲層
50a、50b:キャビティ
50c、56:ビア
58:ボイド
60:酸化物材料
62:窒化物材料
910:設計プロセス
920、990:設計構造体
930:ライブラリ要素
940:設計仕様
950:特徴データ
960:検証データ
970:設計ルール
980:ネットリスト
985:試験データ・ファイル
995:ステージ
Claims (4)
- MEMSスイッチを製造する方法であって、
断面形状において略中央部に位置するビアによって接続され、犠牲材料で一時的に充填される下部及び上部キャビティ内にMEMS構造体を形成するステップであって、前記MEMS構造体は、前記下部及び上部キャビティの間の前記ビアの両側の少なくとも一方に設けられ、前記下部キャビティは、犠牲材料から形成された少なくとも1つのタブを含む、ステップと、
前記下部及び上部キャビティの部分、並びに、前記MEMS構造体の上を囲む誘電体層を形成するステップと、
前記下部キャビティの上の前記MEMS構造体の側部の前記誘電体層内に前記少なくとも1つのタブに至る通気孔を開口するステップと、
ドライ又はウェット・エッチング剤を用いて、前記通気孔を介して前記犠牲材料を剥離し、前記MEMS構造体の周りにボイドを形成するステップと、
前記通気孔をキャッピング材料で密封するステップと、を含む方法。 - 前記下部キャビティはその表面に、前記MEMS構造体のコンタクト電極及び強制電極を含む、請求項1に記載の方法。
- 前記通気孔は、前記少なくとも1つのタブの上に完全に位置合わせされる、前記少なくとも1つのタブに対してオフセットされる、及び前記少なくとも1つのタブの側部に形成される、の中から選択された1つである、請求項1に記載の方法。
- 前記犠牲材料はシリコンであり、前記剥離することはXeF2ガスを用いて行われる、または、前記犠牲材料はPMGIであり、前記剥離することはN−メチル−2−ピロリジン(NMP)及び/又はジメチルスルホキシド(DMSO)ベースの除去剤を用いて行われる、のうちの一方である、請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/548,697 US8569091B2 (en) | 2009-08-27 | 2009-08-27 | Integrated circuit switches, design structure and methods of fabricating the same |
US12/548,697 | 2009-08-27 | ||
PCT/US2010/045248 WO2011028384A1 (en) | 2009-08-27 | 2010-08-12 | Integrated circuit switches, design structure and methods of fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013503446A JP2013503446A (ja) | 2013-01-31 |
JP5651178B2 true JP5651178B2 (ja) | 2015-01-07 |
Family
ID=43533073
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012526823A Active JP5651178B2 (ja) | 2009-08-27 | 2010-08-12 | 集積回路スイッチ、設計構造体及びその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8569091B2 (ja) |
JP (1) | JP5651178B2 (ja) |
CN (1) | CN102471048A (ja) |
DE (2) | DE112010003412T5 (ja) |
GB (2) | GB2485714B8 (ja) |
TW (1) | TWI529120B (ja) |
WO (1) | WO2011028384A1 (ja) |
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2009
- 2009-08-27 US US12/548,697 patent/US8569091B2/en active Active
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2010
- 2010-08-06 TW TW099126309A patent/TWI529120B/zh active
- 2010-08-12 DE DE112010003412T patent/DE112010003412T5/de not_active Ceased
- 2010-08-12 JP JP2012526823A patent/JP5651178B2/ja active Active
- 2010-08-12 WO PCT/US2010/045248 patent/WO2011028384A1/en active Application Filing
- 2010-08-12 DE DE112010006130.0T patent/DE112010006130B3/de active Active
- 2010-08-12 CN CN2010800354400A patent/CN102471048A/zh active Pending
- 2010-08-12 GB GB1203306.4A patent/GB2485714B8/en not_active Expired - Fee Related
- 2010-08-12 GB GB1321363.2A patent/GB2506770B8/en not_active Expired - Fee Related
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2013
- 2013-09-16 US US14/027,939 patent/US9284185B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
GB2506770A (en) | 2014-04-09 |
GB2485714B8 (en) | 2015-09-23 |
TWI529120B (zh) | 2016-04-11 |
DE112010006130B3 (de) | 2019-06-27 |
US9284185B2 (en) | 2016-03-15 |
DE112010003412T5 (de) | 2012-08-16 |
WO2011028384A1 (en) | 2011-03-10 |
GB2506770B (en) | 2014-08-20 |
US20140017844A1 (en) | 2014-01-16 |
TW201121876A (en) | 2011-07-01 |
GB2485714A (en) | 2012-05-23 |
US8569091B2 (en) | 2013-10-29 |
GB2506770A8 (en) | 2015-09-23 |
JP2013503446A (ja) | 2013-01-31 |
CN102471048A (zh) | 2012-05-23 |
GB201203306D0 (en) | 2012-04-11 |
GB2506770B8 (en) | 2015-09-23 |
GB2485714B (en) | 2014-05-14 |
GB2485714A8 (en) | 2015-09-23 |
GB201321363D0 (en) | 2014-01-15 |
US20110049649A1 (en) | 2011-03-03 |
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