JP5650337B2 - CMOS image sensor pixel and control sequence thereof - Google Patents

Description

The present application is the priority of the Chinese patent application filed with the Chinese Patent Office on April 15, 2011 with the application number 2011010095448.2 and the title of the invention "CMOS image sensor pixel readout circuit structure and its control sequence". The entire content of which is claimed and incorporated herein by reference.

The present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor pixel and its control sequence.

  Currently, image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications. In particular, due to the rapid development of CMOS (complementary metal oxide semiconductor) image sensors, there is an increasing demand for low output, small size, high resolution image sensors.

  The arrangement of the CMOS image sensor pixel structure in the prior art depends on the structural characteristics of the pixel itself, taking 4T2S as an example, and the array generally consists of a first layer metal, a second layer metal, and a third layer metal. The metal in the first layer needs to be interconnected as an element, and the pixels in the first layer in the plurality of rows or the metal in the second layer need to be connected between the pixels in the adjacent rows. It is necessary to connect the second layer metal or the first layer metal in a plurality of rows between them.

The prior art described above includes at least the following drawbacks.
Small pixel sensors have a small photosensitive area, low sensitivity, and information transfer under dark light is not clear enough. In particular, when the first layer metal, the second layer metal, and the third layer metal are interconnected as an element, the height of the medium on the surface of the photodiode Si (silicon) is relatively high, It affects the incidence of light on the photodiode. A plurality of metal lines between pixels in adjacent rows and adjacent columns lowers the aperture ratio of the metal window.

An object of the present invention is to provide a small CMOS image sensor pixel having a relatively large metal window aperture ratio and high sensitivity, and a control sequence thereof.

The object of the present invention is realized by the following technical technique.

  The CMOS image sensor pixel of the present invention includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, and an active region.

  Specifically, four pixels are arranged in a 2 × 2 pixel array to form a set of pixel cells. The two pixels in the first column and the second column each share a selection transistor, a source follower transistor, a reset transistor and an active region in the column, and the first column and the second column are arranged back to back. .

  A plurality of sets of pixel cells are arranged so as to form a two-dimensional pixel array in the vertical and horizontal directions, and pixels in the same row realize element connection by a metal wire of the second layer. The connection of the element is realized by the metal wire of the layer.

  The arrangement method of the elements of the two pixels in the first column is as follows.

  The selection transistor (SX1) and the source follower transistor (SF1) are located above the photodiode (PD11) of the pixel (11), and the reset transistor (RX1) is the photodiode (PD11) of the pixel (11) and the pixel (21). It is located between the photodiode (PD21).

  The arrangement method of the elements of the two pixels in the second column is as follows.

  The selection transistor (SX2) and the source follower transistor (SF2) are located below the photodiode (PD22) of the pixel (22), and the reset transistor (RX2) is the photodiode (PD12) of the pixel (12) and the pixel (22). It is located between the photodiode (PD22).

  In the arrangement method of the elements of the two pixels in the first column, the selection transistor (SX1) is located on the left side of the source follower transistor (SF1).

  In the arrangement method of the elements of the two pixels in the second column, the selection transistor (SX2) is located on the right side of the source follower transistor (SF2).

  In the arrangement method of the elements of the two pixels in the first column, the active region (FD1) is provided between the photodiode (PD11) of the pixel (11) and the photodiode (PD21) of the pixel (21), and a reset transistor ( It is located on the right side of RX1).

  In the arrangement method of the elements of the two pixels in the second column, the active region (FD2) is provided between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22), and a reset transistor ( It is located on the left side of RX2).

  In the arrangement method of the elements of the two pixels in the first column, the active region (FD1) is connected to the gate of the source follower transistor (SF1) by the metal line of the first layer.

  In the arrangement method of the elements of the two pixels in the second column, the active region (FD2) is connected to the gate of the source follower transistor (SF2) by the metal line of the first layer.

  The CMOS image sensor pixel may include a pixel array including a plurality of pixel cell sets.

  The above described CMOS image sensor pixel control sequence of the present invention includes a CMOS image sensor pixel array row decoder sequence and a column controller sequence.

  The metal lines of the first layer are signal output lines, column controller sequence control lines, and power supply control lines.

  The second layer metal line is a row decoder sequence output control line.

  As can be seen from the above description, the CMOS image sensor pixel according to the present invention employs a 4T2S structure (four transistors, two pixels share a selection transistor, a source follower transistor, and a reset transistor). Four pixels are arranged in a 2 × 2 pixel array to form one set. Two pixels in the first column and the second column share a selection transistor, a source follower transistor, and a reset transistor, respectively, in the column, and the first column and the second column are arranged back to back.

  The CMOS image sensor pixel array of the present invention uses only the metal of the first layer and the metal of the second layer as element interconnections. The third layer metal is not used as an element interconnect, and the height of the medium on the surface of the photodiode Si (silicon) can be lowered and more light can be incident on the photodiode. According to the CMOS image sensor pixel structure and the arrangement method of each transistor of the present invention, only two rows of second-layer metal lines are arranged between adjacent row pixels, and two columns of first layers are arranged between adjacent column pixels. The function can be realized by arranging only the metal wires. This metal wire structure effectively increases the metal window aperture ratio.

  Also, based on the pixel structure of the present invention, two types of control sequences can be used: a CMOS image sensor pixel array row decoder sequence and a column controller sequence.

  Since the CMOS image sensor pixel structure of the present invention can improve the sensitivity by increasing the light utilization efficiency of the small area pixel sensor, the image quality of the small area pixel image sensor can be effectively increased.

FIG. 4 is a schematic diagram of a back-to-back structure layout of 4T2S composed of four pixels in a specific example of a CMOS image sensor pixel provided by the present invention. FIG. 3 is a schematic diagram of a back-to-back structure circuit of 4T2S composed of four pixels in a specific example of a CMOS image sensor pixel provided by the present invention. FIG. 5 is a schematic diagram of a 6 × 4 pixel array layout in a specific example of a CMOS image sensor pixel provided by the present invention. FIG. 6 is a schematic diagram of a 6 × 4 pixel array circuit in a specific example of a CMOS image sensor pixel provided by the present invention. FIG. 2 is a schematic diagram of a pixel array with a row decoder and a column controller in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 3 is a schematic diagram of a row decoder sequence and a column controller sequence of a pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention.

  A preferred specific embodiment of the CMOS image sensor pixel and its control sequence according to the present invention is as shown in FIGS.

  A photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, an active region, a first-layer metal line, and a second-layer metal line are included. The pixels 11 and 21 located in the pixel array column 1 share the selection transistor SX1, the source follower transistor SF1, the reset transistor RX1, and the active region FD1. The pixel 12 and the pixel 22 located in the pixel array column 2 share the selection transistor SX2, the source follower transistor SF2, the reset transistor RX2, and the active region FD2. The selection transistor SX1 and the source follower transistor SF1 are located above the photodiode PD11 of the pixel 11, and the reset transistor RX1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21. The selection transistor SX2 and the source follower transistor SF2 are located below the photodiode PD22 of the pixel 22, and the reset transistor RX2 is located between the photodiode PD11 of the pixel 12 and the photodiode PD11 of the pixel 22. The pixel 11 and the pixel 21 form a back-to-back structure in the horizontal direction with the pixel 12 and the pixel 22.

  The selection transistor SX1 is located on the left side of the source follower transistor SF1. The selection transistor SX2 is located on the right side of the source follower transistor SF2.

  The active region FD1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21 on the right side of the reset transistor RX1. The active region FD2 is located between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22 on the left side of the reset transistor RX2.

  The active region FD1 is connected to the gate of the source follower transistor SF1 by a metal line of the first layer. The active region FD2 is connected to the gate of the source follower transistor SF2 by a metal line of the first layer.

  The metal line Vdd of the first layer of the power supply is connected to the drains of SF1 and SF2.

  The metal line SC1 of the first layer is connected to the source of the selection transistor SX1, and the gate and source of the reset transistor RX1. The first-layer metal line SC2 is connected to the source of the select transistor SX2 and the gate and source of the reset transistor RX2. The first-layer metal line SC1 and the first-layer metal line SC2 are a signal output line and a column controller sequence control line.

  The second-layer metal line SX is connected to the gates of the selection transistor SX1 and the selection transistor SX2.

  The second-layer metal line TX1 is connected to the gates of the charge transfer transistor TX11 and the charge transfer transistor TX12. The second-layer metal line TX2 is connected to the gates of the charge transfer transistor TX21 and the charge transfer transistor TX22.

  The second-layer metal line SX, the second-layer metal line TX1, and the second-layer metal line TX2 are row decoder sequence output control lines.

  The present invention solves the problem that a conventional image sensor has low sensitivity of a small area pixel.

<Specific Example 1>
As shown in FIG. 1, the CMOS image sensor pixel adopts a 4T2S structure, includes four pixels, and the photodiodes of the pixel 11, the pixel 12, the pixel 21, and the pixel 22 are PD11, PD12, PD21, and PD22, respectively. . TX11 and TX12 are charge transfer transistors of the pixel 11 and pixel 12, respectively, and TX21 and TX22 are charge transfer transistors of the pixel 21 and pixel 22, respectively. SX1, SF1, and RX1 are a selection transistor, a source follower transistor, and a reset transistor of the pixel 11 and the pixel 21, respectively. SX2, SF2, and RX2 are a selection transistor, a source follower transistor, and a reset transistor of the pixel 12 and the pixel 22, respectively. The pixel 11 and the pixel 21 share the transistors SX1, SF1, RX1, and the active region FD1 (Floating Diffusion), and the pixel 12 and the pixel 22 share the transistors SX2, SF2, RX2, and the active region FD2. The shared pixels 11 and 21 and the shared pixels 12 and 22 form a structure that is adjacent in the horizontal direction.

  The metal interconnections used in CMOS image sensor pixels are as follows. The active region FD1 is connected to the SF1 gate by the first layer metal line. The active region FD2 is connected to the SF2 gate by the first layer metal line. The metal line Vdd of the first layer of the power supply is connected to the drains of SF1 and SF2. The SC1 line is a first layer metal line, connected to the source of SX1, connected to the gate and source of RX1, the first layer metal line of SC1 is a signal output line, and a column controller sequence control line But there is. SC2 line is the first layer metal line, connected to the source of SX2, connected to the gate and source of RX2, SC2 first layer metal line is the signal output line, also column controller sequence control line is there. The SX line is a second-layer metal line and is connected to the gates of SX1 and SX2. The TX1 line is a second layer metal line and is connected to the gates of TX11 and TX12. The TX2 line is a second-layer metal line and is connected to the gates of TX21 and TX22. The SX second layer metal line, the TX1 second layer metal line, and the TX2 second layer metal line are all row decoder sequence output control lines.

As shown in FIG. 2, the above is a schematic diagram of a layout structure composed of four pixels. The above-mentioned four pixels are set as one set, and a plurality of sets of adjacent pixels are arranged in the vertical and horizontal directions. A dimensional pixel array is formed.

<Specific Example 2>
FIG. 3 is a schematic diagram of a 6 × 4 pixel array layout. A circuit schematic diagram corresponding to the pixel array layout schematic diagram shown in FIG. 3 is as shown in FIG.

  In the pixel arrays shown in FIG. 3 and FIG. 4, the FD region of each pixel is connected to the corresponding source follower transistor gate and the first layer metal line, and the power supply Vdd line is the first layer metal line. Is used. SC1 to SC6 lines are first-layer metal lines, and are signal output lines and column controller sequence control lines. The second layer metal line SX1 is connected to the gates of SX11 to SX16, the second layer metal line TX1 is connected to the gates of TX11 to TX16, and the second layer metal line TX2 is the gate of TX21 to TX26. Connected to. The second layer metal line SX2 is connected to the gates of SX21 to SX26, the second layer metal line TX3 is connected to the gates of TX31 to TX36, and the second layer metal line TX4 is the gate of TX41 to TX46. Connected to. In this two-dimensional pixel array, interconnects are made using only two layers of metal, there are only two rows of second-layer metal lines between adjacent row pixels, and two columns between adjacent column pixels. There is only a metal wire of the first layer. The present invention effectively increases the sensitivity of small area pixel sensors by using only two layers of metal and a high metal window aperture ratio.

<Specific Example 3>
Details of the CMOS image sensor pixel array signal acquisition are as follows.

  FIG. 5 is a schematic diagram of a pixel array with a row decoder and a column controller. The row decoder is placed on the left side of the pixel array (may be placed on the right side of the array), the column controller is placed on the top of the pixel array, and the signal readout element is placed on the bottom of the pixel array. The positions of the decoder, the controller, and the signal reading element are not the only methods of the present invention, and may be adjusted according to the specific design layout of the chip. In the schematic shown in FIG. 5, specific positions of the array pixels are specified in detail, and specific numbers of decoder sequence output control lines and column controller sequence control lines are also specified in detail. m and n are non-negative integers and represent the row and column positions of the pixels of the pixel array, respectively. For example, the pixel (2m + 1, 2n + 1) indicates that the position of this pixel is in the (2m + 1) th row and the (2n + 1) th column. The metal line Vdd is a power supply line, and when the sensor is operating normally, Vdd is a power supply voltage. The metal line SC is a signal output line and a column controller sequence control line, and the metal lines SX and TX are row decoder sequence output control lines.

  FIG. 6 is a schematic diagram of a row decoder output sequence and a column controller sequence employed in the CMOS image sensor pixel array. The pixel array of the present invention employs all N-type transistors. When the gate of the N-type transistor is placed at a high level, that is, when the signal at the gate of this transistor is controlled to be placed at a high level, it indicates that the transistor is on. When the gate of an N-type transistor is placed at a low level, that is, when the signal at the gate of this transistor is controlled to be placed at a low level, it indicates that the transistor is turned off. The control of the length of the on-time of the N-type transistor, that is, the length of time for which the signal of the gate of this transistor is placed at a high level depends on the specific situation of the operation of the sensor. When the signal readout element at the bottom of the pixel array reads the signal, the SC line is converted from the column controller sequence control line to the signal output line, and the signal readout element reads the signal through the signal output line. In FIG. 6, a rectangle having a diagonal line indicates an operation in which the signal reading element reads the pixel signal. After the pixel signal is read by the signal reading element, the signal output line is converted into a column controller sequence control line.

  When the CMOS image sensor pixel array of the present invention operates normally, a row scroll type exposure method is adopted, pixels in the 2m + 1 row start exposure first, then pixels in the 2m + 2 row start exposure, It becomes 2m + 3 line and 2m + 4 line. The order of completion of exposure is the same as the order of exposure start. The signal reading order of the pixels in each row is also the same as the exposure start order of the row pixels. When the sensor collects pixel array signals for the same frame, the exposure times for the pixels in each row are equal.

  Next, sequence control of pixels in one row will be described in detail. The row pixel exposure time is from the first high level falling edge of the TX signal to the next high level falling edge of the TX signal. Prior to the start of the exposure time, the charge placed in the potential well of the pixel photodiode must be removed, i.e., the SX signal is at a low level and the TX and SC signals are placed from a low level to a high level. The charge transfer transistor and the reset transistor are turned on. After the charge placed in the potential well of the pixel photodiode is removed, the charge transfer transistor is first turned off and then the reset transistor is turned off, ie, the SX signal is at a low level, the TX signal and the SC The signal is placed at a low level in order from the high level, and at this time, the pixel photodiode starts exposure. During pixel exposure, the TX signal is always low. Before the end of the exposure time, it is necessary to collect the pixel reset signal, first the SX and TX signals are at a low level, the SC signal is placed from a low level to a high level, and the corresponding FD area of the pixel is Reset to high level. After resetting the FD region to a high level, the SC signal is placed from a high level to a low level, turning off the reset transistor. The SC line is then converted from the column controller control line to the signal output line, the TX signal is kept low, the SX signal is placed from low to high, the select transistor is turned on, via the signal output line, The signal reading element reads and stores the signal of each pixel in the entire corresponding row to obtain signal 1. After reading signal 1, the SX signal remains high, the signal readout element stops reading the pixel signal, the SC line is converted from the signal output line to the column controller control line, and the SC signal is placed low. The SC signal is at a low level, the SX signal is at a high level, the TX signal is placed from a low level to a high level, the charge transfer transistor is turned on, and the photoelectric charge in the potential well of the photodiode is changed to the corresponding FD of the pixel. Move to the area.

  After the photoelectric charge in the potential well of the pixel photodiode has moved to the corresponding FD region of the pixel, the charge transfer transistor is turned on, that is, the SC sequence is low, the SX sequence is high, and the TX sequence is From the high level to the low level, the exposure time ends. Next, the SC line is converted from the column controller control line to the signal output line, and the signal of each pixel in the corresponding row is read by the signal reading element via the signal output line to obtain the signal 2. After reading signal 2, the signal readout element stops reading the pixel signal, the SX sequence is placed from high level to low level, and the SC line is converted from the signal output line to the column controller control line.

  The sequence control method employed in the CMOS image sensor pixel array of the present invention is not the only method. For example, when the signal readout element sequentially reads the signal 1 and the signal 2 of the same pixel of the same frame via the signal output line, after reading the signal 1, the SX sequence is first placed from the high level to the low level, Before the selection transistor is turned off and the signal 2 is read, the signal 2 may be read by the signal read element after the SX sequence is further changed from low level to high level to turn on the selection transistor. The photoelectric signal collected by the sensor pixel is read and recorded by the signal reading element, and the actual photoelectric signal is a difference signal between the signal 1 and the signal 2.

  The above is only a preferred specific embodiment of the present invention, and the protection scope of the present invention is not limited to this. Any change or replacement readily conceivable by those skilled in the art within the technical scope disclosed in the present invention shall fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (9)

A CMOS image sensor pixel including a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, and an active region,
Four pixels are arranged in a 2 × 2 pixel array to form a set of pixel cells,
Two pixels in the first column and the second column each share a selection transistor, a source follower transistor, a reset transistor and an active region in the column;
The first column and the second column are arranged adjacent to each other ;
Arranging a plurality of sets of pixel cells to form a two-dimensional pixel array vertically and horizontally,
The pixels in the same row realize element connection by the second layer metal line , and in the one set of pixel cells, the element connection is realized by two second layer metal lines,
The pixels in the same column realize the connection of the elements by the metal wire of the first layer ,
The arrangement method of the elements of the two pixels in the first column is:
The selection transistor (SX1) and the source follower transistor (SF1) are located above the photodiode (PD11) of the pixel (11), and the reset transistor (RX1) is the photodiode (PD11) of the pixel (11) and the pixel (21). Located between the photodiode (PD21)
The arrangement of the elements of the two pixels in the second column is as follows:
The selection transistor (SX2) and the source follower transistor (SF2) are positioned below the photodiode (PD22) of the pixel (22), and the reset transistor (RX2) is the photodiode (PD12) of the pixel (12) and the pixel (22). A CMOS image sensor pixel, which is located between the photodiode (PD22) and the photodiode . In the arrangement method of the elements of the two pixels in the first column, the selection transistor (SX1) is located on the left side of the source follower transistor (SF1),
2. The CMOS image sensor pixel according to claim 1 , wherein in the arrangement of the elements of the two pixels in the second column, the selection transistor (SX2) is located on the right side of the source follower transistor (SF2). In the arrangement method of the elements of two pixels in the first column, the active region (FD1) is between the photodiode (PD11) of the pixel (11) and the photodiode (PD21) of the pixel (21), Located on the right side of the reset transistor (RX1)
In the arrangement of elements of two pixels in the second column, the active region (FD2) is between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22), The CMOS image sensor pixel according to claim 2 , wherein the pixel is located on the left side of the reset transistor (RX2). In the arrangement method of the elements of the two pixels in the first column, the active region (FD1) is connected to the gate of the source follower transistor (SF1) by the metal line of the first layer,
In the arrangement scheme of the elements of the two pixels in the second row, the active region (FD2) in claim 3, wherein the connecting a metal wire of the gate and the first layer of the source follower transistor (SF2) A CMOS image sensor pixel as described. The CMOS image sensor pixel according to claim 1 , wherein the CMOS image sensor pixel includes a pixel array including a plurality of sets of the pixel cells. The control sequence of the CMOS image sensor pixel according to claim 1 , wherein the control sequence includes a row decoder sequence and a column controller sequence of the CMOS image sensor pixel array. The first layer metal lines are signal output lines and column controller sequence control lines;
7. The control sequence of a CMOS image sensor pixel according to claim 6 , wherein the metal line of the second layer is a row decoder sequence output control line. 6. The control sequence of CMOS image sensor pixels according to claim 5 , wherein the control sequence includes a CMOS image sensor pixel array row decoder sequence and a column controller sequence. The first layer metal lines are signal output lines and column controller sequence control lines;
9. The control sequence of a CMOS image sensor pixel according to claim 8 , wherein the metal line of the second layer is a row decoder sequence output control line.

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