CN109887947B - Image sensor with compact design layout - Google Patents
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- CN109887947B CN109887947B CN201910266989.3A CN201910266989A CN109887947B CN 109887947 B CN109887947 B CN 109887947B CN 201910266989 A CN201910266989 A CN 201910266989A CN 109887947 B CN109887947 B CN 109887947B
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Abstract
The invention provides an image sensor with compact design layout, which comprises a pixel array arranged in a row and column layout on a semiconductor substrate, wherein the pixel units of two adjacent columns in the same row of the pixel array are arranged in mirror symmetry along a column direction central line. The photodiodes in each pixel unit are distributed along one direction, and the transmission transistors are obliquely arranged at corners of the photodiodes at an angle; the reset transistor is arranged at the side of the photodiode; the source follower transistor is disposed on an edge side of the photodiode adjacent to the reset transistor and is disposed near the floating diffusion point. The drains of two reset transistors adjacently arranged in the pixel units of two adjacent columns of the same row and two source follower transistors adjacently arranged in the next adjacent row of the pixel array are connected to the same fixed power supply. The compact design layout structure provided by the invention can further improve the performance of the image sensor.
Description
Technical Field
The invention relates to the technical field of image sensors, in particular to an image sensor which is compact in layout design structure and effectively improves the performance of a pixel circuit.
Background
The image sensor is widely applied to various fields, such as smart phones, monitoring equipment, unmanned aerial vehicles, artificial intelligence and the like, and the application requirements thereof are gradually miniaturized. With the development of technology, the size of pixel units of an image sensor is further reduced, and the increasing of conversion gain of pixel circuits and the increasing of sensitivity of the image sensor are the directions of development and improvement thereof. In the design of the image sensor, the reasonable layout design structure is adopted to effectively improve the performance of the image sensor. For example, the layout structure is compact, the arrangement structure of each device in the pixel unit is reasonable, the influence on the photosensitive area in the pixel unit is reduced, and the quantum efficiency of the photosensitive unit can be effectively improved.
In the layout design of the image sensor, when the source follower transistor is far away from the floating diffusion point, the floating diffusion point generates larger parasitic capacitance. When the parasitic capacitance of the floating diffusion point in the pixel circuit is large, the conversion gain of the pixel circuit is limited, and the sensitivity of the pixel circuit is reduced, so that the performance of the image sensor is affected. Reasonable layout design is carried out on the image sensor so as to improve parasitic capacitance of the floating diffusion point, and meanwhile, the layout structure and pixel unit wiring of the image sensor are improved, so that the performance of a pixel circuit of the image sensor is further improved, and the technical problem and the direction which are solved by the patent are solved.
Disclosure of Invention
An object of the present invention is to provide an image sensor having a compact design layout, the image sensor including a pixel array composed of a plurality of pixel cells laid out in rows and columns on a semiconductor substrate, each of the pixel cells including:
a photodiode and a transfer transistor connected to the photodiode, wherein the photodiode is arranged in a layout along one direction in a design layout of the image sensor, and the transfer transistor is obliquely arranged at a corner position of the photodiode at a certain angle;
a floating diffusion point connected to and disposed proximate to the pass transistor;
a reset transistor disposed at an edge side of the photodiode and connected to the floating diffusion point; and
A source follower transistor disposed on a side of the photodiode, adjacent to a side of the reset transistor, and disposed near the floating diffusion point;
the pixel units of two adjacent columns in the same row of the pixel array are arranged in mirror symmetry along the central line of the column direction; defining the row direction as the opposite arrangement direction of the transmission transistors of two adjacent pixel units or the back-to-back arrangement direction of the photodiodes; a direction perpendicular to the row direction is defined as a column direction;
optionally, the image sensor further includes a row selection transistor, where the row selection transistor and the source follower transistor are arranged in a same direction and are located on a same side of the photodiode;
optionally, the transmission transistor is obliquely arranged at a corner position of the photodiode at an angle of 45 degrees;
optionally, the reset transistor of each row of the pixel units in the pixel array is connected to the same fixed power supply as the drain of the source follower transistor of the pixel unit in the next adjacent row located in the same column;
optionally, drains of two source follower transistors disposed adjacent to each other of two adjacent columns of the pixel units in the same row in the pixel array are connected to the same fixed power supply;
optionally, the reset transistor is connected to the floating diffusion point by doped silicon;
optionally, the source follower transistor is connected to the row select transistor by doped silicon;
alternatively, the image sensor may be an FSI (Front Side Illumination, front-illuminated) image sensor or a BSI (Back Side Illumination, back-illuminated) image sensor.
The image sensor with compact design layout provided by the invention has the advantages that the pixel units of two adjacent columns in the same row of the pixel array are arranged in a mirror symmetry manner along the central line of the column direction on the basis of layout structure design, and the drains of two reset transistors arranged adjacently and two source follower transistors arranged adjacently in the next adjacent row are connected to the same fixed power supply so as to save the power supply wiring design. The reset transistor and the floating diffusion point in each pixel unit are connected by adopting doped silicon to replace metal wires, so that the influence on light of the photodiode Guan Rushe in the pixel unit can be further reduced. The source electrode following transistor is arranged close to the floating diffusion point layout, so that parasitic capacitance of the floating diffusion point is reduced, conversion gain of the pixel circuit is improved, and performance of the image sensor is further improved.
Drawings
FIG. 1 is a circuit diagram of an image sensor pixel in a basic 4T configuration;
FIG. 2 is a schematic diagram of a layout structure of two adjacent rows and two columns of pixel units according to the present invention; and
FIG. 3 is a schematic diagram of a pixel array layout of an image sensor with a compact design layout according to the present invention.
Detailed Description
The following describes the invention of the present patent in detail with reference to the accompanying drawings. Fig. 1 is an image sensor pixel circuit diagram of a basic 4T structure, and as shown in fig. 1, the image sensor pixel circuit includes a photodiode PD and a transfer transistor TX connected to the photodiode PD, which transfers electrons accumulated by the photodiode PD during exposure to a floating diffusion FD according to a control signal TX. The drains of the reset transistor RST and the source follower transistor SF are connected to the same fixed power supply VDD. The pixel circuit further includes a row selection transistor RS which controls the output of the pixel signal (pixout) amplified by the source follower transistor SF to the corresponding column line in accordance with the row selection control signal row_sel.
The image sensor with compact design layout proposed by the present patent comprises a plurality of pixel units arranged in rows and columns on a semiconductor substrate, each pixel unit comprises a pixel circuit as shown in fig. 1, the design layout of the pixel units of two adjacent columns in the same row of the pixel array is shown in fig. 2, the layout structure of two adjacent columns in the same row is included but not limited in fig. 2, and fig. 2 is only for illustrating the layout arrangement structure of the present invention. In fig. 2, a pixel unit is schematically indicated in a dashed line box.
As shown in fig. 2, each of the pixel units of the adjacent two columns in the same row includes photodiodes PD arranged in a horizontal direction (the present invention is not limited to the horizontal direction but may include other forms of directional layout), and the transfer transistor TX is disposed at an angle of the photodiodes PD at an inclination angle of 45 degrees. The inclination angle given in the embodiment of the present invention is 45 degrees, and other angle layouts may be used to set the corners of the photodiode PD. The reset transistor RST is laid out on the side of the photodiode PD to be connected to the floating diffusion FD with doped silicon. The doped silicon is used for replacing the metal wire to connect the reset transistor RST to the floating diffusion FD, so that the influence on the incident light of the photodiode PD can be effectively reduced. The source follower transistor SF is disposed on the side of the photodiode PD, as shown in fig. 2, vertically opposite to the reset transistor RST layout, and the source follower transistor SF is disposed close to the floating diffusion FD layout. The arrangement of the floating diffusion points FD is close to the arrangement of the floating diffusion points FD, so that parasitic capacitance of the floating diffusion points FD can be reduced, and conversion gain of the pixel unit circuit is improved, and performance of the pixel circuit is improved. In this embodiment, each pixel unit further includes a row selection transistor RS disposed adjacent to the source follower transistor SF and disposed on the same side of the source follower transistor SF. The source follower transistor SF may also be connected to the row select transistor RS by doped silicon instead of a metal line to reduce the influence of incident light to the photodiode PD.
In fig. 2, a schematic structure of two adjacent columns of pixel units in the pixel array is shown, and in this patent, since the pixel units in two adjacent columns in the same row are in mirror symmetry along the central line in the column direction, the specific arrangement structure of the two adjacent columns of pixel units further includes a structure (not shown in fig. 2, reference may be made to the related layout structure shown in the schematic diagram of the pixel array) in which two photodiodes PD of the pixel units in two adjacent columns in the same row are arranged adjacently (arranged adjacently back to back). The reset transistor RST in each pixel cell is connected to the same fixed power supply VDD as the drain of the source follower transistor SF in the next adjacent row of the same column. As shown in fig. 2, the drains of the four transistors, two reset transistors RST and two source follower transistors SF, of the adjacent two columns of pixel cells of the same row are connected to the same fixed power supply VDD. The connection mode can effectively reduce the design of power wiring in the circuit. In the embodiment of the present invention, the row direction is defined as the direction in which the transfer transistors in two adjacent pixel units are disposed opposite to each other, or the direction in which the photodiodes PD in two adjacent pixel units are disposed back to back, and the other direction perpendicular to the row direction is defined as the column direction.
Fig. 3 is a schematic layout structure of a pixel array of an image sensor having a compact design layout. As shown in fig. 3, the pixel units of two adjacent columns in the same row in the pixel array are arranged in mirror symmetry along the column direction center line. The layout structure of the pixel array shown in fig. 3 includes, in addition to the layout structure of the two adjacent columns of pixel units shown in fig. 2, a layout structure in which photodiodes PD in the two adjacent columns of pixel units are disposed back-to-back adjacent to each other. The photodiodes PD of two adjacent columns of pixel units in the same row are arranged back-to-back adjacently, and the two source follower transistors SF thereof are not adjacently arranged, and the drains of the two source follower transistors SF are not connected to the same fixed power supply VDD, but are respectively connected to the same fixed power supply VDD with the drains of the source follower transistors SF of the other adjacent columns thereof.
The invention provides an image sensor with compact design layout, which also comprises a reading-out and control circuit for reading and controlling pixel output of the image sensor. The image sensor can be designed as an FSI image sensor or a BSI image sensor, and the image sensors with two design forms are within the protection scope of the compact layout design structure provided by the patent of the invention.
The embodiments and drawings of the present invention are presented for illustrative purposes and various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Modifications may be made to the embodiments of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, a full scope of the claims should be construed as being established doctrines of claim interpretation. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (8)
1. An image sensor having a compact design layout, said image sensor comprising a pixel array of a plurality of pixel cells arranged in rows and columns on a semiconductor substrate, wherein each of said pixel cells comprises:
a photodiode and a transfer transistor connected to the photodiode, the photodiode being arranged in a direction layout, the transfer transistor being disposed at an angle to a corner of the photodiode;
a floating diffusion point connected to and disposed proximate to the pass transistor;
a reset transistor disposed on an edge side of the photodiode; and
A source follower transistor disposed on an edge side of the photodiode adjacent to the reset transistor and close to the floating diffusion point;
the pixel units of two adjacent columns in the same row of the pixel array are arranged in a mirror symmetry mode along a central line in the column direction, and drains of two reset transistors arranged adjacent to each other and two source follower transistors arranged adjacent to each other in the next adjacent row are connected to the same fixed power supply.
2. The image sensor with a compact design layout of claim 1, comprising a row of select transistors disposed adjacent to the layout in the same direction as the source follower transistors.
3. The image sensor with a compact design layout of claim 1 wherein the pass transistor is disposed at a 45 degree angle to the corner of the photodiode.
4. The image sensor with a compact design layout of claim 2 wherein the reset transistor of the pixel cell in each row of the pixel array is connected to the same fixed power supply as the drain of the source follower transistor of the pixel cell in the next adjacent row of the same column.
5. An image sensor having a compact design layout as in claim 2 or 4, wherein the drains of two of said source follower transistors disposed adjacent to each other in two adjacent columns of said pixel cells are connected to the same fixed power supply.
6. The image sensor with a compact design layout of claim 1 wherein the reset transistor is connected to the floating diffusion point by doped silicon.
7. The image sensor with a compact design layout of claim 2 wherein the source follower transistor is connected to the row select transistor by doped silicon.
8. The image sensor with a compact design layout of claim 1, wherein the image sensor is an FSI image sensor or a BSI image sensor.
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