CN110061026B - Image sensor with shared structure pixel layout - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H01L27/144—Devices controlled by radiation
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- H01L27/14601—Structural or functional details thereof
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/14643—Photodiode arrays; MOS imagers
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
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Abstract
The invention provides an image sensor with a shared structural pixel layout, which comprises a pixel array formed by a plurality of shared pixel units arranged in rows and columns. The shared pixel unit comprises a first photosensitive pixel unit and a second photosensitive pixel unit, and the first photosensitive pixel unit and the second photosensitive pixel unit share a reset transistor, a floating diffusion point, a source follower transistor and a row selection transistor. The floating diffusion point is arranged at an opening formed by the first photosensitive pixel unit and the second photosensitive pixel unit structure, and the source electrode following transistor is close to and faces the opening. Meanwhile, the image sensor provided by the invention is provided with the isolation structure so as to reduce dark current of the pixel circuit. The image sensor provided by the invention has compact structural layout, and the source electrode following transistor is close to the floating diffusion point, so that the capacitance of the floating diffusion point can be effectively reduced, and the conversion gain of a pixel circuit is improved.
Description
Technical Field
The present invention relates to image sensor technology, and more particularly, to an image sensor with a pixel sharing structure and a compact layout arrangement to reduce floating diffusion point capacitance and improve conversion gain of pixel circuits.
Background
The image sensor is widely applied to various fields, such as smart phones, monitoring equipment, unmanned aerial vehicles, artificial intelligence and the like, and the application requirements thereof are gradually miniaturized. A typical image sensor employs a 4-transistor design, a photodiode plus a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. The pixel unit adopts a shared structure, which can be used for reducing the pixel size and improving the filling factor (fill factor). The filling factor corresponds to the ratio of the area occupied by the photosensitive unit to the area of the pixel unit, and the sensitivity and the signal-to-noise ratio of the pixel circuit can be improved by improving the filling factor.
In the layout design of the image sensor, for example, the layout design disclosed in the patent No. ZL200610006729.6 entitled "sensor array" document adopts a layout of 2 pixels sharing or 4 pixels sharing, and the layout of fig. 3, fig. 4, fig. 6 and fig. 7 in the above-mentioned patent are shown in the circuit of fig. 3, fig. 4, fig. 6, the source follower transistor SF is disposed at a relatively long distance from the floating diffusion FD, and the capacitance generated by the floating diffusion FD is relatively large in this arrangement, and the circuit conversion gain is relatively low, so that the sensitivity of the pixel circuit is reduced. Next, the row selection transistor SEL and the source follower transistor are disposed between two shared pixel units, and this arrangement reduces the quantum efficiency of the photosensitive pixel for blocking incident light of the partial photodiodes PD1 and PD 2.
Based on the problems, the invention provides a new compact design scheme with reasonable layout based on a shared pixel unit structure to meet the design and application of an image sensor with the shared pixel structure in order to further improve the design layout of the pixel circuit and effectively reduce the capacitance of the floating diffusion point FD, improve the conversion gain of the pixel circuit and improve the quantum efficiency of the photosensitive pixel.
Disclosure of Invention
The invention proposes an image sensor with a shared structural pixel layout, comprising a pixel array composed of a plurality of shared pixel units tiled by rows and columns, each of the shared pixel units comprising:
A first photosensitive pixel unit including a photodiode and a transfer transistor connected to the photodiode, the photodiode being disposed along a direction, the transfer transistor being disposed at an oblique angle along a corner of the photodiode;
The second photosensitive pixel unit is identical to the first photosensitive pixel unit and is arranged in mirror symmetry with the first photosensitive pixel unit along the horizontal direction;
The first photosensitive pixel unit and the second photosensitive pixel unit share a reset transistor, a floating diffusion point and a source electrode following transistor;
the arrangement structures of the two transmission transistors of the first photosensitive pixel unit and the second photosensitive pixel unit form an opening, and the floating diffusion point is arranged at the opening; the source follower transistor is disposed facing and adjacent to the opening; the reset transistor is arranged between the first photosensitive unit and the second photosensitive unit;
The nearest distance between the edge of the gate of the source follower transistor, i.e. the edge of the gate opposite the floating diffusion point, and the edge of the floating diffusion point is less than 0.25 microns; preferably, the distance is less than 0.15 microns;
Optionally, the first photosensitive pixel unit and the second photosensitive pixel unit further include a shared row selection transistor, and the row selection transistor is disposed at a corner of the shared pixel unit;
optionally, the row selection transistor is disposed at the corner of the source follower transistor near end to reduce its effect on the incident light of the photodiode;
optionally, the pass transistor is disposed at an oblique angle of about 45 degrees along a corner of the photodiode;
Optionally, the first photosensitive pixel unit and the second photosensitive pixel unit are mirror symmetrical along the horizontal center lines of the reset transistor, the floating diffusion point and the source follower transistor;
optionally, the openings formed by the arrangement structures of the two transfer transistors of the first photosensitive pixel unit and the second photosensitive pixel unit are about 90 degrees;
Optionally, each of the shared pixel units includes a conversion gain control transistor disposed between the first photosensitive pixel unit and the second photosensitive pixel unit and near the floating diffusion point; in this layout design structure, the reset transistor in each of the shared pixel units may be further disposed at an edge position along a layout arrangement direction of the source follower transistor;
Optionally, a doped silicon connection mode is used to replace a metal connection mode to connect the source follower transistor and the row select transistor, so as to reduce the influence of the metal connection on the incident light of the photodiode; the reset transistor is connected to the floating diffusion point by using doped silicon to replace a metal wire so as to improve the opening ratio of the opening;
Optionally, high-potential silicon (silicon with positive voltage) is adopted to perform isolation arrangement around each shared pixel unit, so that symmetry of the shared pixel units is improved, and electrical signal crosstalk is prevented;
optionally, an isolation structure is arranged between the shared pixel units, and is ion implantation isolation or STI isolation;
Optionally, isolation structures are arranged between the photodiodes and between the transistors of each of the shared pixel units, and are ion implantation type isolation or STI isolation (shallow trench isolation );
Optionally, STI isolation is arranged between the source follower transistor and the floating diffusion point of the image sensor, and ion implantation isolation is arranged between the photodiodes and between other multiple transistors;
Optionally, the image sensor is an FSI (front side illumination, front-illuminated) image sensor or a BSI (back side illumination, back-illuminated) image sensor.
According to the image sensor with the shared structure pixel layout, each shared pixel unit tiled in the pixel array is arranged in a compact layout, the floating diffusion point is arranged at the opening of the two photosensitive pixel arrangement structures, the source following transistors are arranged on the surface and the minimum distance is close to the opening, the source following transistors are close to the floating diffusion point, the capacitance of the floating diffusion point is small, and the conversion gain can be effectively improved. Meanwhile, the row selection transistor is arranged at the corner part of the shared pixel unit, has small influence on the shielding of the incident light of the photodiode, and can effectively improve the quantum efficiency of the pixel unit; the connection between the source follower transistor and the row select transistor, and between the reset transistor and the floating diffusion point uses doped silicon instead of metal lines, further reducing the effect on the photodiode Guan Rushe light.
Drawings
FIG. 1 is a circuit diagram of a first embodiment of an image sensor according to the present invention;
FIG. 2 is a schematic layout diagram of a shared pixel unit corresponding to the pixel circuit of the first embodiment in FIG. 1;
FIG. 3 is a circuit diagram of a second embodiment of an image sensor according to the present invention;
FIG. 4 is a schematic layout diagram of a shared pixel unit corresponding to the pixel circuit of the second embodiment in FIG. 3;
FIGS. 5-6 are schematic diagrams illustrating the isolation structure of an image sensor according to the present invention;
Fig. 7 is a schematic diagram of a pixel array layout structure of a second embodiment of an image sensor according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples. The drawings and examples are presented below to illustrate the present invention and their corresponding descriptions are not intended to limit the invention.
Fig. 1 is a circuit diagram of an image sensor with a shared structure pixel layout according to a first embodiment of the present invention, wherein a photodiode PD1 and a transfer transistor TX1 form a first photosensitive pixel unit, and a photodiode PD2 and a transfer transistor TX2 form a second photosensitive pixel unit, as shown in fig. 1. The first photosensitive pixel unit and the second photosensitive pixel unit constitute a sharing structure that shares the floating diffusion FD, the reset transistor RST, and the source follower transistor SF. The reset transistor is connected to a variable voltage source Vref, the drain of the source follower transistor is connected to a fixed power supply VDD, and a pixel signal is output to a column line (Pout) through the source of the source follower transistor SF. The circuit diagram shown in fig. 1 is a pixel unit circuit of one embodiment of an image sensor according to the present invention. The following proposes a shared pixel cell design layout with a compact arrangement structure for the pixel circuit of the image sensor shown in fig. 1, and further improved pixel cell performance.
Fig. 2 is a schematic layout structure of one of the shared pixel units according to the first embodiment of the image sensor. The schematic diagram of fig. 2 is for the purpose of illustrating the device arrangement and is not intended to limit the specific shape, size or angle of each device. In a particular circuit design, it may be designed in different shapes depending on the particular application. In connection with each device unit of the pixel circuit in fig. 1, the transfer transistor TX1 is disposed at a corner of the photodiode PD1 and is disposed at an inclined angle, which may be an angle of 45 degrees in general. The transfer transistor TX2 and the photodiode PD2 are arranged in the same structural manner. The first photosensitive pixel unit constituted by PD1 and TX1 and the second photosensitive pixel unit constituted by PD1 and TX2 are mirror-symmetrically arranged in the horizontal direction as shown in fig. 2. The reset transistor RST is disposed between the first and second photosensitive pixel units. The arrangement of the transfer transistors TX1 and TX2 forms an opening where the floating diffusion FD is located closest to the opening. In one application example, the edge of the gate of the source follower transistor SF corresponding to the floating diffusion is spaced no more than 0.25 μm from the edge closest to the floating diffusion. As a preferred embodiment, this spacing is no greater than 0.15 microns. The above-mentioned spacing may be set in the range of 0.08 to 0.15 microns, preferably at 0.12 microns, for different process technology platforms, such as 0.13 μm process technology, in these application embodiments. For a 0.11 μm process technology platform, the above-mentioned spacing may be set in the range of 0.05 to 0.12 microns, preferably 0.10 microns. The pitch may be designed to be 0.08 microns depending on the particular application, depending on the advanced process technology platform. The source following transistor SF is arranged in a face phase opening and is close to the floating diffusion point FD, and the floating diffusion point FD generates small capacitance in the arrangement mode, so that the conversion gain of the pixel circuit can be improved. The first photosensitive pixel unit and the second photosensitive pixel unit are in mirror symmetry along the reset transistor RST, the floating diffusion point FD and the source follower transistor SF, and the pixel circuit has good symmetry, so that noise of the pixel circuit can be effectively reduced.
In each shared pixel unit of the pixel array, the connection from the reset transistor RST to the floating diffusion point can be realized by adopting doped silicon to replace metal wires, and in the specific layout design, the wiring is relatively simple, the opening ratio of the opening part is relatively large, and the luminous flux entering the photodiode can be improved. High-potential silicon can be adopted around each shared pixel unit for isolation setting, good symmetry among the shared pixel units is guaranteed, and meanwhile, the electric crosstalk among the pixel sharing units can be prevented, and the performance of the image sensor is further improved.
Fig. 3 is a diagram showing an image sensor pixel circuit according to a second embodiment of the present invention, and unlike the pixel circuit of fig. 1, two shared photosensitive pixel units in this embodiment further include a row selection transistor RS in addition to the reset transistor RST, the floating diffusion FD, and the source follower transistor SF. In the pixel circuit of the present embodiment, the reset transistor RST and the source follower transistor SF are connected to the fixed power supply VDD. The pixel signal is output to the column line through the row select transistor RS. Fig. 3 is a layout design corresponding to the pixel circuit shown in fig. 4, and fig. 4 is a schematic layout structure of a shared pixel unit in the second embodiment of the present invention. The schematic diagram is for the purpose of illustrating the device arrangement and is not intended to limit the specific shape, size or angle of each device. In a particular circuit design, it may be designed in different shapes depending on the particular application.
The layout structure of the shared pixel unit provided in the second embodiment of the present invention is different from the layout structure in the first embodiment in that the layout arrangement further includes a row selection transistor RS, and the row selection transistor RS is disposed at a corner position of the shared pixel unit. As shown in fig. 4, the corner near the proximal end of the source follower transistor SF. The arrangement mode row selection transistor RS has little influence on light incident to the photodiode PD1 or PD2 to improve the quantum efficiency of the shared pixel unit. Since the distance setting of the source follower transistor SF and the row select transistor RS is slightly distant from the setting position of other devices, doped silicon may be used instead of a metal line to connect the source follower transistor SF and the row select transistor RS. This connection reduces the shielding effect of the metal wire connection on the light incident on the photodiode PD1, and avoids the low quantum efficiency of the photosensitive cell. Similarly, in this embodiment, high-potential silicon may be used to isolate the periphery of each shared pixel unit, so that good symmetry of the shared pixel units can be ensured, and meanwhile, influence caused by crosstalk of electrical signals can be prevented.
The present invention also provides a third embodiment and a fourth embodiment. The third embodiment is the pixel circuit of the first embodiment, including one conversion gain control transistor DCG connected between the reset transistor RST and the floating diffusion FD. The pixel circuit of the fourth embodiment, which is the second embodiment, further includes a conversion gain control transistor DCG connected between the reset transistor RST and the floating diffusion FD. The pixel circuits in the above-described third and fourth embodiments realize conversion of the high and low gains of the pixel circuits by controlling the conversion gain control transistor DCG and the capacitance to improve the dynamic range of the output image. The above two embodiments are arranged in a structural layout, the conversion gain control transistor DCG is arranged between the first and second photosensitive pixel units, and the reset transistor may also be arranged on the side of the shared pixel unit along the source follower transistor SF direction. This embodiment does not give illustrations, but does not affect the protection of the image sensor layout design structure given in the third and fourth embodiments.
In the above embodiments, the image sensor has isolation structures between the photodiodes and between the transistors of each shared pixel unit, so as to prevent signal crosstalk and leakage current between devices in the pixel circuit. In a specific embodiment of the present invention, an ion implantation isolation manner may be used between a plurality of photodiodes, between a plurality of transistors in a pixel circuit, and between each pixel unit, so as to reduce dark current in the pixel circuit. The pixel units all adopt an ion implantation isolation mode, so that dark current in a pixel circuit can be effectively reduced. In some embodiments, the photodiodes are isolated by ion implantation, and STI isolation structures are disposed between the transistors in the pixel circuit. The high dark current generated by defects due to lattice dislocation caused by damage during the etching process to form the trench structure is liable to occur due to STI isolation, so that undesirable fixed noise occurs, and the excessive dark current in the pixel circuit may reduce the dynamic range of the image sensor. Therefore, in an application example, STI isolation is arranged between the source follower transistor and the floating diffusion point, and ion implantation isolation structures are adopted between other parts of the shared pixel units and between the shared pixel units, so as to reduce dark current in the pixel circuit, improve circuit conversion gain, and improve performance of the image sensor. Fig. 5 and 6 are schematic diagrams of the ion implantation isolation and a portion of the STI isolation, and the blank between the source follower transistor and the floating diffusion point in fig. 6 is schematic diagram of the STI isolation. The above-described drawings are for illustrative purposes only and are not intended to limit the positional relationship and schematic form of the isolation structures employed.
Fig. 7 is a schematic diagram of a pixel array formed by tiling the shared pixel cells shown in fig. 4 in rows and columns. The image sensor with the shared structure pixel layout provided by the invention comprises, but is not limited to, a pixel array shown in fig. 7, wherein the pixel signals output by the pixel array are read, controlled, processed and output by a control circuit. The image sensor with the shared pixel unit pixel array provided by the invention can be an FSI image sensor or a BSI image sensor, and the image sensor is within the practical range of the invention.
The embodiments and drawings of the present invention are presented for illustrative purposes and various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Modifications may be made to the embodiments of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, a full scope of the claims should be construed as being established doctrines of claim interpretation. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (9)
1. An image sensor having a shared architecture pixel layout, comprising a pixel array of a plurality of shared cells arranged in a row and column layout, wherein each of said shared cell pixel arrays comprises:
A first photosensitive pixel unit including a photodiode and a transfer transistor connected to the photodiode, the photodiode being disposed along a direction, the transfer transistor being disposed at an oblique angle along a corner of the photodiode;
The second photosensitive pixel unit is identical to the first photosensitive pixel unit and is arranged in mirror symmetry with the first photosensitive pixel unit along the horizontal direction;
The transmission transistor arrangement structures of the first photosensitive pixel unit and the second photosensitive pixel unit form an opening facing one side of a source following transistor, and a floating diffusion point is arranged at the opening; a source follower transistor disposed facing and adjacent to the opening, a proximal distance between a gate edge of the source follower transistor and an edge of the floating diffusion point being less than 0.25 microns;
An isolation structure is arranged between pixel arrays formed by the sharing units, and is ion implantation isolation or STI isolation;
the first photosensitive pixel unit and the second photosensitive pixel unit share a reset transistor, a floating diffusion point, a source electrode following transistor and a row selection transistor, and the row selection transistor is arranged at the corner of the pixel array formed by the sharing units.
2. The image sensor with shared structural pixel layout of claim 1, wherein the pass transistor is disposed at a 45 degree oblique angle along a corner of the photodiode.
3. The image sensor with shared structural pixel layout of claim 1, wherein the reset transistor is disposed between the first and second photosensitive pixel cells, the first and second photosensitive pixel cells being mirror symmetric along horizontal centerlines of the reset transistor, the floating diffusion point, and the source follower transistor.
4. The image sensor of claim 1, wherein each of the pixel arrays of shared architecture pixel arrangements includes a conversion gain control transistor, the arrangement being disposed between the first and second photosensitive pixel cells and adjacent to the floating diffusion point.
5. The image sensor with shared structure pixel layout of claim 1 wherein the source follower transistor is connected to the row select transistor by doped silicon.
6. The image sensor with shared structure pixel layout of claim 1 wherein the reset transistor is connected to the floating diffusion point by doped silicon.
7. The image sensor with shared structure pixel layout according to claim 1, wherein isolation structures are provided between the photodiodes and between the transistors of the pixel array formed by each of the shared cells, for ion implantation type isolation or STI isolation.
8. The image sensor with shared structure pixel layout of claim 1 wherein STI isolation is provided between the source follower transistor and the floating diffusion point of the image sensor, and ion implantation isolation is provided between the photodiodes and between other multiple transistors.
9. The image sensor with shared structural pixel layout of claim 1, wherein the image sensor is an FSI image sensor or a BSI image sensor.
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| CN110896082A (en) * | 2019-05-28 | 2020-03-20 | 思特威(上海)电子科技有限公司 | Image sensor with novel layout |
| CN110336953B (en) * | 2019-07-02 | 2021-04-16 | 思特威(上海)电子科技股份有限公司 | Image sensor with four-pixel structure and reading control method |
| CN110891137A (en) * | 2019-11-15 | 2020-03-17 | Oppo广东移动通信有限公司 | Image sensor, electronic device, image processing method, and storage medium |
| KR20220043449A (en) | 2020-09-29 | 2022-04-05 | 에스케이하이닉스 주식회사 | Image sensing device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1017106A2 (en) * | 1998-12-31 | 2000-07-05 | Eastman Kodak Company | Active pixel sensor with wired floating diffusions and shared amplifier |
| JP2009302349A (en) * | 2008-06-13 | 2009-12-24 | Sharp Corp | Amplification type solid-state imaging element, and electronic information apparatus |
| CN103607547A (en) * | 2013-12-09 | 2014-02-26 | 江苏思特威电子科技有限公司 | Pixel imaging device for mirror image and imaging method for mirror image |
| CN104752448A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Backside illuminated CMOS (Complementary Metal Oxide Semiconductors) image sensor and forming method thereof |
| CN206742242U (en) * | 2016-05-13 | 2017-12-12 | 半导体元件工业有限责任公司 | Imaging sensor and imaging pixel |
| JP2018098772A (en) * | 2016-12-13 | 2018-06-21 | ソニーセミコンダクタソリューションズ株式会社 | Image pickup device and electronic device |
| CN108242449A (en) * | 2016-12-27 | 2018-07-03 | 三星电子株式会社 | Imaging sensor and the electronic device for including it |
| CN108476298A (en) * | 2017-02-25 | 2018-08-31 | 华为技术有限公司 | Lazer's pixel cmos image sensor |
| CN108810430A (en) * | 2017-06-15 | 2018-11-13 | 思特威电子科技（美国）有限公司 | A kind of imaging system and forming method thereof |
| CN209880621U (en) * | 2019-01-25 | 2019-12-31 | 思特威(上海)电子科技有限公司 | Image sensor with shared structure pixel layout |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060255380A1 (en) * | 2005-05-10 | 2006-11-16 | Nan-Yi Lee | CMOS image sensor |
| JP4595464B2 (en) * | 2004-09-22 | 2010-12-08 | ソニー株式会社 | Manufacturing method of CMOS solid-state imaging device |
| KR100674923B1 (en) * | 2004-12-03 | 2007-01-26 | 삼성전자주식회사 | CMOS image sensor sharing readout circuits between adjacent pixels |
| US8405751B2 (en) * | 2009-08-03 | 2013-03-26 | International Business Machines Corporation | Image sensor pixel structure employing a shared floating diffusion |
| US9190434B2 (en) * | 2011-09-30 | 2015-11-17 | Omnivision Technologies, Inc. | CMOS image sensor with reset shield line |
-
2019
- 2019-01-25 CN CN201910072333.8A patent/CN109659329A/en active Pending
- 2019-05-28 CN CN201910454041.0A patent/CN110061026B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1017106A2 (en) * | 1998-12-31 | 2000-07-05 | Eastman Kodak Company | Active pixel sensor with wired floating diffusions and shared amplifier |
| JP2009302349A (en) * | 2008-06-13 | 2009-12-24 | Sharp Corp | Amplification type solid-state imaging element, and electronic information apparatus |
| CN103607547A (en) * | 2013-12-09 | 2014-02-26 | 江苏思特威电子科技有限公司 | Pixel imaging device for mirror image and imaging method for mirror image |
| CN104752448A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Backside illuminated CMOS (Complementary Metal Oxide Semiconductors) image sensor and forming method thereof |
| CN206742242U (en) * | 2016-05-13 | 2017-12-12 | 半导体元件工业有限责任公司 | Imaging sensor and imaging pixel |
| JP2018098772A (en) * | 2016-12-13 | 2018-06-21 | ソニーセミコンダクタソリューションズ株式会社 | Image pickup device and electronic device |
| CN108242449A (en) * | 2016-12-27 | 2018-07-03 | 三星电子株式会社 | Imaging sensor and the electronic device for including it |
| CN108476298A (en) * | 2017-02-25 | 2018-08-31 | 华为技术有限公司 | Lazer's pixel cmos image sensor |
| CN108810430A (en) * | 2017-06-15 | 2018-11-13 | 思特威电子科技（美国）有限公司 | A kind of imaging system and forming method thereof |
| CN209880621U (en) * | 2019-01-25 | 2019-12-31 | 思特威(上海)电子科技有限公司 | Image sensor with shared structure pixel layout |
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