CN117957659A - Solid-state imaging device and electronic apparatus - Google Patents
Solid-state imaging device and electronic apparatus Download PDFInfo
- Publication number
- CN117957659A CN117957659A CN202180102386.5A CN202180102386A CN117957659A CN 117957659 A CN117957659 A CN 117957659A CN 202180102386 A CN202180102386 A CN 202180102386A CN 117957659 A CN117957659 A CN 117957659A
- Authority
- CN
- China
- Prior art keywords
- region
- solid
- state imaging
- imaging device
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 144
- 238000006243 chemical reaction Methods 0.000 claims abstract description 150
- 238000012546 transfer Methods 0.000 claims abstract description 148
- 239000004065 semiconductor Substances 0.000 claims abstract description 146
- 238000009792 diffusion process Methods 0.000 claims abstract description 91
- 238000000926 separation method Methods 0.000 claims description 68
- 238000002955 isolation Methods 0.000 claims description 46
- 239000010410 layer Substances 0.000 description 186
- 239000000758 substrate Substances 0.000 description 28
- 238000012545 processing Methods 0.000 description 20
- 238000000034 method Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 230000009977 dual effect Effects 0.000 description 12
- 238000003860 storage Methods 0.000 description 11
- 238000009825 accumulation Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 230000000875 corresponding effect Effects 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000005670 electromagnetic radiation Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 101001018097 Homo sapiens L-selectin Proteins 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 102100033467 L-selectin Human genes 0.000 description 2
- 101150054516 PRD1 gene Proteins 0.000 description 2
- 101100459905 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NCP1 gene Proteins 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000005421 electrostatic potential Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000004313 glare Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 101100238374 Arabidopsis thaliana MPS1 gene Proteins 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14621—Colour filter arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
- H01L27/14627—Microlenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14645—Colour imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Provided is a solid-state imaging device (100) including: a semiconductor layer (160) of a first conductivity type semiconductor; a photoelectric conversion portion (170), wherein the photoelectric conversion portion includes a first side (171) and a second side (172) opposite to the first side (171), and is in contact with the semiconductor layer (160) at the first side (171); a charge transfer gate device that is electrically connected to the photoelectric conversion portion (170) and transfers charge stored in the photoelectric conversion portion (170) to a floating diffusion region (300), wherein the photoelectric conversion portion (170) includes at least a first sub-region (181) of the first conductivity type semiconductor and a second sub-region (182) of a second conductivity type semiconductor different from the first conductivity type semiconductor, the first sub-region (181) and the second sub-region (182) are in contact with the semiconductor layer (160) at the first side (171) of the photoelectric conversion portion (170), and a thickness of the first sub-region (181) in a normal direction perpendicular to the first side (171) is smaller than a thickness of the second sub-region (182) in a normal direction perpendicular to the first side (171), the charge transfer gate device including a first charge transfer gate device (450) and a second charge transfer gate device (550).
Description
Technical Field
The present invention relates to a solid-state imaging device and an electronic apparatus.
Background
As solid-state imaging devices (image sensors) that detect electromagnetic radiation and generate electric charges using photoelectric conversion elements, charge coupled device (charge coupled device, CCD) image sensors and complementary metal oxide semiconductor (complementary metal oxide, CMOS) image sensors have been put into practical use. CCD image sensors and CMOS image sensors are widely used as components of digital cameras, video cameras, monitoring cameras, medical endoscopes, personal computers (personal computer, PCs), mobile phones and other portable terminals (mobile devices), and other various types of electronic apparatuses.
The CCD image sensor and the CMOS image sensor use photodiodes as photoelectric conversion elements, but transmit photoelectrically converted signal charges by different methods. In the CCD image sensor, signal charges are transferred to an output section through a vertical transfer section (vertical CCD, VCCD) and a horizontal transfer section (horizontal CCD, HCCD), and then converted into an electric signal and amplified. In contrast, in the CMOS image sensor, the electric charge converted for each pixel including the photodiode is amplified and output as a readout signal.
When the pixel size is small, the full well capacity becomes small due to the limited area. Due to glare problems, lower full well capacity can result in low dynamic range and low signal-to-noise ratio SNR.
Patent document 1 discloses a solid-state imaging device including: a substrate having a first substrate side and a second substrate side on a side opposite the first substrate side; a photoelectric conversion portion including a first conductivity type semiconductor layer which is buried in the substrate and has a photoelectric conversion function of receiving light and a charge accumulation function; a second-conductivity-type separation layer formed in a side portion of the first-conductivity-type semiconductor layer in the photoelectric conversion portion; a charge transfer gate portion capable of transferring charges accumulated in the photoelectric conversion portion, wherein the photoelectric conversion portion includes at least one second conductivity type semiconductor layer in at least a portion of the first conductivity type semiconductor layer, the second conductivity type semiconductor layer forming at least one sub-region in a normal direction perpendicular to the substrate, and having a junction capacitance component together with the first conductivity type semiconductor layer, the one charge transfer gate portion capable of transferring charges accumulated in the sub-region in the photoelectric conversion portion.
[ Prior Art literature ]
[ Patent literature ]
[ Patent document 1 ] Japanese patent laid-open No. 2018-139269A
[ Problem to be solved by the invention ]
However, patent document 1 holds an n-type layer between the second substrate side and the second conductive type semiconductor layer, and the second substrate side and the second conductive type semiconductor layer are p-type layers, and therefore, in a Photodiode (PD), there is a limit in disposing the second conductive type semiconductor layer in the vicinity of the charge transfer gate device side, resulting in low improvement of Full WELL CAPACITY (FWC).
Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device and an electronic apparatus capable of further improving a Full WELL CAPACITY (FWC) capacity.
[ Solution to the problem ]
The present invention has been completed based on the above-described findings, and the gist thereof is as follows.
A solid-state imaging device, the solid-state imaging device comprising:
A semiconductor layer of a first conductivity type semiconductor;
A photoelectric conversion portion including a first side and a second side opposite to the first side, and being in contact with the semiconductor layer at the first side;
a charge transfer gate device electrically connected to the photoelectric conversion portion and transferring charges stored in the photoelectric conversion portion to a floating diffusion region,
Wherein the photoelectric conversion portion includes at least a first sub-region of the first conductivity type semiconductor and a second sub-region of a second conductivity type semiconductor different from the first conductivity type semiconductor,
On the first side of the photoelectric conversion portion, the first sub-region and the second sub-region are in contact with the semiconductor layer,
The thickness of the first sub-region in a direction perpendicular to the normal of the first side is smaller than the thickness of the second sub-region in a direction perpendicular to the normal of the first side,
The charge transfer gate device includes a first charge transfer gate device and a second charge transfer gate device.
The solid-state imaging device according to [1], characterized in that,
At least one cross-sectional area of the first sub-area parallel to the first side is larger than another cross-sectional area of the first sub-area parallel to the first side.
The solid-state imaging device according to [ 1 ] or [ 2 ], characterized in that,
The first sub-region includes an intermediate p-well portion,
A cross-sectional area of the intermediate P-well portion parallel to the first side is greater than an area of the first sub-region on the first side.
The solid-state imaging device according to [3], characterized in that,
The thickness of the intermediate p-well portion in a normal direction perpendicular to the first side is greater than 0 μm and less than or equal to 3.0 μm.
The solid-state imaging device according to any one of [1] to [ 4 ], characterized in that the solid-state imaging device further comprises:
a separation layer formed in the portion of the photoelectric conversion portion,
Wherein the separation layer is a separation layer of a first conductivity type semiconductor.
The solid-state imaging device according to [5], characterized in that,
At least one cross-sectional area of the separation layer parallel to the first side is greater than another cross-sectional area of the separation layer parallel to the first side.
The solid-state imaging device according to [ 5] or [ 6 ], characterized in that,
The separation layer is in contact with the semiconductor layer and includes a deep p-well portion,
A cross-sectional area of the deep P-well portion parallel to the first side is larger than an area of a portion of the separation layer in contact with the semiconductor layer.
The solid-state imaging device according to any one of [ 5 ] to [ 7 ], characterized in that,
At least one region of the separation layer has a doping concentration different from other regions of the separation layer.
The solid-state imaging device according to any one of [ 5 ] to [ 8 ], characterized in that the solid-state imaging device further comprises:
And a deep trench isolation portion buried in the separation layer from a side of the second side of the photoelectric conversion portion.
The solid-state imaging device according to [ 9 ], characterized in that,
The deep trench isolation portion is buried within the semiconductor layer.
The solid-state imaging device according to [ 9 ] or [ 10 ], characterized in that,
The deep trench isolation portion is buried within the second sub-region.
The solid-state imaging device according to any one of [ 9 ] to [ 11 ], characterized in that,
The deep trench isolation portion is a junction isolation or an STI isolation.
The solid-state imaging device according to any one of [ 1 ] to [ 12 ], characterized in that,
The first charge transfer gate device and the second charge transfer gate device are electrically connected on opposite sides of the semiconductor layer from the photoelectric conversion portion.
The solid-state imaging device according to any one of [ 1 ] to [ 13 ], characterized in that,
At least one region of the first subregion is doped at a different concentration than other regions of the first subregion.
The solid-state imaging device according to any one of [ 1 ] to [ 14 ], characterized in that,
At least one region of the second subregion is doped at a different concentration than other regions of the second subregion.
The solid-state imaging device according to any one of [ 1 ] to [ 15 ], characterized in that,
The first charge transfer gate and the second charge transfer gate have embedded portions in the semiconductor layer.
The solid-state imaging device according to any one of [ 1 ] to [ 16 ], characterized in that the solid-state imaging device further comprises:
A second separation layer that is in contact with the second side of the photoelectric conversion portion, and that is a separation layer of the first conductivity type semiconductor.
The solid-state imaging device according to any one of [ 1 ] to [ 17 ], characterized in that,
At least one cross-sectional area of the second sub-area parallel to the first side is simply connected.
The solid-state imaging device according to any one of [ 1 ] to [ 18 ], characterized in that the solid-state imaging device further comprises:
a circuit, the circuit comprising:
A floating diffusion electrically connected to the first and second charge transfer gate devices, a double conversion device electrically connected to the floating diffusion,
And a reset device electrically connected to the floating diffusion through the double conversion device.
The solid-state imaging device according to any one of [ 1 ] to [ 19 ], characterized in that,
The circuit also includes a source follower device electrically connected to the floating diffusion and a row select device electrically connected to the source follower device.
The solid-state imaging device according to any one of [ 1 ] to [ 20 ], characterized in that,
At the first side of the photoelectric conversion portion, the second sub-region includes at least a first region surface and a second region surface placed apart from the first region surface, at least a portion of the first sub-region is in contact with the first region surface, and at least a portion of the first sub-region is in contact with the second region surface,
The first charge transfer gate device is disposed at least in the first region surface and the second charge transfer gate device is disposed at least in the second region surface.
An electronic device, the electronic device comprising:
The solid-state imaging device according to any one of [1] to [ 21 ].
Effects of the invention
As described above, according to the present invention, a solid-state imaging device and an electronic apparatus capable of further improving the Full WELL CAPACITY (FWC) capacity can be provided.
Drawings
Fig. 1 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a first embodiment of the present invention.
Fig. 2 is a circuit diagram showing an example of a pixel according to the first embodiment of the present invention.
Fig. 3 is a block diagram of an imaging system according to a second embodiment of the present invention.
Fig. 4 is a circuit diagram showing an example of a solid-state imaging device according to a second embodiment of the present invention.
Fig. 5 is a top view of an exemplary circuit layout according to a second embodiment of the present invention.
Fig. 6 is a cross-sectional view of an example of a circuit layout along line A-A' of fig. 5.
Fig. 7 is a flow chart of a method of forming the pixel sensor of fig. 5.
Fig. 8 is a simulation result of electrostatic potential distribution of a pixel center and full well capacity simulated by 3D process and device simulation according to one example of the present invention.
Fig. 9 is a top view of an exemplary circuit layout according to a third embodiment of the present invention.
Fig. 10 is a circuit diagram showing an example of a solid-state imaging device according to a third embodiment of the present invention.
Fig. 11 is a top view of an exemplary circuit layout according to a fourth embodiment of the present invention.
Fig. 12 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to a fifth embodiment of the present invention.
Fig. 13 is a top view of an exemplary circuit layout according to a sixth embodiment of the invention.
Fig. 14 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to a seventh embodiment of the present invention.
Fig. 15 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to an eighth embodiment of the present invention.
Fig. 16 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to a ninth embodiment of the present invention.
Fig. 17 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to a tenth embodiment of the present invention.
Fig. 18 is a simplified cross-sectional view showing an example of the configuration of a main portion in a solid-state imaging device according to an eleventh embodiment of the present invention.
Fig. 19 is a simplified cross-sectional view showing an example of the configuration of a main part in an apparatus according to a twelfth embodiment of the present invention.
Fig. 20 is a schematic diagram showing a solid-state imaging device according to an embodiment of the present invention.
Fig. 21 is a block diagram of an electronic device according to an embodiment of the invention.
Fig. 22 is an example of a technique of applying the image sensor of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Further, in the present specification and the drawings, the same constituent elements having substantially the same functions and configurations are denoted by the same reference numerals, and repetitive descriptions will be omitted.
Solid-state imaging device
First, the solid-state imaging device 100 according to an embodiment of the present invention will be described in detail. The solid-state imaging device 100 according to this embodiment of the present invention includes the following features: a semiconductor layer 160 of a first conductivity type semiconductor; a photoelectric conversion portion 170 including a first side 171 and a second side 172 opposite to the first side 171, and being in contact with the semiconductor layer 160 at the first side 171; a charge transfer gate device electrically connected to the photoelectric conversion portion 170 and transferring the charge stored in the photoelectric conversion portion 170 to a floating diffusion 300 region, wherein the photoelectric conversion portion 170 includes at least a first sub-region 181 of the first conductivity type semiconductor and a second sub-region 182 of a second conductivity type semiconductor different from the first conductivity type semiconductor, the second sub-region 182 includes at least a first region surface and a second region surface disposed apart from the first region surface at the first side 171 of the photoelectric conversion portion 170, at least a portion of the first sub-region 181 is in contact with the first region surface, and at least a portion of the first sub-region 181 is in contact with the second region surface, wherein a thickness of the first sub-region 181 in a normal direction perpendicular to the first side 171 is smaller than a thickness of the second sub-region 182 in a direction perpendicular to the first side 171, the second sub-region 182 includes at least a first region surface and a second region surface disposed at the first charge transfer gate 550, and the second sub-region 181 is disposed at least at the first charge transfer gate 550 at the first region surface.
First embodiment
Fig. 1 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a first embodiment of the present invention. As shown in fig. 1, a solid-state imaging device 100 according to a first embodiment of the present invention includes a Photodiode (PD) 150, a first charge transfer gate device 450, and a second charge transfer gate device 550. The first charge transfer gate device 450 and the second charge transfer gate device 550 are electrically connected to a Photodiode (PD).
< Photodiode (PD) >
As shown in fig. 1, a Photodiode (PD) 150 includes a semiconductor layer 160, a photoelectric conversion portion 170, a separation layer 180, a color filter 250, a microlens 350, and a deep trench isolation 173 portion. The photoelectric conversion portion 170 includes a first side 171 and a second side 172 opposite to the first side 171. The photoelectric conversion portion 170 contacts the semiconductor layer 160 at the first side 171. The separation layer 180 is formed in a part of the photoelectric conversion portion 170. The deep trench isolation 173 is partially buried in the separation layer 180 from the side of the second side 172 of the photoelectric conversion portion 170. The color filter 250 is in contact with the photoelectric conversion portion 170 at the second side 172. The microlens 350 is in contact with the color filter 250. In the present embodiment, the Photodiode (PD) 150 is a pinned photodiode (pinned photodiode, PPD).
(Semiconductor layer)
As shown in fig. 1, the semiconductor layer 160 is a first conductive type semiconductor. The first conductive type semiconductor may be a p-type semiconductor or an n-type semiconductor. In fig. 1, in the present embodiment, the semiconductor layer 160 is a p-type semiconductor. The semiconductor layer 160 is bonded to the photoelectric conversion portion 170 and the separation layer 180. The doping concentration of the semiconductor layer 160 is preferably greater than the doping concentration of the separation layer 180.
(Photoelectric conversion portion)
As shown in fig. 1, the photoelectric conversion portion 170 includes a first sub-region 181 of a first conductivity type semiconductor and a second sub-region 182 of a second conductivity type semiconductor. The second conductivity type semiconductor is different from the first conductivity type semiconductor. As shown in fig. 1, the first sub-region 181 is a p-type semiconductor, and the second sub-region 182 is an n-type semiconductor. The second sub-region 182 has a deep PD layer 1821 and a shallow PD layer 1822. The shallow PD layer 1822 is divided into two regions by the first sub-region 181. That is, the two regions of the shallow PD layer 1822 do not contact each other. The doping concentration of the shallow PD layer 1822 is preferably less than the doping concentration of the separation layer 180.
On the first side 171 of the photoelectric conversion portion 170, the second sub-region 182 includes a first region surface (surface 'a' in fig. 1) and a second region surface (surface 'B' in fig. 1) placed apart from the first region surface. That is, the first area surface and the second area surface do not contact each other. The first region surface and the second region surface are surfaces of the shallow PD layer 1822 that are in contact with the semiconductor layer 160. At least a portion of the first sub-region 181 is in contact with the first region surface and at least a portion of the first sub-region 181 is in contact with the second region surface. That is, the first area surface and the second area surface are divided by the first sub-area 181. As shown in fig. 1, the first sub-region 181 is in contact with the semiconductor layer 160. The deep PD layer 1821 is simply connected. That is, the deep PD layer 1821 is formed as only one region, and the deep PD layer 1821 is not divided into two or more regions.
The first sub-area 181 is in contact with the second sub-area 182. The first sub-region 181 is in contact with the shallow PD layer 1822 and the deep PD layer 1821. The junction portion of the first sub-region 181 and the second sub-region 182 forms a pn junction. The pn junction has a junction capacitance. As shown in fig. 1, there are at least two pn junctions between the first sub-region 181 and the shallow PD layer 1822. In addition, there is one pn junction between the first sub-region 181 and the deep PD layer 1821. The shallow PD layer 1822 is in contact with the separation layer 180. The structure of the second sub-region 182 may also be a single layer structure. Further, the structure of the second subregion 182 may be a three-layer or more multi-layer structure.
The junction portion of the shallow PD layer 1822 and the separation layer 180 forms a pn junction. As shown in fig. 1, there are at least two pn junctions between the separation layer 180 and the shallow PD layer 1822. The deep PD layer 1821 is in contact with the separation layer 180. The junction portion of the deep PD layer 1821 and the separation layer 180 forms a pn junction. As shown in fig. 1, there are at least two pn junctions between separation layer 180 and deep PD layer 1821. The deep PD layer 1821 is in contact with both portions of the shallow PD divided by the first sub-region 181. The deep PD layer 1821 is electrically connected to two portions of the shallow PD divided by the first sub-region 181.
The thickness of the first sub-region 181 in the normal direction perpendicular to the first side 171 of the photoelectric conversion portion 170 is smaller than the thickness of the second sub-region 182 in the normal direction perpendicular to the first side 171 of the photoelectric conversion portion 170. That is, the first sub-region 181 is not exposed from the second side 172 of the photoelectric conversion portion 170.
(Separation layer)
In this embodiment, the separation layer 180 is formed in a portion of the photoelectric conversion portion 170. The portion of the separation layer 180 covers the photoelectric conversion portion 170 so that photoelectric conversion is not in contact with other portions than the separation layer 180. The separation layer 180 covers the deep PD layer 1821 and the shallow PD layer 1822. The separation layer 180 is a p-type semiconductor.
(Deep trench isolation portion)
As shown in fig. 1, the deep trench isolation 173 is partially buried in the separation layer 180 from the side of the second side 172 of the photoelectric conversion portion 170. The deep trench isolation 173 portions may be physical isolation portions. The height of the deep trench isolation 173 portion is greater than the height of the deep PD layer 1821 in a direction parallel to the normal of the first side 171. A separation layer 180 is formed between the deep trench isolation 173 portion and the photoelectric conversion portion 170. The deep trench isolation 173 partially overlaps the first sub-region 181 of the photoelectric conversion portion 170 in a normal direction perpendicular to the first side 171. The deep trench isolation 173 partially overlaps the shallow PD layer 1822 of the photoelectric conversion portion 170 in a normal direction perpendicular to the first side 171.
(Color Filter)
The type of the color filter 250 is not limited, and any known color filter 250 may be used. The color filter 250 may include a red filter, a green filter, and a blue filter.
(Microlens)
The type of microlens 350 is not limited, and any known microlens 350 may be used.
< Charge transfer Gate device >
In the present embodiment, the solid-state imaging device 100 includes a first charge transfer gate device 450 and a second charge transfer gate device 550. That is, the solid-state imaging device 100 includes two charge transfer gate devices. The first and second charge transfer gate devices 450 and 550 transfer charges stored in the photoelectric conversion portion 170 connected to the floating diffusion 300 region. The first charge transfer gate device 450 and the second charge transfer gate device 550 do not transfer charges stored in other pixels of the solid-state imaging device 100. The first charge transfer gate device 450 is electrically connected to a portion of the shallow PD layer 1822. The second charge transfer gate device 550 is electrically connected to another portion of the shallow PD layer 1822. The first charge transfer gate device 450 transfers charge across the surface of the first region of the shallow PD layer 1822. The second charge transfer gate device 550 transfers charge across the surface of the second region of the shallow PD layer 1822. The first charge transfer gate device 450 may also be used to transfer charge across the surface of the second region of the shallow PD layer 1822. The second charge transfer gate device 550 may also be used to transfer charge across the surface of the first region of the shallow PD layer 1822. The first and second charge transfer gates may have embedded portions in the semiconductor layer 160. The first charge transfer gate and the second charge transfer gate may be vertical transfer gates.
< Circuitry >
Fig. 2 is a circuit diagram showing an example of a pixel according to the first embodiment of the present invention. As shown in fig. 2, a pixel of the solid-state imaging device 100 according to the first embodiment of the present invention includes a Photodiode (PD) 150, a first charge transfer gate device 450, a second charge transfer gate device 550, a floating diffusion 300 region, a double conversion device 400, a reset device 500, a source follower device 600, a row selection device 700, and a current source 800. The floating diffusion 300 region is electrically connected to a first charge transfer gate device 450 and a second charge transfer gate device 550. The dual conversion device 400 is electrically connected to the floating diffusion 300 region. The reset device 500 is electrically connected to the floating diffusion 300 region through the double conversion device 400. The source follower device 600 is electrically connected to the floating diffusion 300 region. The row selection device 700 is electrically connected to the source follower device 600. Junction isolation or STI isolation may be used to divide the device elements of the solid-state imaging device 100.
(Photodiode (PD))
A Photodiode (PD) 150 generates and accumulates an amount of signal charge (here, electrons) corresponding to the amount of incident electromagnetic radiation. The case where the signal charge includes electrons and each transistor is an n-type transistor will be described below, but the signal charge may be holes and some transistors may be p-type transistors. In addition, the present embodiment is also effective in the case where each transistor is shared among a plurality of photodiodes and in the case where a three-transistor (3 Tr) pixel without a selection transistor is employed.
As the Photodiode (PD) 150, a pinned photodiode (pinned photodiode, PPD) may be used. On the substrate surface where the Photodiode (PD) 150 is formed, there is a surface level due to dangling bonds or other defects, and thus, thermal energy generates a large amount of charges (dark current), so that a correct signal cannot be read out any more. In the pinned photodiode (pinned photodiode, PPD), a charge accumulating portion of the Photodiode (PD) 150 is buried in the substrate, and thus dark current into a signal can be reduced.
However, in the case where the size is relatively large and the aspect ratio is relatively large, for example, in the case where the pixel is about 3 μm square, the accumulated charge is mainly limited to the pn junction capacitance in the vertical direction (normal direction of the substrate: depth direction of the substrate) near the position of the Photodiode (PD) 150 portion (photoelectric conversion portion 170), and thus it is difficult to effectively increase the storage capacity.
Therefore, in the solid-state imaging device 100 according to the present embodiment, in the photoelectric conversion portion 170 of the pinned photodiode (pinned photodiode, PPD), in order to increase the storage capacity, a plurality of sub-regions are provided by dividing the photoelectric conversion layer (for example, N layer) so that a plurality of pn junction portions exist in the normal direction (horizontal direction) perpendicular to the pixel-internal semiconductor layer 160. Other configurations of the Photodiodes (PDs) 150 are the same as those of the Photodiodes (PDs) 150 in the solid-state imaging device 100 described above.
(Charge transfer Gate device)
The solid-state imaging device 100 according to the present embodiment adopts a configuration capable of reading out the electric charges accumulated in the photoelectric conversion portion 170 through the two charge transfer gate devices including the transfer transistors TG to Tr. Therefore, in the solid-state imaging device 100 according to the present embodiment, the Full WELL CAPACITY (FWC) capacity can be improved while reducing noise and improving sensitivity. Therefore, the dynamic range can be enlarged without degrading the optical characteristics.
The first charge transfer gate device 450 and the second charge transfer gate device 550 may be composed of transfer transistors TG-Tr. First charge transfer gate device 450 and second charge transfer gate device 550 may be constructed, including: an n layer forming a floating diffusion 300 (floating diffusion, FD) region to which charges accumulated in a storage capacity portion formed in a sub-region in the photoelectric conversion portion 170 are transferred; a p layer formed between the semiconductor layer 160 and an n layer forming a floating diffusion 300 (floating diffusion, FD) region; a gate electrode (GT) formed by an insulating film at least on the semiconductor layer 160.
The two transfer transistors TG-Tr constituting the first and second charge transfer gate devices 450 and 550 are connected between a Photodiode (PD) 150 and a floating diffusion 300 (floating diffusion, FD) region. The two transfer transistors TG-Tr are controlled by a control signal TG. The two transfer transistors TG-Tr are selected in a period in which the control signal TG is at a high level (H) and becomes a conductive state, and transfer charges (electrons) subjected to photoelectric conversion and accumulated in the Photodiode (PD) 150 to the floating diffusion 300 (floating diffusion, FD) region.
(Floating diffusion)
The floating diffusion 300 region may be an n-type semiconductor. The floating diffusion 300 (floating diffusion, FD) region may be electrically connected to a variable capacity portion that is connected to the floating diffusion 300 (floating diffusion, FD) region and may change the capacity of the floating diffusion 300 (floating diffusion, FD) region in response to a capacity change signal CS.
(Double conversion apparatus)
The dual switching device 400 (dual conversion device, DCG) may be connected between the reset device 500 (RESET DEVICE, RST) and the floating diffusion 300 (floating diffusion, FD) regions to achieve a high dynamic range by combining the two types of gains. The dual conversion device 400 (dual conversion device, DCG) may be composed of MOS transistors. In some embodiments, dual conversion device 400 may be removed.
(Reset device)
The reset device 500 (RESET DEVICE, RST) selectively resets the charge accumulated in the FD. The reset device 500 (RESET DEVICE, RST) may be formed of MOS transistors.
(Source follower device)
The source follower device 600 (SF) may be connected between the row select device 700 (row-SELECT DEVICE, SEL) and the floating diffusion 300 (floating diffusion, FD) region. The source follower device 600 (SF) may be constituted by a MOS transistor or a JFET.
(Line selection device)
A row select device 700 (row-SELECT DEVICE, SEL) may be connected between the source follower device 600 (SF) and the current source 800. The row select device 700 (row-SELECT DEVICE, SEL) may be formed of MOS transistors.
(Current Source)
Current source 800 may be connected between row select device 700 (row-SELECT DEVICE, SEL) and ground. As the current source 800, a known current source 800 can be used.
(Substrate)
The elements of the solid-state imaging device 100 may be provided on a substrate (not shown in the figure). The semiconductor substrate may be composed of a semiconductor material (e.g., silicon or germanium). In some embodiments, the substrate may be comprised of at least one or more other radiation-sensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium, antimony, semiconductor-on-insulator, or combinations thereof.
Typically, the n-region (second sub-region 182) of the photodiode must be fully depleted. The depletion potential (voltage) must be low enough to complete the charge transfer. The maximum depletion potential must be near the first charge transfer gate device 450 and the second charge transfer gate device 550. In order to maximize the storage capacity, after the above space charge density condition is satisfied, the concentration of the second subregion 182 of the photoelectric conversion portion 170 needs to be maximized. However, if the impurity amount in the second subregion 182 of the photoelectric conversion portion 170 increases, the Photodiode (PD) 150 becomes deep in potential and the readout voltage increases. Thus, the concentration of the second subregion 182 is limited.
Therefore, by providing a p region (first sub region 181) having a depletion layer distance Wd shorter than the pixel pitch in the normal direction X perpendicular to the semiconductor layer 160 at an n region (second sub region 182) in the photoelectric conversion portion 170, the storage capacity in the photoelectric conversion portion 170 having a lower depletion voltage Vapp can be increased. Therefore, the saturated output at the same read voltage is improved.
Further, the Full Well Capacity (FWC) is one of important key performance indicators of the solid-state imaging device 100 s. Under high intensity glare, lower full well capacity results in lower dynamic range (DYNAMIC RANGE, DR) and lower signal-to-noise ratio (signal to noise ratio, SNR). Therefore, higher full well capacity is always preferred. However, other key performance indicators are competing with full well capacity. It is strongly desired to increase the full well capacity as much as possible with a limited area.
According to the present embodiment of the present invention, each pixel has a Deep Portion (DPD) of one photodiode, and there are a plurality of photodiode (SPD) regions from the middle to the device side, i.e., by vertically disposing a p-type separation layer, as shown in fig. 1. The deep portion extends from the photosensitive surface on the device side to a depth intermediate the photodiodes. This structure can increase the pn junction capacitance in the photodiode, thereby increasing the full well capacity. In this case, the finely divided shallow photodiodes (shallow photodiode, SPD) should have separate transfer gates, which have sufficiently high charge transfer capability and further increase the full well capacity (full WELL CAPACITY, FWC). The pixel circuit is also shown in fig. 2.
In addition, according to the present embodiment of the present invention, the first sub-region 181 of the photoelectric conversion portion 170 is in contact with the semiconductor layer 160, and the semiconductor type of the semiconductor layer 160 is the same as the semiconductor type of the first sub-region 181 of the photoelectric conversion portion 170. Therefore, the inserted vertical p-type layer can be prevented from floating or the resistance between the p-type layer and the p-well electrode is excessively high. Therefore, the pn junction capacitance becomes higher, and the full well capacity (full WELL CAPACITY, FWC) increases more.
Second embodiment
< Imaging System >
A second embodiment of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 3 is a block diagram of an imaging system 201 according to a second embodiment of the present invention. As shown in fig. 3, the imaging system 201 includes a control circuit 205, a pixel array 209, a readout circuit 210, and a signal processing circuit 206. The pixel array 209 is a two-dimensional pixel array. Each pixel may be an imaging device as shown in fig. 2. Pixels are arranged in rows (R1 to Ry) and columns (C1 to Cx) to acquire image data of an object. The control circuit 205 controls the pixel array 209, for example, generates a shutter signal. The image data is read out by the readout circuit 210 through the bit lines and sent to the signal processing circuit 206.
In the present embodiment, the imaging system 201 is constituted by, for example, a CMOS image sensor 201A. In the present embodiment, the imaging system 201 includes the solid-state imaging device 100 according to the first embodiment. Further, in the present embodiment, the solid-state imaging device 100 has pixels arranged in a matrix in the pixel array 209 as photoelectric conversion elements. In the present embodiment, the photoelectric conversion element is the photoelectric conversion portion 170. Each pixel is formed of a Photodiode (PD) 150. In this embodiment, the photodiode is a pinned photodiode (pinned photodiode, PPD). The configuration of the Photodiode (PD) 150 may be the same as that of the Photodiode (PD) 150 in the first embodiment of the present invention.
For example, each pixel in the CMOS image sensor 201A may be configured to include four elements, that is, a transfer element including a transfer transistor, a reset element including a reset transistor, a source follower element (amplification element) including a source follower transistor, and a selection element including a selection transistor as active elements for one photodiode. In addition, one overflow gate (overflow transistor) may be provided for each pixel for discharging overflowing electric charge overflowing from the photodiode during an accumulation period of the photodiode. Further, each pixel may be provided with a dual conversion device 400 (dual conversion device, DCG).
The transfer transistor may be connected between the photodiode and an output node including a floating diffusion 300 region layer (floating diffusion, FD). The transfer transistor may remain in a non-conductive state during the charge accumulation period of the photodiode. In a transfer period in which the charges accumulated in the photodiode are transferred to the floating diffusion 300 region, a control signal is supplied to the gate, whereby the control signal is maintained in a conductive state and the charges photoelectrically converted in the photodiode are transferred to the floating diffusion 300 (floating diffusion, FD) region.
The reset transistor is connected between the power supply line and the floating diffusion 300 (floating diffusion, FD) region. When a reset use control signal is given at the gate thereof, the reset transistor resets the potential of the floating diffusion 300 (floating diffusion, FD) region to the potential of the power supply line.
The floating diffusion 300 (floating diffusion, FD) region is connected to the gate of the source follower transistor. The source follower transistor is connected to a vertical signal line through a selection transistor, and constitutes a source follower together with a constant current source 800 of a load circuit outside the pixel portion. Further, a control signal (address signal or selection signal) is supplied to the gate of the selection transistor, thereby turning on the selection transistor. When the selection transistor is turned on, the source follower transistor amplifies the potential of the floating diffusion 300 (floating diffusion, FD) region, and outputs a voltage to the vertical signal line according to the potential. The voltage output from the pixel is output to the pixel signal readout circuit 210 constituted by the column parallel processing section through the vertical signal line.
Further, in each pixel, as a Photodiode (PD) 150, a pinned photodiode (pinned photodiode, PPD) is widely used. On the substrate surface where the Photodiode (PD) 150 is formed, there is a surface level due to dangling bonds or other defects, and thus, thermal energy generates a large amount of charges (dark current), so that a correct signal cannot be read out any more. In the pinned photodiode (pinned photodiode, PPD), a charge accumulating portion of the Photodiode (PD) 150 is buried in the substrate, and thus dark current into a signal can be reduced. Note that the sensitivity of the Photodiode (PD) 150 may be changed by, for example, changing the exposure time or the like.
For example, a pinned photodiode (pinned photodiode, PPD) is configured by forming an n-type semiconductor region, and forming a shallow p-type semiconductor region having a thick impurity concentration on the surface of the n-type semiconductor region (i.e., near the interface with an insulating film) to suppress dark current.
< Circuitry >
Fig. 4 is a circuit diagram showing an example of a pixel according to the second embodiment of the present invention. As shown in fig. 2, the circuit has four sets of PDs and TX that share in-pixel devices and may be the pixels in fig. 3. A Photodiode (PD) 150 converts electromagnetic radiation into electrical charge. Charge is selectively sent to the floating diffusion 300 (floating diffusion, FD) region through the transfer gate device (TRANSFER GATE DEVICE, TX). The FD layer is connected to a gate of a Source Follower (SF) device 600 (SF), and an output signal (Vout) is sent to a signal line through a row selection device (row SELECT DEVICE, SEL). Current source 800 (Icolumn) is connected between SEL and ground. Accordingly, if the gates of TX and SEL are on, an output signal corresponding to the electrical signal from the PD is acquired on the signal line. The reset device 500 (RESET DEVICE, RST) selectively resets the charge accumulated in the FD. The dual conversion (dual conversion gain, DCG) device can be connected between the RST and FD layers, also becoming a high dynamic range achieved by combining the two types of gains. In the case of an n-type photodiode, AVSS1 may be grounded or a negative voltage in the range of-5.0V to 0V. In some embodiments, the photodiode is p-type and the pixel-to-pixel isolation is n-type.
In the present embodiment, the readout circuit 210 is configured such that the readout circuit is capable of performing a first conversion gain mode read operation of reading out the pixel signal at the first conversion gain in accordance with the first capacity set by the variable capacity section and a second conversion gain mode read operation of reading out the pixel signal at the second conversion gain in accordance with the second capacity set by the variable capacity section (different from the first capacity) in one read cycle. That is, the solid-state imaging device 100 in the present embodiment is provided as the solid-state imaging device 100 having a wide dynamic range, which outputs a signal concerning charges (electrons) photoelectrically converted in one accumulation period (exposure period) and outputs a bright signal and a dark signal while switching between a first conversion gain (e.g., high conversion gain) mode and a second conversion gain (low conversion gain) mode inside a pixel in one reading period.
The readout circuit 210 in the present embodiment performs the first conversion gain mode read operation and the second conversion gain mode read operation substantially in an accumulation period after a reset period for discharging the charges in the photodiode and floating diffusion 300 region. Further, in the present embodiment, the readout circuit 210 performs at least one of the first conversion gain mode read operation or the second conversion gain mode read operation in a read period subsequent to at least one transfer period subsequent to a read period subsequent to the reset period. That is, in a read period subsequent to the transfer period, the first conversion gain mode read operation and the second conversion gain mode read operation are sometimes performed simultaneously.
In the normal pixel readout operation, a shutter scanning operation is performed by driving of the readout circuit 210, and then a read scanning operation is performed. A first conversion gain mode (HCG) read operation and a second conversion gain mode (LCG) read operation are performed in a read scan period.
A plurality of pixels each including a photodiode (photoelectric conversion element) and an in-pixel amplifier are arranged in a two-dimensional matrix including N rows and M columns.
The pixel has, for example, a Photodiode (PD) 150 as a photoelectric conversion portion 170 (photoelectric conversion element). For this Photodiode (PD) 150, each of a first charge transfer gate device 450 constituted by a transfer transistor TG-Tr, a second charge transfer gate device 550 constituted by a transfer transistor TG-Tr, a reset device 500 constituted by a reset transistor RST-Tr, a source follower device 600 constituted by a source follower transistor SF-Tr, and a row selection device 700 constituted by a selection transistor SEL-Tr is provided.
Further, the pixel may have a variable capacity portion that is connected to the floating diffusion 300 (floating diffusion, FD) region (floating diffusion 300 region layer) and may change the capacity of the floating diffusion 300 (floating diffusion, FD) region in response to the capacity change signal CS.
A Photodiode (PD) 150 generates and accumulates an amount of signal charge (here, electrons) corresponding to the amount of incident electromagnetic radiation. In the following, a case where the signal charge includes electrons and each transistor is an n-type transistor will be described, but the signal charge may include holes, and some transistors may be p-type transistors. In addition, the present embodiment is also effective in the case where each transistor is shared among a plurality of photodiodes and in the case where a three-transistor (3 Tr) pixel without a selection transistor is employed.
In each pixel, as a Photodiode (PD) 150, a pinned photodiode (pinned photodiode, PPD) may be used. On the substrate surface where the Photodiode (PD) 150 is formed, there is a surface level due to dangling bonds or other defects, and thus, thermal energy generates a large amount of charges (dark current), so that a correct signal cannot be read out any more. In the pinned photodiode (pinned photodiode, PPD), a charge accumulating portion of the Photodiode (PD) 150 is buried in the substrate, and thus dark current into a signal can be reduced.
However, in the case where the size is relatively large and the aspect ratio is relatively large, for example, in the case of about 3 μm square pixel, the accumulated charge is mainly limited to the pn-junction capacitance in the vertical direction (normal direction of the semiconductor layer 160: depth direction of the semiconductor layer 160) near the position of the Photodiode (PD) 150 portion (photoelectric conversion portion 170), and thus it is difficult to effectively increase the storage capacity.
Therefore, in the solid-state imaging device 100 of the present embodiment, in the photoelectric conversion portion 170 of the pinned photodiode (pinned photodiode, PPD), in order to increase the storage capacity, a plurality of sub-regions are provided by dividing the photoelectric conversion layer (for example, N layer) so that there are a plurality of pn junction portions in the normal direction (horizontal direction) perpendicular to the substrate inside the pixel. Other effects of the second embodiment of the present invention are the same as those of the first embodiment.
Fig. 5 is a top view of an exemplary circuit layout according to the present embodiment of the invention. As shown in fig. 5, a Photodiode (PD) 150 is divided into two parts by a vertically inserted intermediate depth p-well (MIDDLEDEPTH P-well, MPW), and a transfer gate is also divided into two parts. The reason for using the divided transfer gate is to reduce leakage current in the floating diffusion 300 region due to GIDL by reducing the gate region in contact with the floating diffusion 300 region. GIDL is critical to this architecture because the transfer gate bias remains negative during exposure to suppress dark current induced by the transfer gate region. In some embodiments, the width of the MPW ranges from 0.1 μm to 0.5 μm. The vertically inserted intermediate depth p-well (MIDDLEDEPTH P-well, MPW) is the first sub-region 181 of the photoelectric conversion portion 170.
As shown in fig. 5, there are 4 sub-pixels in the pixel set 2091. The set of pixels 2091 may correspond to one pixel (P1, P2, P3, … …) in the pixel array 209 of the imaging system 201 in fig. 3. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094, and a lower right sub-pixel 2095. Each sub-pixel has a first charge transfer gate device 450 and a second charge transfer gate device 550. The first charge transfer gate device 450 is connected to the second charge transfer gate device 550 through a wiring 2099. The vertically inserted intermediate depth p-well of the upper left subpixel 2092 is connected to the vertically inserted intermediate depth p-well of the lower left subpixel 2093. The vertically inserted intermediate depth p-well of the upper right sub-pixel 2094 is connected to the vertically inserted intermediate depth p-well of the lower right sub-pixel 2095.
Fig. 6 is a cross-sectional view of an exemplary circuit layout along line A-A' of fig. 5. As shown in fig. 6, line A-A' intersects the lower left subpixel 2093 and the lower right subpixel 2095. The lower left subpixel 2093 has a Photodiode (PD) 150, a first charge transfer gate device 450, and a second charge transfer gate device 550. The Photodiode (PD) 150 of the lower left sub-pixel 2093 includes a semiconductor layer 160, a photoelectric conversion portion 170, a separation layer 180, a color filter 250, a microlens 350, a deep trench isolation 173, an anti-reflection 183, and a metal grid 185. As shown in fig. 6, the lower left sub-pixel 2093 shares the separation layer 180 with the lower right sub-pixel 2095. A vertically inserted intermediate depth P-well (MIDDLEDEPTH P-well, MPW) is electrically connected to AVSS1 through a shallow P-well (SPW), a pinned photodiode (pinned photodiode, PPD), and p+ source/drain. The depth of MPW ranges from 0.0 μm or more to less than or equal to 3.0 μm. In this embodiment, at least one cross-sectional area of the first sub-area 181 parallel to the first side 171 may be greater than another cross-sectional area of the first sub-area 181 parallel to the first side 171. At least one region of the first sub-region 181 is doped at a different concentration than other regions of the first sub-region 181. In addition, the first sub-region 181 has an intermediate p-well portion 1811 (MPW) and a shallow intermediate p-well portion 1812. A cross-sectional area of the middle p-well portion 1811 (MPW) parallel to the first side 171 may be greater than an area of the first sub-region 181 at the first side 171. As shown in fig. 6, an intermediate p-well section 1811 (MPW) is disposed separately from the semiconductor layer 160. The doping concentration of the shallow intermediate p-well portion 1812 is greater than the doping concentration of the intermediate p-well portion 1811 (MPW).
In this embodiment, at least one cross-sectional area of the separation layer 180 parallel to the first side 171 may be greater than another cross-sectional area of the separation layer 180 parallel to the first side 171. Further, the separation layer 180 is in contact with the semiconductor layer 160. The separation layer 180 has a deep p-well portion having a cross-sectional area parallel to the first side 171 that is larger than an area of a portion of the separation layer 180 in contact with the semiconductor layer 160. As shown in fig. 6, the deep p-well portion is placed separately from the semiconductor layer 160. In this embodiment, at least one region of the separation layer 180 is doped at a different concentration from other regions of the separation layer 180. As shown in fig. 6, the separation layer 180 has a shallow p-well region 1801 (SPW) and a deep p-well region 1802 (DPW). The doping concentration of the shallow p-well region 1801 (SPW) is greater than the doping concentration of the deep p-well region 1802 (DPW).
The deep trench isolation 173 is partially buried in the deep p-well portion of the separation layer 180 from the side of the second side 172 of the photoelectric conversion portion 170. Deep trench isolation 173 does not partially penetrate the deep p-well portion of separation layer 180. An anti-reflection 183 portion is present between the deep p-well portion and the deep trench isolation 173 portion of separation layer 180. The deep trench isolation 173 portion has a plate portion 1731 and a buried portion. The plate portion 1731 is placed at the second side 172 of the photoelectric conversion portion 170. The plate portion 1731 covers the lower left subpixel 2093 and the lower right subpixel 2095. An anti-reflection 183 portion exists between the plate portion 1731 and the photoelectric conversion portion 170. The plate portion 1731 connects the deep trench isolation 173 portion of the lower left subpixel 2093 and the deep trench isolation 173 portion of the lower right subpixel 2095 that is not buried in the separation layer 180 common to the lower left subpixel 2093.
< Control method of imaging System >
Hereinafter, a control method of the imaging system 201 according to the second embodiment of the present invention will be described in detail. The reset device 500 is constituted by reset transistors RST-Tr. The reset transistors RST-Tr are connected between the power line AVDD and the floating diffusion 300 (floating diffusion, FD) region and controlled by a control signal RST. As shown in fig. 4, the reset transistors RST-Tr may be connected between the power line AVDD and the floating diffusion 300 (floating diffusion, FD) region, and may also be controlled by a control signal RST. The power line AVDD may be connected to the source follower device 600. The power line AVDD may be connected to a gate of the row selection device 700. The reset transistors RST-Tr are selected and enter a conductive state when the control signal RST is at the H level, and reset the floating diffusion 300 (floating diffusion, FD) region to the potential of the power supply line AVDD (or VRst).
Note that, as will be explained later, the present embodiment may be configured such that the first combining transistors (P1, P2, … …, pn, pn+1) serving as the double conversion device 400 also have a function as the reset device 500. Further, a configuration may also be adopted in which all pixels (four in this example) among the plurality of pixels connected by the first merge transistor (Pn, pn+1) share the reset device 500 formed by the first merge transistor (pn+1) which releases the floating diffusion 300 (floating diffusion, FD) region in the reset period PR.
The source follower device 600 is constituted by source follower transistors SF-Tr. The row selection device 700 is constituted by selection transistors SEL-Tr. The source follower transistors SF-Tr and the selection transistors SEL-Tr (the row selection device 700) are connected in series between the power supply line AVDD and the vertical signal line Vout. The gate of the source follower transistor SF-Tr is connected to the floating diffusion 300 (floating diffusion, FD) region. The selection transistors SEL-Tr are controlled by a control signal SEL. The selection transistors SEL-Tr are selected and enter a conductive state when the control signal SEL is at an H level (high level). Accordingly, the source follower transistor SF-Tr outputs a column-output readout signal VSL, which is obtained by converting the charge in the floating diffusion 300 (floating diffusion, FD) region into a voltage signal having a gain corresponding to the amount of charge (potential), to the vertical signal line Vout. Since gates of, for example, the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in units of rows, these operations are performed in parallel at the same time for one row of pixels.
As shown in fig. 3, the pixel array 209 is arranged in Y rows (R1, R2, … …) and X columns (C1, C2, … …). Y and X are positive integers. Accordingly, the control lines LSEL, LRST, and LTG each have Y pieces, and the vertical signal line Vout has X pieces. For example, the control lines LSEL, LRST, and LTG may be configured as one row scanning control line. One pixel (RX, RY) is the pixel set 2091 in fig. 5.
The control circuit 205A may have a vertical scanning circuit and a timing control circuit 205A. The vertical scanning circuit drives pixels through row scanning control lines in the shutter row and the read row under the control of the timing control circuit 205A. Further, the vertical scanning circuit outputs a row selection signal having a row address of a read row for the read signal and a row address of a shutter row for resetting charges accumulated in a Photodiode (PD) 150 according to the address signal.
The readout circuit 210 may have a reading portion and a horizontal scanning circuit. In the normal pixel readout operation, the shutter scan is performed by driving the reading section by the horizontal scanning circuit. Subsequently, a read scan is performed.
Next, operation timings of shutter scanning and reading scanning at the time of the normal pixel readout operation in the present embodiment will be described.
The control signal SEL for controlling the on (conductive) and off (nonconductive) states of the selection transistor SEL-Tr is set to an L level (low level) in the shutter scan period PSHT so that the selection transistor SEL-Tr maintains the nonconductive state, and is set to an H level in the read scan period PRDO so that the selection transistor SEL-Tr maintains the conductive state. Further, in the shutter scan period PSHT, the control signal TG is set to the H level for a predetermined period in which the control signal RST is the H level, so that the Photodiode (PD) 150 and the floating diffusion 300 (floating diffusion, FD) regions are reset by the reset transistors RST-Tr and the transfer transistors TG-Tr.
In the read scan period PRDO, the control signal RST is set to an H level, so that the floating diffusion 300 (floating diffusion, FD) region is reset by the reset transistors RST-Tr. In a read period PRD1 after the reset period PR, a signal in a reset state is read out. After the read period PRD1, the control signal TG is set to an H level for a predetermined period, so that charges accumulated in the Photodiode (PD) 150 are transferred to the floating diffusion 300 (floating diffusion, FD) region through the transfer transistor TG-Tr. In a read period PRD2 after the transfer period PT, a signal corresponding to the accumulated electrons (charges) is read out.
Note that in the normal pixel readout operation in the present embodiment, the accumulation period (exposure period) EXP is a period from resetting the Photodiode (PD) 150 and floating diffusion 300 (floating diffusion, FD) regions in the shutter scan period PSHT to switch the control signal TG to the L level until the control signal TG is switched to the L level again to end the transfer period PT in the read scan period PRDO.
The readout circuit 210 may be configured to include a plurality of column signal processing circuits 2061 (not shown) which are arranged to correspond to column outputs of the pixel array 209 so that column parallel processing is possible between the plurality of column signal processing circuits 2061.
The readout circuit 210 may be configured to include a correlated double sampling (correlated double sampling, CDS) circuit or an analog-to-digital converter (ADC: AD converter), an Amplifier (AMP), a sample/hold (S/H) circuit, and the like.
In this way, the readout circuit 210 may include ALC, for example, for converting the readout signal Vout output by the columns of the pixel array 209 into a digital signal. Otherwise, in the readout circuit 210, for example, an Amplifier (AMP) for amplifying the readout signal Vout of the column output of the pixel array 209 may be provided. Further, in the readout circuit 210, for example, a sample/hold (S/H) circuit for sampling and holding the readout signal Vout output from the column of the pixel array 209 may be provided.
The horizontal scanning circuit scans signals processed in the plurality of column signal processing circuits 2061, for example, ALC in the readout circuit 210, transfers the result to the horizontal direction, and outputs the result to the signal processing circuit 206, which is not shown.
The timing control circuit 205A generates timing signals necessary for signal processing in the pixel array 209, the vertical scanning circuit, the reading section, the horizontal scanning circuit, and the like.
The configuration and functions of the respective components in the solid-state imaging device 100 are briefly described above. Next, the configuration of the double conversion apparatus 400 according to the present embodiment, readout processing and the like related thereto will be described in detail. The dual conversion apparatus 400 is composed of a variable capacity section.
Further, as described above, in the photoelectric conversion portion 170 of the pinned photodiode (pinned photodiode, PPD) in each pixel set 2091, in order to increase the storage capacity, the photoelectric conversion layer made up of n layers is divided by p layers to provide a plurality of sub-regions (the first sub-region 181 and the second sub-region 182) so as to have a plurality of pn junction portions in the normal direction (horizontal direction) perpendicular to the semiconductor layer 160 inside the pixel set 2091. By forming two sub-regions (the first sub-region 181 and the second sub-region 182) from the p-layer (the first conductivity type semiconductor) in the pinned photodiode (pinned photodiode, PPD) of each pixel set 2091 in the normal direction perpendicular to the semiconductor layer 160 in this manner, full depletion can be achieved even with a low bias voltage. Further, in the solid-state imaging device 100 of the present embodiment, the charge accumulated in the sub-region by the charge transfer section constituted by the two transfer transistors TG to Tr can be read out. Accordingly, the storage capacity can be increased while reducing noise and improving sensitivity, and the dynamic range can be enlarged without reducing the optical characteristics.
In the present embodiment, description has been made by way of example in which sub-pixel charges in all sub-pixels each stored in the pixel array 209 are sequentially read out by using the row selection transistor, and data is read out as a frame composed of all sub-pixels in the pixel array 209. Alternatively, however, an image sensor that operates by a method called "event-driven type" instead of reading out data as a frame may be realized by using the pixels of the present embodiment. The event driven image sensor can output data over time in an asynchronous manner in response to changes in the intensity of electromagnetic waves incident on the pixelets 2091. Specifically, for example, if the sub-pixel charge generated by the electromagnetic wave incident on the photodiode and stored in the photodiode exceeds a predetermined threshold value, an event that the electromagnetic wave intensity exceeds the threshold value or data of the electromagnetic wave intensity may be output together with the coordinates and timing information of the sub-pixel. When there is only one sub-pixel in the pixel set 2091, the sub-pixel can be read as the pixel set 2091.
As described above, in the solid-state imaging device 100 of the present embodiment, the pinned photodiode (pinned photodiode, PPD) has: a semiconductor layer 160 of a first conductivity type semiconductor; a photoelectric conversion portion 170 having a first side 171 and a second side 172 opposite to the first side 171, and being in contact with the semiconductor layer 160 at the first side 171; a charge transfer gate device electrically connected to the photoelectric conversion portion 170 and transferring charges stored in the photoelectric conversion portion 170 to the floating diffusion 300 region. In addition, the photoelectric conversion portion 170 includes at least a first sub-region 181 of a first conductivity type semiconductor and a second sub-region 182 composed of a second conductivity type semiconductor different from the first conductivity type semiconductor. Further, the charge transfer gate device has a first charge transfer gate device 450 and a second charge transfer gate device 550, the first charge transfer gate device 450 being disposed in at least a first region surface and the second charge transfer gate device 550 being disposed in at least a second region surface. Further, in the solid-state imaging device 100 of the present embodiment, in the pinned photodiode (pinned photodiode, PPD), in order to increase the storage capacity, the photoelectric conversion portion 170 constituted by n layers is divided by p layers to provide a plurality of sub-regions (first sub-region 181 and second sub-region 182) so as to have a plurality of pn junction portions (junction portions) in the normal direction perpendicular to the semiconductor layer 160 inside the pixel set 2091.
In this way, in the pinned photodiode (pinned photodiode, PPD) of the first embodiment, by forming two sub-regions (the first sub-region 181 and the second sub-region 182) from the p-layer (the first conductivity type semiconductor) in the normal direction perpendicular to the semiconductor layer 160, it is possible to achieve complete depletion even with a low bias voltage as compared with the comparative example in which no sub-region is formed. Therefore, in the solid-state imaging device 100 of the present embodiment, the storage capacity can be increased while reducing noise and improving sensitivity, and the dynamic range can be enlarged without reducing the optical characteristics.
Further, the Full Well Capacity (FWC) is one of important key performance indicators of the solid-state imaging device 100 s. In intense light, lower full well capacity results in a low dynamic range (DYNAMIC RANGE, DR) and a low signal-to-noise ratio (SNR). Therefore, higher full well capacity is always preferred. However, other key performance indicators are competing with full well capacity. It is strongly desired to increase the full well capacity as much as possible with a limited area.
According to the present embodiment of the present invention, each pixel has a deep portion of one photodiode (FD), and there are a plurality of photodiode (FD) layers from the middle to the device side, that is, by vertically disposing a p-type separation layer, as shown in fig. 1. The deep portion extends from the photosensitive surface on the device side to the intermediate depth of the photodiode. This structure can increase the pn junction capacitance in the photodiode and then increase the full well capacity. In this case, the finely divided shallow photodiodes (shallow photodiode, SPD) should have separate transfer gates, which have sufficiently high charge transfer capability and further increase the full well capacity (full WELL CAPACITY, FWC).
In addition, according to the present embodiment of the present invention, the first sub-region 181 of the photoelectric conversion portion 170 is in contact with the semiconductor layer 160, and the semiconductor type of the semiconductor layer 160 is the same as the semiconductor type of the first sub-region 181 of the photoelectric conversion portion 170. Therefore, the inserted vertical p-type layer can be prevented from floating or the resistance between the p-type layer and the p-well electrode is excessively high. Therefore, the pn junction capacitance becomes higher, and the full well capacity (full WELL CAPACITY, FWC) increases more.
In addition, according to the first embodiment, such effects can be obtained: in one reading period, while switching between the high conversion gain mode and the low conversion gain mode inside the pixel group 2091, a signal of electric charge (electrons) photoelectrically converted in one accumulation period (exposure period) can be output, thereby outputting a bright signal and a dark signal, reset noise at the time of the high conversion gain mode and the low conversion gain mode can be eliminated, expansion of a dynamic range can be realized, and occurrence of distortion of a moving object can be suppressed, and thus higher image quality can be realized.
Further, according to the present embodiment, the number of connected floating diffusion 300 (floating diffusion, FD) regions can be flexibly switched, and therefore, the configuration is excellent in terms of the expansibility of the dynamic range. Further, the pixels in the pixel set 2091 share a floating diffusion 300 (floating diffusion, FD) region. In addition, the number of transistors in each pixel set 2091 is small. Therefore, it is possible to improve the PD aperture ratio and to improve the photoelectric conversion sensitivity and the number of saturated electrons.
Third embodiment
Hereinafter, the solid-state imaging device 100A according to the third embodiment of the present invention will be described in detail with reference to the drawings. Fig. 9 is a top view of an exemplary circuit layout according to a third embodiment of the present invention. As shown in fig. 9, the first sub-region 181 of the solid-state imaging device 100A has an x-direction portion 1813 and a y-direction portion 1814. x-direction portion 1813 intersects y-direction portion 1814. The first sub-area 181 is cross-shaped in top view. There are 4 subpixels in the pixel set 2091. The set of pixels 2091 may correspond to one pixel (P1, P2, P3, … …) in the pixel array 209 of the imaging system 201 in fig. 3. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094, and a lower right sub-pixel 2095. Each pixel has a first charge transfer gate device 450, a second charge transfer gate device 550, a third charge transfer gate device 650, and a fourth charge transfer gate device 750. The shallow PD layer 1822 is divided into 4 parts by the x-direction and the y-direction of the first sub-region 181 of each pixel. The embodiment can further increase the pn junction capacitance in the photodiode, thereby contributing to further improvement of the full well capacity. This configuration exhibits greater robustness to overlay errors of the pixel layer.
Fig. 10 is a circuit diagram showing an example of a pixel according to the third embodiment of the present invention. The circuit in fig. 10 is an equivalent circuit of the exemplary circuit layout in fig. 9 according to the third embodiment of the present invention. In contrast to the circuit of the second embodiment in fig. 4, a Photodiode (PD) 150 is electrically connected to four charge transfer gate devices. That is, there are 16 charge transfer gate devices in the pixel set 2091.
Fourth embodiment
Hereinafter, the solid-state imaging device 100B according to the fourth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 11 is a top view of an exemplary circuit layout according to a fourth embodiment of the present invention. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094, and a lower right sub-pixel 2095. Each pixel has a first charge transfer gate device 450 and a second charge transfer gate device 550. The shallow photodiode is divided into two parts by a first sub-region 181. As shown in fig. 11, the first sub-region 181 may be a vertically inserted intermediate depth p-well (MIDDLEDEPTH P-well, MPW).
As shown in fig. 11, the pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094, and a lower right sub-pixel 2095. Each sub-pixel has a first charge transfer gate device 450 and a second charge transfer gate device 550. The first charge transfer gate device 450 is connected to the second charge transfer gate device 550 through a wiring 2099. The vertically inserted intermediate depth p-well of the upper left subpixel 2092 is connected to the vertically inserted intermediate depth p-well of the lower right subpixel 2095. The vertically inserted intermediate depth p-well of the upper right sub-pixel 2094 is connected to the vertically inserted intermediate depth p-well of the lower left sub-pixel 2093. The vertically interposed intermediate depth p-well of the upper left subpixel 2092, lower left subpixel 2093, upper right subpixel 2094, and lower right subpixel 2095 is cross-shaped in top view. The embodiment can further increase the pn junction capacitance in the photodiode, thereby contributing to further improvement of the full well capacity. This configuration exhibits greater robustness to overlay errors of the pixel layer.
Fifth embodiment
Hereinafter, the solid-state imaging device 100C according to the fifth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 12 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a fifth embodiment of the present invention. As shown in fig. 12, the first charge transfer gate device 450 and the second charge transfer gate device 550 have portions embedded in the photoelectric conversion portion 170. When the shallow photodiode is divided into two parts by the first sub-region 181, the first charge transfer gate device 450 is embedded in a different part from the second charge transfer gate device 550. As shown in fig. 12, a gate insulator 190 is placed between the first charge transfer gate device 450 and the shallow photodiode and between the second charge transfer gate device 550 and the shallow photodiode. This embodiment can enhance the charge transfer capability and can increase the full well capacity.
< Sixth embodiment >
Hereinafter, the solid-state imaging device 100D according to the sixth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 13 is a top view of an exemplary circuit layout according to a sixth embodiment of the invention. As shown in fig. 13, the vertically inserted intermediate p-well region is not included in the floating diffusion 300 region. That is, the vertically interposed intermediate p-well region is placed separately from the floating diffusion 300 region. On the first side 171 of the photoelectric conversion portion 170, a first sub-region is provided so as to protrude from the separation layer. The second sub-region 182 is almost divided into two regions. The present embodiment can further improve the fixed pattern noise caused by the leakage of the floating diffusion 300 region.
< Seventh embodiment >
Hereinafter, the solid-state imaging device 100E according to the seventh embodiment of the present invention will be described in detail with reference to the drawings. Fig. 14 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a seventh embodiment of the present invention. As shown in fig. 14, deep trench isolation 173 is formed in the vertically interposed intermediate p-well region. The negative charge of the anti-reflection 183 portion may contribute to photodiode capacitance. The anti-reflection 183 portion may be in the shape of a thin film. The deep trench isolation 173 is partially buried within a deep PD layer 1821 of the photoelectric conversion portion 170. The deep trench isolation 173 is partially buried in the first sub-region 181 of the photoelectric conversion portion 170 from the side of the second side 172 of the photoelectric conversion portion 170. The deep PD is separated into two parts by deep trench isolation 173. The embodiment can further improve the full well capacity.
< Eighth embodiment >
Hereinafter, the solid-state imaging device 100F according to the eighth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 15 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to an eighth embodiment of the present invention. As shown in fig. 15, the deep trench isolation 173 has a full depth. That is, the deep trench isolation 173 is partially buried in the semiconductor layer 160 from the side of the second side 172 of the photoelectric conversion portion 170. The full depth deep trench isolation 173 can be made from either the front side or the back side. The back side represents the back side of the page and the front side represents the front side of the page. With the present embodiment, the anti-blurring performance can be improved. In addition, the full well capacity can be further improved due to the larger anti-blurring design margin.
< Ninth embodiment >
Hereinafter, a solid-state imaging device 100G according to a ninth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 16 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a ninth embodiment of the present invention. In the present embodiment, the second sub-region 182 of the photoelectric conversion portion 170 has the extremely deep p-well region 174. The ultra-deep p-well region 174 is formed of a first conductivity type semiconductor. In this embodiment, the ultra-deep p-well region 174 is formed of a p-type semiconductor. Ultra-deep p-well region 174 is disposed between deep PD layer 1821 and anti-reflective 183 portion. Ultra-deep p-well region 174 is in contact with deep PD layer 1821. The doping concentration of the ultra-deep p-well region 174 is less than the doping concentration of the first sub-region 181. An ultra-deep p-well region 174 is formed from deep PD layer 1821 to the back side. The back surface is the first side 171 of the photoelectric conversion portion 170. That is, an extremely deep p-well region 174 is formed on the first side 171 of the photoelectric conversion portion 170. In addition, the separation layer 180 also extends to the back surface. This embodiment can further increase the full well capacity by increasing the effective photoactive voltage.
< Tenth embodiment >
Hereinafter, the solid-state imaging device 100H according to the tenth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 17 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to a tenth embodiment of the present invention. In comparison with the ninth embodiment, the deep trench isolation 173 of the present embodiment is buried in the extremely deep p-well region 174. The deep trench isolation 173 of this embodiment penetrates the very deep p-well region 174. The separation layer 180 extends to a deep PD layer 1821 of the photoelectric conversion portion 170. An ultra-deep p-well region 174 is formed from deep PD layer 1821 to the back side. The back surface is the first side 171 of the photoelectric conversion portion 170. This embodiment can further increase the full well capacity by increasing the effective photoactive voltage.
< Eleventh embodiment >
Hereinafter, the solid-state imaging device 100I according to the eleventh embodiment of the present invention will be described in detail with reference to the accompanying drawings. Fig. 18 is a simplified cross-sectional view showing an example of the configuration of a main portion in a pixel according to an eleventh embodiment of the present invention. In comparison with the tenth embodiment, the deep trench isolation 173 of the present embodiment is buried in the deep PD layer 1821. The deep trench isolation 173 of the present embodiment penetrates the deep PD layer 1821. The separation layer 180 extends to the shallow PD layer 1822 of the photoelectric conversion portion 170. An ultra-deep p-well region 174 is formed from deep PD layer 1821 to the back side. The back surface is the first side 171 of the photoelectric conversion portion 170. As shown in fig. 18, the depth of the ultra-deep p-well region 174 may be equal to or less than the first sub-region 181. The depth of the ultra-deep p-well region 174 refers to the thickness of the first sub-region 181 in a direction perpendicular to the normal to the first side 171. This embodiment can further increase the full well capacity by increasing the effective photoactive voltage.
< Twelfth embodiment >
Hereinafter, the solid-state imaging device 100J according to the twelfth embodiment of the present invention will be described in detail with reference to the drawings. Fig. 19 is a simplified cross-sectional view showing an example of the configuration of a main part in an apparatus according to a twelfth embodiment of the present invention. As shown in fig. 19, the solid-state imaging device 100 according to the twelfth embodiment of the present invention has a second integrated circuit chip 850.
Fig. 20 is a schematic diagram showing a solid-state imaging device 100J according to an embodiment of the present invention. First, a typical solid-state imaging device 100 may be described with reference to a in fig. 20. The typical solid-state imaging device 100J includes a pixel array, a control circuit, and a logic circuit for signal processing, all mounted on a single semiconductor chip. In general, an image sensor includes a pixel array and a control circuit. The pixel array may be front-side illuminated or back-side illuminated.
As shown in B in fig. 20, on the other hand, the solid-state imaging device 100 according to the embodiment of the present invention includes: a pixel array and a control circuit (control region) mounted on the first semiconductor chip portion; a logic circuit mounted on the second semiconductor chip portion, the logic circuit including a signal processing circuit for signal processing. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other, and a single semiconductor chip may be formed to provide the solid-state imaging device 100.
As shown in C in fig. 20, in the solid-state imaging device 100 according to the embodiment of the present invention, the pixel array may be mounted on the first semiconductor chip section. Further, a control circuit and a logic circuit including a signal processing circuit may be mounted on the second semiconductor chip portion. The first semiconductor chip portion and the second semiconductor chip portion may be electrically connected to each other, and a single semiconductor chip may be formed to provide the solid-state imaging device 100.
As shown in D in fig. 20, in the solid-state imaging device 100 according to the embodiment of the present invention, the pixel array is mounted on the first semiconductor chip section. Further, the memory circuit may be mounted on the second semiconductor chip portion. Then, a control circuit and a logic circuit including a signal processing circuit may be mounted on the third semiconductor chip portion. The first semiconductor chip portion and the second and third semiconductor chip portions may be electrically connected, and a single semiconductor chip or two semiconductor chips may be formed to provide the solid-state imaging device 100.
As shown by E in fig. 20, in the solid-state imaging device 100 according to the embodiment of the present invention, the pixel array may be mounted on the first semiconductor chip section. Further, the pixel circuit may be mounted on the second semiconductor chip portion. Then, a control circuit and a logic circuit including a signal processing circuit may be mounted on the third semiconductor chip portion. The first semiconductor chip portion and the second and third semiconductor chip portions may be electrically connected, and a single semiconductor chip or two semiconductor chips may be formed to provide the solid-state imaging device 100.
The solid-state imaging device 100 according to the embodiment of the present invention can be applied to both the front-side illumination type image sensor and the back-side illumination type image sensor.
Electronic device
Hereinafter, an electronic device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The solid-state imaging device 100 explained above may be applied as an imaging device to an electronic apparatus, for example, a digital camera, a video camera, a portable terminal, or a monitoring camera, a camera for a medical endoscope.
Fig. 21 is a block diagram of an electronic device according to an embodiment of the invention. As shown in fig. 21, the electronic apparatus 200A includes a lens 201A, an imaging element 202A, DSP circuit 203A, a frame memory 204A, a display unit 205A, a recording unit 206A, an operation unit 207A, and a power supply unit 208A. Further, in the electronic apparatus 200A, the DSP circuit 203A, the frame memory 204A, the display unit 205A, the recording unit 206A, the operation unit 207A, and the power supply unit 208A are connected to each other through the bus 209.
For example, the imaging element 202A corresponds to the solid-state imaging device 100. The DSP circuit 203A is a camera signal processing circuit for processing a signal supplied from the imaging element 202A. The DSP circuit 203A outputs image data obtained by processing a signal from the imaging element 202A. The frame memory 204A temporarily stores the image data processed by the DSP circuit 203A in units of frames. The display unit 205A includes, for example, a panel type display device such as a liquid crystal panel and an organic electroluminescence (Electro Luminescence, EL) panel, and displays a moving image or a still image imaged by the imaging element 202. The recording unit 206A records image data of a moving image or a still image imaged by the imaging element 202A into a recording medium such as a semiconductor memory or a hard disk. The operation unit 207A outputs operation instructions regarding various functions of the electronic apparatus 200A according to the operation of the user. The power supply unit 208A appropriately supplies various power supplies as operation power supplies of the DSP circuit 203A, the frame memory 204A, the display unit 205A, the recording unit 206A, and the operation unit 207A to these components as supply targets. Fig. 22 is an example of a technique of applying the image sensor of the present invention.
Method for manufacturing electronic device
Hereinafter, a method for manufacturing an embodiment of an electronic device according to the present invention will be described in detail with reference to the accompanying drawings. Fig. 7 is a flow chart of a method of forming the pixel sensor of fig. 5. As shown in fig. 7, a method for manufacturing an electronic device according to an embodiment of the present invention has the steps of: forming a pixel device region isolation structure in a semiconductor substrate; forming a deep photodiode well of a pixel sensor in a semiconductor substrate; forming a plurality of shallow photodiode wells in the pixel sensor well, wherein the plurality of shallow photodiode wells are divided by a vertically inserted intermediate depth p-well; forming a transfer transistor and a pixel device transistor on a front surface of a semiconductor substrate; forming floating diffusion nodes in the pixel well region between the plurality of photodetectors; forming an interconnection structure on the front surface of the semiconductor substrate; bonding the interconnect structure to the second integrated chip; forming a deep trench isolation structure in a semiconductor substrate; an anti-reflection layer is formed, a plurality of color filters are formed on the anti-reflection layer, a plurality of grid structures are formed between the color filters, and a plurality of microlenses are formed on the color filters.
The substrate comprises a semiconductor material, such as silicon or germanium. In some embodiments, the substrate may include at least one or more other photosensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium, antimony, semiconductor-on-insulator, or combinations thereof.
In some embodiments, the first subregion may have a doping concentration of between about 5 x 10 16 atoms/cm 3 and about 5 x 10 18 atoms/cm 3. In some embodiments, the separation layer may have a doping concentration of between about 5 x 10 16 atoms/cm 3 and about 5 x 10 18 atoms/cm 3. In some embodiments, the deep PD layer may have a doping concentration of between about 5 x 10 15 atoms/cm 3 and about 5 x 10 17 atoms/cm 3. In some embodiments, the peak doping concentration of the separation layer may be greater than the peak doping concentration of the deep PD layer.
[ Example ]
Next, examples of the present invention will be described. The condition in the example is one example of a condition employed for confirming the feasibility and effect of the present invention, but the present invention is not limited to this example of a condition. As long as the object of the present invention is achieved, the present invention may employ various conditions without departing from the gist of the present invention.
Fig. 8 is a simulation result of electrostatic potential distribution of a pixel center and full well capacity simulated by 3D process and device simulation according to one example of the present invention. In the device simulation, the pixel size was 1.0 μm. As shown in fig. 8, the simulation results clearly show that two shallow photodiode regions (shallow photodiode, SPD) are near the front side, and that the photodiode potential is smoothly connected from the SPD to one large Deep Photodiode (DPD). In addition, the simulation result shows that the capacity of the full well is improved by 35%.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary embodiments of the invention and should not be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims. The control device according to an embodiment of the invention may be a robot with hydraulic or electric actuators.
[ INDUSTRIAL APPLICABILITY ]
According to the present invention, a solid-state imaging device and an electronic apparatus capable of further improving the Full WELL CAPACITY (FWC) capacity can be provided. Therefore, the industrial applicability of the present invention is high.
[ Brief description of the reference numerals ]
A solid-state imaging device 100, a Photodiode (PD) 150, a semiconductor layer 160, a photoelectric conversion portion 170, a first side 171, a second side 172, a deep trench isolation 173, a plate portion 1731, an extremely deep p-well region 174, a separation layer 180, a first sub-region 181, an intermediate p-well portion 1811, a shallow intermediate p-well portion 1812, a second sub-region 182, a deep PD layer 1821, a shallow PD layer 1822, a color filter 250, a microlens 350, a first charge transfer gate device 450, a second charge transfer gate device 550, a third charge transfer gate device 650, a fourth charge transfer gate device 750, a Photodiode (PD) 150, a floating diffusion 300, a dual conversion device 400, a reset device 500, a source follower device 600, a row selection device 700, a current source 800, an imaging system 201, a control circuit 205, a pixel array 209, a readout circuit 210, a signal processing circuit 260, a pixel set 2091, an upper left sub-pixel 2092, a lower left sub-pixel 3, an upper right sub-pixel 4, a lower sub-pixel 185, a right sub-pixel 205, a 5 anti-reflection pixel portion 205A, a metal frame image element 209, a 2099, a power supply unit image element 209, a power supply unit 209, a power supply unit image cell unit 209, a power supply unit 209, a recording unit 209.
Claims (22)
1. A solid-state imaging device, characterized in that the solid-state imaging device comprises:
A semiconductor layer of a first conductivity type semiconductor;
A photoelectric conversion portion including a first side and a second side opposite to the first side, and being in contact with the semiconductor layer at the first side;
a charge transfer gate device electrically connected to the photoelectric conversion portion and transferring charges stored in the photoelectric conversion portion to a floating diffusion region,
Wherein the photoelectric conversion portion includes at least a first sub-region of the first conductivity type semiconductor and a second sub-region of a second conductivity type semiconductor different from the first conductivity type semiconductor,
On the first side of the photoelectric conversion portion, the first sub-region and the second sub-region are in contact with the semiconductor layer,
The thickness of the first sub-region in a direction perpendicular to the normal of the first side is smaller than the thickness of the second sub-region in a direction perpendicular to the normal of the first side,
The charge transfer gate device includes a first charge transfer gate device and a second charge transfer gate device.
2. The solid-state imaging device according to claim 1, wherein,
At least one cross-sectional area of the first sub-area parallel to the first side is larger than another cross-sectional area of the first sub-area parallel to the first side.
3. The solid-state imaging device according to claim 1 or 2, wherein,
The first sub-region includes an intermediate p-well portion,
A cross-sectional area of the intermediate P-well portion parallel to the first side is greater than an area of the first sub-region on the first side.
4. A solid-state imaging device according to claim 3, wherein,
The thickness of the intermediate p-well portion in a normal direction perpendicular to the first side is greater than 0 μm and less than or equal to 3.0 μm.
5. The solid-state imaging device according to any one of claims 1 to 4, characterized in that the solid-state imaging device further comprises:
A separation layer formed in a portion of the photoelectric conversion portion,
Wherein the separation layer is a separation layer of a first conductivity type semiconductor.
6. The solid-state imaging device according to claim 5, wherein,
At least one cross-sectional area of the separation layer parallel to the first side is greater than another cross-sectional area of the separation layer parallel to the first side.
7. The solid-state imaging device according to claim 5 or 6, wherein,
The separation layer is in contact with the semiconductor layer and includes a deep p-well portion,
A cross-sectional area of the deep P-well portion parallel to the first side is larger than an area of a contact portion of the separation layer with the semiconductor layer.
8. The solid-state imaging device according to any one of claims 5 to 7, wherein,
At least one region of the separation layer has a doping concentration different from other regions of the separation layer.
9. The solid-state imaging device according to any one of claims 5 to 8, characterized in that the solid-state imaging device further comprises:
And a deep trench isolation portion buried in the separation layer from a side of the second side of the photoelectric conversion portion.
10. The solid-state imaging device according to claim 9, wherein,
The deep trench isolation portion is buried within the semiconductor layer.
11. The solid-state imaging device according to claim 9 or 10, wherein,
The deep trench isolation portion is buried within the second sub-region.
12. The solid-state imaging device according to any one of claims 9 to 11, wherein,
The deep trench isolation portion is a junction isolation or an STI isolation.
13. The solid-state imaging device according to any one of claims 1 to 12, wherein,
The first charge transfer gate device and the second charge transfer gate device are electrically connected on opposite sides of the semiconductor layer from the photoelectric conversion portion.
14. The solid-state imaging device according to any one of claims 1 to 13, wherein,
At least one region of the first subregion is doped at a different concentration than other regions of the first subregion.
15. The solid-state imaging device according to any one of claims 1 to 14, wherein,
At least one region of the second subregion is doped at a different concentration than other regions of the second subregion.
16. The solid-state imaging device according to any one of claims 1 to 15, wherein,
The first charge transfer gate and the second charge transfer gate have embedded portions in the semiconductor layer.
17. The solid-state imaging device according to any one of claims 1 to 16, characterized in that the solid-state imaging device further comprises:
A second separation layer that is in contact with the second side of the photoelectric conversion portion, and that is a separation layer of the first conductivity type semiconductor.
18. The solid-state imaging device according to any one of claims 1 to 17, wherein,
At least one cross-sectional area of the second sub-area parallel to the first side is simply connected.
19. The solid-state imaging device according to any one of claims 1 to 18, characterized in that the solid-state imaging device further comprises:
a circuit, the circuit comprising:
A floating diffusion electrically connected to the first charge transfer gate device and the second charge transfer gate device,
A double conversion device electrically connected to the floating diffusion,
And a reset device electrically connected to the floating diffusion through the double conversion device.
20. The solid-state imaging device according to any one of claims 1 to 19, wherein,
The circuit also includes a source follower device electrically connected to the floating diffusion and a row select device electrically connected to the source follower device.
21. The solid-state imaging device according to any one of claims 1 to 20, wherein,
At the first side of the photoelectric conversion portion, the second sub-region includes at least a first region surface and a second region surface placed apart from the first region surface, at least a portion of the first sub-region is in contact with the first region surface, and at least a portion of the first sub-region is in contact with the second region surface,
The first charge transfer gate device is disposed at least in the first region surface and the second charge transfer gate device is disposed at least in the second region surface.
22. An electronic device, the electronic device comprising:
the solid-state imaging device according to any one of claims 1 to 21.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2021/131949 WO2023087289A1 (en) | 2021-11-19 | 2021-11-19 | Solid-state imaging device and electronic apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117957659A true CN117957659A (en) | 2024-04-30 |
Family
ID=86396033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180102386.5A Pending CN117957659A (en) | 2021-11-19 | 2021-11-19 | Solid-state imaging device and electronic apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117957659A (en) |
| WO (1) | WO2023087289A1 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5369505B2 (en) * | 2008-06-09 | 2013-12-18 | ソニー株式会社 | Solid-state imaging device and electronic apparatus |
| JP7121468B2 (en) * | 2017-02-24 | 2022-08-18 | ブリルニクス シンガポール プライベート リミテッド | Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic device |
| WO2018207340A1 (en) * | 2017-05-12 | 2018-11-15 | オリンパス株式会社 | Solid-state imaging device |
| JP7032902B2 (en) * | 2017-10-05 | 2022-03-09 | ブリルニクス シンガポール プライベート リミテッド | Solid-state image sensor, manufacturing method of solid-state image sensor, and electronic equipment |
| JP6987603B2 (en) * | 2017-10-26 | 2022-01-05 | ブリルニクス シンガポール プライベート リミテッド | Solid-state image sensor, solid-state image sensor driving method, and electronic equipment |
| US20200027910A1 (en) * | 2018-07-17 | 2020-01-23 | Brillnics, Inc. | Solid-state imaging device, method for fabricating solid-state imaging device, and electronic apparatus |
| JP2020181932A (en) * | 2019-04-26 | 2020-11-05 | ブリルニクス インク | Solid-state image sensor, manufacturing method of solid-state image sensor, and electronic device |
-
2021
- 2021-11-19 CN CN202180102386.5A patent/CN117957659A/en active Pending
- 2021-11-19 WO PCT/CN2021/131949 patent/WO2023087289A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023087289A1 (en) | 2023-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11322535B2 (en) | Solid-state imaging device and camera | |
| US8692303B2 (en) | Solid-state imaging device, electronic device, and manufacturing method for solid-state imaging device | |
| US8994862B2 (en) | Photoelectric conversion device and image-pickup apparatus | |
| JP7121468B2 (en) | Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic device | |
| KR102499590B1 (en) | Solid state imaging device and manufacturing method therefor, and electronic apparatus | |
| KR100820520B1 (en) | Solid state imaging apparatus | |
| US8089543B2 (en) | Solid-state image pickup element and solid-state image pickup device | |
| JP2009253149A (en) | Photoelectric conversion device and imaging system using same | |
| TWI725484B (en) | Solid-state imaging device, method for fabricating solid-state imaging device, and electronic apparatus | |
| WO2010151299A1 (en) | Imager with biased material and backside well | |
| US20120104523A1 (en) | Solid-state imaging device manufacturing method of solid-state imaging device, and electronic apparatus | |
| CN116057953A (en) | Solid-state image pickup element and electronic apparatus | |
| JP2013131516A (en) | Solid-state imaging device, method of manufacturing the same, and electronic equipment | |
| WO2023087289A1 (en) | Solid-state imaging device and electronic apparatus | |
| US20200027910A1 (en) | Solid-state imaging device, method for fabricating solid-state imaging device, and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |