WO2023087289A1

WO2023087289A1 - Solid-state imaging device and electronic apparatus

Info

Publication number: WO2023087289A1
Application number: PCT/CN2021/131949
Authority: WO
Inventors: Seiji Takahashi; Zhijian Huang
Original assignee: Huawei Technologies Co.,Ltd.
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2023-05-25

Abstract

A solid-state imaging device (100) comprising: a semiconductor layer (160) of a first conductivity type semiconductor; a photoelectric conversion part (170) comprising a first side (171) and a second side (172) opposite to the first side (171), and being formed in contact with the semiconductor layer (160) at the first side (171); and a charge transfer gate device electrically connected to the photoelectric conversion part (170), and transferring charge stored in the photoelectric conversion part (170) to floating diffusion region (300), wherein the photoelectric conversion part (170) at least comprises a first sub-area (181) of the first conductivity type semiconductor and a second sub-area (182) of a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor, wherein on the first side (171) of the photoelectric conversion part (170), the first sub-area (181) and the second sub-area (182) contacts with the semiconductor layer (160), wherein thickness of the first sub-area (181) in a direction perpendicular to a normal line of the first side (171) is smaller than thickness of the second sub-area (182) in a direction perpendicular to a normal line of the first side (171), and wherein the charge transfer gate device comprises a first charge transfer gate device (450) and a second charge transfer gate device (550).

Description

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

Technical Field

The present invention relates to a solid-state imaging device and an electronic apparatus.

[Related Art]

As solid-state imaging devices (image sensors) using photoelectric conversion elements detecting electromagnetic radiation and generating a charge, CCD (charge coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors have been put into practical use. CCD image sensors and CMOS image sensors have been widely applied as parts of digital cameras, video cameras, monitoring cameras, medical endoscopes, personal computers (PC) , mobile phones and other portable terminals (mobile devices) and other various types of electronic apparatuses.

CCD image sensors and CMOS image sensors use photodiodes for photoelectric conversion elements, but differ in the methods of transferring the photoelectrically converted signal charges. In a CCD image sensor, a signal charges are transferred to an output part by a vertical transfer part (vertical CCD, VCCD) and horizontal transfer part (horizontal CCD, HCCD) then converted to electrical signals and amplified. Contrary to this, in a CMOS image sensor, charges which are converted for each pixel including a photodiode are amplified and are output as a read-out signal.

When the pixel size is small, full well capacity becomes small due to limited area. Lower full well capacity induces low dynamic range and low signal to noise ratio SNR under high light problems.

Patent Document 1 discloses a solid-state imaging device comprising a substrate which has a first substrate side and a second substrate side on the side opposite to the first substrate side, a photoelectric conversion part which includes a first conductivity type semiconductor layer formed so that it is buried in the substrate and has a photoelectric conversion function for received light and a charge accumulation function, a second conductivity type separation layer which is formed in a side portion of the first conductivity type semiconductor layer in the photoelectric conversion part, and one charge transfer gate part capable of transferring a charge accumulated in the photoelectric conversion part, wherein the photoelectric conversion part, in at least a portion of the first conductivity type semiconductor layer, includes at least one second-conductivity type semiconductor layer forming at least one sub-area in a direction perpendicular to a normal line of the substrate and having a junction capacitance component together with the first conductivity type semiconductor layer, and the one charge transfer gate part can transfer a charge accumulated in the sub-area in the photoelectric conversion part.

[Prior Art Document]

[Patent Documents]

[Patent Document 1] Japanese Patent Publication No. 2018-139269A

[Problems to be Solved by the Invention]

However, Patent Document 1 keeps n-type layer between a second substrate sideand second-conductivity type semiconductor layer, and the second substrate sideand second-conductivity type semiconductor layer are p-typelayer. Therefore, there is limitations to arrange the second-conductivity type semiconductor layer near a charge transfer gate device side in photodiode (PD) , leading that FWC (full well capacity) improvement is lower.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device and electronic apparatus capable of further improving FWC (full well capacity) .

[Means for Solving the Problem]

The present invention has been made based on the above findings, and the gist is as follows.

[1] A solid-state imaging device including:

a semiconductor layer of a first conductivity type semiconductor;

a photoelectric conversion part comprising a first side and a second side opposite to the first side, and being formed in contact with the semiconductor layer at the first side; and

a charge transfer gate device electrically connected to the photoelectric conversion part, and transferring charge stored in the photoelectric conversion part to floating diffusion region,

wherein the photoelectric conversion part at least includes a first sub-area of the first conductivity type semiconductor and a second sub-area of a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor,

wherein on the first side of the photoelectric conversion part, the first sub-area and the second sub-area contact with the semiconductor layer,

wherein thickness of the first sub-area in a direction perpendicular to a normal line of the first side is smaller than thickness of the second sub-area in a direction perpendicular to a normal line of the first side, and

wherein the charge transfer gate device comprises a first charge transfer gate device and a second charge transfer gate device.

[2] The solid-state imaging device according to [1] ,

wherein at least one cross sectional area of the first sub-area parallel to the first side is larger than another cross sectional area of the first sub-area parallel to the first side.

[3] The solid-state imaging device according to [1] or [2] ,

wherein the first sub-area includes a middle p-well portion, and

a cross sectional area of the middle p-well portion parallel to the first side is larger than area of the first sub-area in the first side.

[4] The solid-state imaging device according to [3] ,

wherein a thickness of the middle p-well portion in a direction perpendicular to a normal line of the first side is more than 0 and 3.0μm or less.

[5] The solid-state imaging device according to any one of [1] to [4] , further comprising:

a separation layer formed in a said portion of the photoelectric conversion part,

wherein the separation layer is of a first conductivity type semiconductor.

[6] The solid-state imaging device according to [5] ,

wherein at least one cross sectional area of the separation layer parallel to the first side is larger than another cross sectional area of the separation layer parallel to the first side.

[7] The solid-state imaging device according to [5] or [6] ,

wherein the separation layer is formed in contact with the semiconductor layer, and comprises a deep p-well portion, and

a cross sectional area of the deep p-well portion parallel to the first side is larger than an area at a portion where the separation layer contacts with the semiconductor layer.

[8] The solid-state imaging device according to any one of [5] to [7] ,

wherein at least one area of the separation layer differs in doping concentration from the other areas of the separation layer.

[9] The solid-state imaging device according to any one of [5] to [8] , further comprising:

a deep trench isolation portion buried inside the separation layer from a side of the second side of a photoelectric conversion part.

[10] The solid-state imaging device according to [9] ,

wherein the deep trench isolation portion is buried inside the semiconductor layer.

[11] The solid-state imaging device according to [9] or [10] ,

wherein the deep trench isolation portion is buried inside the second sub-area.

[12] The solid-state imaging device according to any one of [9] to [11] ,

wherein the deep trench isolation portion is junction isolation or STI isolation.

[13] The solid-state imaging device according to any one of [1] to [12] ,

wherein the first charge transfer gate device and the second charge transfer gate device electrically connect at the opposite side of the semiconductor layer from the photoelectric conversion part.

[14] The solid-state imaging device according to any one of [1] to [13] ,

wherein at least one area of the first sub-area differs in doping concentration from the other areas of the first sub-area.

[15] The solid-state imaging device according to any one of [1] to [14] ,

wherein at least one area of the second sub-area differs in doping concentration from the other areas of the second sub-area.

[16] The solid-state imaging device according to any one of [1] to [15] ,

wherein the first charge transfer gate and the second charge transfer gate have an embedded portion in the semiconductor layer.

[17] The solid-state imaging device according to any one of [1] to [16] , further comprising:

a second separation layer being formed in contact with the second side of the photoelectric conversion part, and being of a first conductivity type semiconductor.

[18] The solid-state imaging device according to any one of [1] to [17] ,

wherein at least one cross sectional area of the second sub-area parallel to the first side is simply connected.

[19] The solid-state imaging device according to any one of [1] to [18] , further comprising:

a circuit including;

a floating diffusion electrically connected to the first charge transfer gate device and the second charge transfer gate device,

a dual conversion device electrically connected to the floating diffusion, and

a reset device electrically connected to the floating diffusion through the dual conversion device.

[20] The solid-state imaging device according to any one of [1] to [19] ,

wherein the circuit further includes a source follower device electrically connected to the floating diffusion, and a row-select device electrically connected to the source follower device.

[21] The solid-state imaging device according to any one of [1] to [20] ,

wherein on the first side of the photoelectric conversion part, the second sub-area at least comprises a first area surface and a second area surface placed apart from the first area surface, at least part of the first sub-area contacts with the first area surface, and at least part of the first sub-area contacts with the second area surface, and

wherein the first charge transfer gate device disposed in at least the first area surface, and the second charge transfer gate device disposed in at least the second area surface.

[22] An electronic apparatus including:

a solid-state imaging device according to any one of [1] to [21] .

[Effects of the Invention]

As described above, according to the present invention it is possible to provide a solid-state imaging device and electronic apparatus capable of further improving FWC (full well capacity) .

[Brief Description of the Drawings]

FIG. 1 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a pixel according to the first embodiment of the present invention.

FIG. 3 is a block diagram of an imaging systemaccording to the second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a solid-state imaging device according to the second embodiment of the present invention.

FIG. 5 is a top view of an example circuit layout according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view of the example of the circuit layout along line A-A' of FIG. 5.

FIG. 7 isa flowchart of a method for forming pixel sensor of FIG. 5.

FIG. 8 iselectrostatic potential distribution at the center of pixel simulated by 3D process and device simulation and the simulation result of full well capacity according to an example of the present invention.

FIG. 9 is a top view of an example circuit layout according to the third embodiment of the present invention.

FIG. 10 isa circuit diagram showing an example of a solid-state imaging device according to the third embodiment of the present invention.

FIG. 11 isa top view of an example circuit layout according to the forth embodiment of the present invention.

FIG. 12 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the fifth embodiment of the present invention.

FIG. 13 isa top view of an example circuit layout according to the sixth embodiment of the present invention.

FIG. 14 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the seventh embodiment of the present invention.

FIG. 15 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the eighth embodiment of the present invention.

FIG. 16 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the ninth embodiment of the present invention.

FIG. 17 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the tenth embodiment of the present invention.

FIG. 18 isa simplified cross-sectional view showing an example of the configuration of principal parts in a solid-state imaging device according to the eleventh embodiment of the present invention.

FIG. 19 isa simplified cross-sectional view showing an example of the configuration of principal parts in the apparatus according to the twelfth embodiment of the present invention.

FIG. 20 isschematic diagrams illustrating the solid-state imaging device according tothe embodiment of the present invention.

FIG. 21 is a block diagram of electronic apparatus according to the embodiment of the present invention.

FIG. 22 isexamples of technologies to which the image sensor of the present invention is applied

[Embodiments of the Invention]

Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings. In addition, in this specification and the drawings, like constituent elements having substantially the same function and configuration are denoted by like reference numerals, and redundant description will be omitted.

<<< Solid-state imaging device >>>

First, a solid-state imaging device 100 according toan embodiment of the present invention will be described in detail. A solid-state imaging device 100 according to this embodiment of the present invention includes the following features: a semiconductor layer 160 of a first conductivity type semiconductor; a photoelectric conversion part 170 comprising a first side 171 and a second side 172 opposite to the first side 171, and being formed in contact with the semiconductor layer 160 at the first side 171; and a charge transfer gate device electrically connected to the photoelectric conversion part 170, and transferring charge stored in the photoelectric conversion part 170 to a floating diffusion 300 region region, wherein the photoelectric conversion part 170 at least includes a first sub-area 181 of the first conductivity type semiconductor and a second sub-area 182 of a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor, wherein on the first side 171 of the photoelectric conversion part 170, the second sub-area 182 at least comprises a first area surface and a second area surface placed apart from the first area surface, at least a part of the first sub-area 181 makes contact with the first area surface, and at least a part of the first sub-area 181 makes contact with the second area surface, wherein the thickness of the first sub-area 181 in a direction perpendicular to a normal line of the first side 171 is smaller than the thickness of the second sub-area 182 in a direction perpendicular to a normal line of the first side 171, and wherein the charge transfer gate device comprises a first charge transfer gate device 450 and a second charge transfer gate device 550, the first charge transfer gate device 450 disposed in at least the first area surface, and the second charge transfer gate device 550 disposed in at least the second area surface.

<< First embodiment >>

FIG. 1 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to first embodiment of the present invention. As shown in FIG. 1, a solid-state imaging device 100 according to the first embodiment of the present invention includes a photodiode (PD) 150, a first charge transfer gate device 450 and a second charge transfer gate device 550. The first charge transfer gate device 450 and the second charge transfer gate device 550 are electrically connected to the photodiode (PD) .

< Photodiode (PD) >

As shown in FIG. 1, the photodiode (PD) 150 includes a semiconductor layer 160, a photoelectric conversion part 170, a separation layer 180, a color filter 250, a micro lens 350, and a deep trench isolation 173 portion. The photoelectric conversion part 170 includes a first side 171 and a second side 172 opposite to the first side 171. The photoelectric conversion part 170 is formed in contact with the semiconductor layer 160 at the first side 171. The separation layer 180 is formed in a portion of the photoelectric conversion part 170. The deep trench isolation 173 portion is buried inside the separation layer 180 from a side of the second side 172 of the photoelectric conversion part 170. The color filter 250 is formed in contact with photoelectric conversion part 170 at the second side 172. The micro lens 350 is formed in contact with the color filter 250. The photodiode (PD) 150 is a pinned photodiode (PPD) in the present embodiment.

(Semiconductor layer)

As shown in FIG. 1, the semiconductor layer 160 is the first conductivity type semiconductor. The first conductivity type semiconductor can be p-type or n-type semiconductor. In FIG. 1, the semiconductor layer 160 is a p-type semiconductor in the present embodiment. The semiconductor layer 160 is joined with the photoelectric conversion part 170 and the separation layer 180. The doping concentration of the semiconductor layer 160 is preferably larger than that of the separation layer 180.

(Photoelectric conversion part)

As shown in FIG. 1, the photoelectric conversion part 170 includes a first sub-area 181 of afirst conductivity type semiconductor and a second sub-area 182 of a second conductivity type semiconductor. The second conductivity type semiconductor is different from the first conductivity type semiconductor. As shown in FIG. 1, the first sub-area 181 is a p-type semiconductor, and the second sub-area 182 is an n-type semiconductor. The second sub-area 182 has a deep PD layer 1821 and a shallow PD layer 1822. The shallow PD layer 1822 is divided into two area by the first sub-area 181. That is, the two areas of the shallow PD layer 1822 do not make contact with each other. The doping concentration of the shallow PD layer 1822 is preferably smaller than that of the separation layer 180.

On the first side 171 of the photoelectric conversion part 170, the second sub-area 182 includes a first area surface (surface ‘A’ in FIG. 1) and a second area surface (surface ‘B’ in FIG. 1) placed apart from the first area surface. That is, the first area surface and the second area surface do not make contact with each other. The first area surface and the second area surface are surfaces where the shallow PD layer 1822 makes contact with the semiconductor layer 160. At least part of the first sub-area 181 contacts with the first area surface, and at least part of the first sub-area 181 makes contact with the second area surface. That is, the first area surface and the second area surface are divided by the first sub-area 181. As shown in FIG. 1, the first sub-area 181 makes contact with the semiconductor layer 160. The deep PD layer 1821 is simply connected. That is, the deep PD layer 1821 is formed as only one area, and the deep PD layer 1821 is not divided into two or more areas.

The first sub-area 181 makes contact with the second sub-area 182. The first sub-area 181 makes contact with the shallow PD layer 1822 and the deep PD layer 1821. Joint parts of the first sub-area 181 and the second sub-area 182 form pn junctions. The pn junctions have junction capacitance. As shown in FIG. 1, there are at least two pn junctions between the first sub-area 181 and the shallow PD layer 1822. In addition, there is one pn junction between the first sub-area 181 and the deep PD layer 1821. The shallow PD layer 1822 makes contact with the separation layer 180. The structure of the second sub-area 182 can be a single layer structure as well. Further, the structure of the second sub-area 182 can be a multilayer structure of three or more layers.

Joint parts of the shallow PD layer 1822 and the separation layer 180 form pn junctions. As shown in FIG. 1, there are at least two pn junctions between the separation layer 180 and the shallow PD layer 1822. The deep PD layer 1821 makes contact with the separation layer 180. Joint parts of the deep PD layer 1821 and the separation layer 180 form pn junctions. As show in FIG. 1, there are at least two pn junctions between the separation layer 180 and the deep PD layer 1821. The deep PD layer 1821 makes contact with the both two parts of the shallow PD which divided by the first sub-area 181. The deep PD layer 1821 is electrically connected to the both two parts of the shallow PD which is divided by the first sub-area 181.

The thickness of the first sub-area 181 in a direction perpendicular to a normal line of the first side 171 of the photoelectric conversion part 170 is smaller than the thickness of the second sub-area 182 in a direction perpendicular to a normal line of the first side 171 of the photoelectric conversion part 170. That is, the first sub-area 181 is not exposed from the second side 172 of the photoelectric conversion part 170.

(Separation layer)

In the present embodiment, the separation layer 180 is formed in the portion of the photoelectric conversion part 170. The separation layer of 180 the said portion of covers the photoelectric conversion part 170 so that the photoelectric conversion do not make contact with the other parts except for the separation layer 180. The separation layer 180 covers the deep PD layer 1821 and the shallow PD layer 1822. The separation layer 180 is a p-type semiconductor.

(Deep trench isolation portion)

As shown in FIG. 1, the deep trench isolation 173 portion is buried inside the separation layer 180 from a side of the second side 172 of a photoelectric conversion part 170. The deep trench isolation 173 portion can be a physical isolation portion. The height of the deep trench isolation 173 portion is larger than that of the deep PD layer 1821 in a direction parallelto a normal line of the first side 171. The separation layer 180 is formed between the deep trench isolation 173 portion and the photoelectric conversion part 170. The deep trench isolation 173 portion overlaps the first sub-area 181 of the photoelectric conversion part 170 in a direction perpendicular to a normal line of the first side 171. The deep trench isolation 173 portion overlaps the shallow PD layer 1822 of the photoelectric conversion part 170 in a direction perpendicular to a normal line of the first side 171.

(Color filter)

The types of the color filter 250 is not limited, and any known color filter 250 can be used. The color filter 250 can include red filter, green filter and blue filter.

(Micro lens)

The types of the micro lens 350 is not limited, and any known micro lens 350 can be used.

In the present embodiment, the solid-state imaging device 100 includes the first charge transfer gate device 450 and the second charge transfer gate device 550. That is, the solid-state imaging device 100 includes two charge transfer gate devices. The first charge transfer gate device 450 and the second charge transfer gate device 550 transfer charge stored in the photoelectric conversion part 170 are connected to a floating diffusion 300 region. The first charge transfer gate device 450 and the second charge transfer gate device 550 do not transfer charge which is stored in other pixels of the solid-state imaging device 100. The first charge transfer gate device 450 is electrically connected to one part of the shallow PD layer 1822. The second charge transfer gate device 550 is electrically connected to the other part of the shallow PD layer 1822. The first charge transfer gate device 450 transfers charges which is passed through the first area surface of the shallow PD layer 1822. The second charge transfer gate device 550 transfers charges which is passed through the second area surface of the shallow PD layer 1822. The first charge transfer gate device 450 can be configured to also transfer charge which is passed through the second area surface of the shallow PD layer 1822. The second charge transfer gate device 550 can be configured to also transfer charge which is passed through the first area surface of the shallow PD layer 1822. The first charge transfer gate and the second charge transfer gate canhave an embedded portion in the semiconductor layer 160. The first charge transfer gate and the second charge transfer gate can be vertical transfer gate.

< Circuit >

FIG. 2 is a circuit diagram showing an example of a pixel according to the first embodiment of the present invention. As shown in FIG. 2, the pixel of the solid-state imaging device 100 according to the first embodiment of the present invention includes the photodiode (PD) 150, the first charge transfer gate device 450, the second charge transfer gate device 550, a floating diffusion 300 region, a dual conversion device 400, a reset device 500, a source follower device 600, a row-select device 700 and a current source 800. The floating diffusion 300 region is electrically connected to the first charge transfer gate device 450 and the second charge transfer gate device 550. The dual conversion device 400 is electrically connected to the floating diffusion 300 region. The reset device 500 is electrically connected to the floating diffusion 300 region through the dual conversion device 400. The source follower device 600 is electrically connected to the floating diffusion 300 region. The row-select device 700 is electrically connected to the source follower device 600. Junction isolation or STI isolation can be used for dividing device elements of a solid-state imaging device 100.

(Photodiode (PD) )

The photodiode (PD) 150 generates and accumulates a signal charge (here, electrons) in an amount in accordance with the incident electromagnetic radiation quantity. Below, an explanation will be given of a case where the signal charge includes electrons and each transistor is an n-type transistor, but the signal charge can be holes and some of transistor may also be a p-type transistor. Further, the present embodiment is effective also in the case where each transistor is shared among a plurality of photodiodes and the case where a three-transistor (3Tr) pixel not having a selection transistor is employed.

As the photodiode (PD) 150, a pinned photodiode (PPD) may be used. On the substrate surface forming the photodiode (PD) 150, there is a surface level due to dangling bonds or other defects, therefore, a large charge (dark current) is generated by the heat energy, so a correct signal can no longer be read out. In a pinned photodiode (PPD) , a charge accumulation part of the photodiode (PD) 150 is buried in the substrate, so it ispossible to reduce entry of dark current into the signal.

However, in the case where the size is relatively large and the longitudinal and lateral aspect ratio is relatively large, for example, the case of a pixel of about 3-μm square pixel, the accumulated charge is mainly limited to the pn-junction capacitance in the vertical direction (normal line direction of substrate: depth direction of substrate) at a location close to the photodiode (PD) 150 part (photoelectric conversion part 170) , so it is difficult to efficiently increase the storage capacity.

Therefore, in the solid-state imaging device 100 according to the present embodiment, in the photoelectric conversion part 170 of the pinned photodiode (PPD) , in order to increase the storage capacity, a plurality of sub-areas are provided by dividing the photoelectric conversion layer (for example n layer) so that there are a plurality of pn junction parts in the direction (horizontal direction) perpendicular to the normal line of the semiconductor layer 160 inside the pixel. The other configuration of the photodiode (PD) 150 is same as that of the photodiode (PD) 150 in the solid-state imaging device 100 described above.

(Charge transfer gate device)

The solid-state imaging device 100 according to the present embodiment employs a configuration capable of reading out the charges accumulated in the photoelectric conversion part 170 by the two charge transfer gate device including the transfer transistor TG-Tr. Thereby, in the solid-state imaging device 100 according to the present embodiment, it ispossible to increase the full well capacity (FWC) while reducing noise and increasing sensitivity. Therefore, it is possible to expand the dynamic range without degrading the optical characteristics.

The first charge transfer gate device 450 and the second charge transfer gate device 550 can be constitutedby a transfer transistor TG-Tr. The first charge transfer gate device 450 and the second charge transfer gate device 550 can be constituted by including an n layer forming a floating diffusion 300 (FD) region to which the charges accumulated in the storage capacity parts formed in the sub-areas in the photoelectric conversion part 170 are transferred, a p layer which is formed between the semiconductor layer 160 and the n layer forming the floating diffusion 300 (FD) region, and a gate electrode (GT) which is formed through an insulation film on at least the semiconductor layer 160.

The two transfer transistors TG-Tr constituting the first charge transfer gate device 450 and second charge transfer gate device 550 are connected between the photodiode (PD) 150 and the floating diffusion 300 (FD) region. The two transfer transistors TG-Tr are controlled through a control signal TG. The two transfer transistors TG-Tr are selected in a period where the control signal TG is at a high level (H) and becomes a conductive state and transfers the charge (electrons) which is photoelectrically converted and accumulated in the photodiode (PD) 150 to the floating diffusion 300 (FD) region.

(Floating diffusion)

The floating diffusion 300 region can be an n-type semiconductor. The floating diffusion 300 (FD) region can be electrically connected to a variable capacity part which is connected to a floating diffusion 300 (FD) region and can change the capacity of the floating diffusion 300 (FD) region in response to a capacity changing signal CS.

(Dual conversion device)

Adual conversion device 400 (DCG) can be connected between a reset device 500 (RST) and the floating diffusion 300 (FD) region, in order to realize high dynamic range by combining two types of gains. The dual conversion device 400 (DCG) can be constitutedby a MOS transistor. In some embodiment, dual conversion device 400 can be removed.

(Reset device)

A reset device 500 (RST) selectively resets an electrical charge accumulated in the FD. The reset device 500 (RST) can be constituted by a MOS transistor.

(Source follower device)

The source follower device 600 (SF) can be connected between the row-select device 700 (SEL) and the floating diffusion 300 (FD) region. The source follower device 600 (SF) can be constituted by a MOStransistoror a JFET.

(Row-select device)

The row-select device 700 (SEL) can be connected between the source follower device 600 (SF) and the current source 800. The row-select device 700 (SEL) can be constituted by a MOStransistor.

(Current source)

The current source 800 can be connected between the row-select device 700 (SEL) and a ground. As the current source 800, a known current source 800 can be used.

(Substrate)

Elements of the solid-state imaging device 100 can be arranged on a substrate (not shown in the FIGs. ) . The semiconductor substrate may consist of semiconductor material such as silicon or germanium. In some embodiments, the substrate may consist of at least one or more of other radiation sensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium, antimonide, semiconductor on insulator or combinations thereof.

In general, an n region (the second sub-area 182) of the photodiode must be completely depleted. The depletion potential (voltage) must be sufficiently low for complete charge transfer. The maximum depletion potential must be in the vicinity of the first charge transfer gate device 450 and the second charge transfer gate device 550. In order to make the storage capacity maximum, it is necessary to make the concentration of the second sub-area 182 of the photoelectric conversion part 170 maximum after satisfying the above condition of space charge density. However, if the quantity of impurities in the second sub-area 182 of the photoelectric conversion part 170 is increased, the photodiode (PD) 150 potential becomes deeper and the readout voltage rises. Therefore there is a limit to the concentration of the second sub-area 182.

Therefore, by providing a p region (the first sub-area 181) at the n region (the second sub-area 182) having a depletion layer distance Wd shorter than the pixel pitch in the direction X perpendicular to anormal line of the semiconductor layer 160 in the photoelectric conversion part 170, it is possible to increase the storage capacity in the photoelectric conversion part 170 having a lower depletion voltage Vapp. Therefore the saturation output at the time of same readout voltage is improved.

Moreover, full well capacity (FWC) is one of the important key performance indicators for solid-state imaging device 100s. Lower full well capacity induces low dynamic range (DR) and low signal to noise ratio (SNR) undera high intensity high light. Therefore, higher full well capacity is always preferred. However, other key performance indicators are competing with the full well capacity. Increasing full well capacity as much as possible with a limited area is strongly required.

According to the present embodiment of the present invention, the deep part of the photodiode (DPD) is one per one pixel, and there is a plurality of the photodiode (SPD) regions locatedfrom the middle to the device side is a plural, which is realized by vertically placing the p-type isolation layer as shown in FIG. 1. It extends from the photosensitive surface at the device side to an intermediate depth of the photodiode. This structure can enhance pn junction capacitance in the photodiode, whereby, the full well capacity will increase. In this case, the subdivided shallow photodiode (SPD) should have a separated transfer gate, whose charge transfer capability is sufficiently high, and full well capacity (FWC) is further improved. The pixel circuit is also shown in FIG. 2.

In addition, according to the present embodiment of the present invention, the first sub-area 181 of the photoelectric conversion part 170 makes contact with the semiconductor layer 160, and the semiconductor type of the semiconductor layer 160 is the same as a semiconductor type of the first sub-area 181 of the photoelectric conversion part 170. Therefore, it is possible to prevent that the inserted vertical p-type layer from floating or the resistance between the p-type layer and p-well pick up from being too high. Thereby, the pn junction capacitance becomes higher and full well capacity (FWC) improvement is higher.

<< Second embodiment >>

< Imaging system >

Hereinafter, a second embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 3 is a block diagram of an imaging system 201 according to the second embodiment of the present invention. As shown in the FIG. 3, the imaging system 201 includes a control circuit 205, a pixel array 209, a readout circuit 210, and a signal processing circuit 206. The pixel array 209 is a two-dimensional array of pixels. Each pixel may be an imaging device as shown in FIG. 2. The pixels are arranged in rows (R1 to Ry) and columns (C1 to Cx) to obtain image data of a subject. The control circuit 205 controls the pixel array 209, for example, generates a shutter signal. The image data is readout by the readout circuit 210 via bit lines and sent to the signal processing circuit 206.

In the present embodiment, the imaging system 201 is, for example, constituted by a CMOS image sensor 201A. In the present embodiment, the imaging system 201 include the solid-state imaging device 100 according to the first embodiment. In addition, in the present embodiment, the solid-state imaging device 100 has the pixels arranged in a matrix in the pixel array 209 as photoelectric conversion elements. Photoelectric conversion elements are the photoelectric conversion part 170 in the present embodiment. Each of the pixels is formed by a photodiode (PD) 150. The photodiode is a pinned photodiode (PPD) in the present embodiment. The constitution of the photodiode (PD) 150 can be the same as that ofthe photodiode (PD) 150 in the first embodiment of the present invention.

For example, each pixel in the CMOS image sensor 201A can be constituted by including as active elements, for one photodiode, four elements of a transfer element including a transfer transistor, a reset element including a reset transistor, a source follower element (amplification element) including a source follower transistor, and a selection element including a selection transistor. Further, each pixel can be provided with an overflow gate (overflow transistor) for discharging an overflow charge overflowing from the photodiode in an accumulation period of the photodiode. In addition, each pixel can be provided with a dual conversion device 400 (DCG) .

The transfer transistor can be connected between the photodiode and an output node including a floating diffusion 300 region layer (FD) . The transfer transistor can be held in a non-conductive state in the charge accumulation period of the photodiode. In the transfer period transferring the accumulated charges in the photodiode to the floating diffusion 300 region, a control signal is supplied to the gate whereby it is held in a conductive state and transfers the charges photoelectrically converted in the photodiode to the floating diffusion 300 (FD) region.

The reset transistor is connected between a power supply line and the floating diffusion 300 (FD) region. The reset transistor, when given a reset-use control signal at its gate, resets the potential of the floating diffusion 300 (FD) region to the potential of the power supply line.

The floating diffusion 300 (FD) region is connected to the gate of the source follower transistor. The source follower transistor is connected through the selection transistor to the vertical signal line and constitutes a source follower together with a constant current source 800 of a load circuit outside of the pixel part. Further, a control signal (address signal or select signal) is given to the gate of the selection transistor, whereby the selection transistor is turned on. When the selection transistor is turned on, the source follower transistor amplifies the potential of the floating diffusion 300 (FD) region and outputs a voltage in accordance with that potential to the vertical signal line. Through the vertical signal line, voltages output from the pixels are output to a pixel signal readout circuit 210 constituted by a column-parallel processing part.

Further, in each pixel, as the photodiode (PD) 150, a pinned photodiode (PPD) is widely used. On the substrate surface forming the photodiode (PD) 150, there is a surface level due to dangling bonds or other defects, therefore a large charge (dark current) is generated by the heat energy, so a correct signal can no longer be read out. In a pinned photodiode (PPD) , a charge accumulation part of the photodiode (PD) 150 is buried in the substrate, so it is possible to reduce entry of dark current into the signal. Note that, the sensitivity of a photodiode (PD) 150 can be changed by, for example, changing theexposure time, etc.

The pinned photodiode (PPD) is, for example, constituted by forming an n-type semiconductor region and forming a shallow p-type semiconductor region which has a rich impurity concentration for suppressing dark current on the surface of this n-type semiconductor region, that is, in the vicinity of the interface with an insulation film.

< Circuit >

FIG. 4 is a circuit diagram showing an example of a pixel according to the second embodiment of the present invention. As shown in FIG. 2, a circuit has four sets of the PDs and the TXs share the in-pixel devices, and which can be the pixel in FIG. 3. The photodiode (PD) 150 converts electromagnetic radiation into an electrical charge. The electrical charge is selectively transmitted to a floating diffusion 300 (FD) region via a transfer gate device (TX) . The FD layer is connected to a gate of a source follower (SF) device 600 (SF) , and an output signal (Vout) is transmitted to a signal line via a row select device (SEL) . A current source 800 (Icolumn) is connected between the SEL and a ground. Accordingly, if gates of the TX and the SEL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line. A reset device 500 (RST) selectively resets an electrical charge accumulated in the FD. A dual conversion gain (DCG) device can be connected between the RST and the FD layer, in order to realize high dynamic range by combining two types of gains. AVSS1 can be ground or a negative voltage in the range of -5.0V to 0V in case of n-type photodiode. In some embodiments, the photodiode is p-type, and pixel to pixel isolation is n-type.

In the present embodiment, the readout circuit 210 is constitutedsuch that it can perform, in one reading period, a first conversion gain mode reading operation of reading out the pixel signal with a first conversion gain in accordance with a first capacity set by the variable capacity part and a second conversion gain mode reading operation of reading the pixel signal with a second conversion gain in accordance with a second capacity (different from the first capacity) set by the variable capacity part. That is, the solid-state imaging device 100 in the present embodiment is provided as a solid-state imaging device 100 having a wide dynamic range which outputs a signal with respect to a charge (electrons) photoelectrically converted in one accumulation period (exposure period) while switching between the first conversion gain (for example high conversion gain) mode and the second conversion gain (low conversion gain) mode inside the pixel in one reading period and outputs both a bright signal and dark signal.

The readout circuit 210 in the present embodiment basically performs the first conversion gain mode reading operation and second conversion gain mode reading operation in the accumulation period after the reset period for discharging the charge in the photodiode and floating diffusion 300 region. Further, in the present embodiment, the readout circuit 210 performs at least one of the first conversion gain mode reading operation or second conversion gain mode reading operation in the reading period after at least one transfer period after the reading period after the reset period. That is, in the reading period after the transfer period, sometimes both of a first conversion gain mode reading operation and a second conversion gain mode reading operation are performed.

In an ordinary pixel read-out operation, by driving by the readout circuit 210, a shutter scan operation is carried out, and then a reading scan operation is carried out. A first conversion gain mode (HCG) reading operation and second conversion gain mode (LCG) reading operation are carried out in the reading scan period.

A plurality of pixels each including a photodiode (photoelectric conversion element) and an in-pixel amplifier are arranged in a two-dimensional matrix including N rows and M columns.

The pixel has for example a photodiode (PD) 150 as a photoelectric conversion part 170 (photoelectric conversion element) . For this photodiode (PD) 150, one each of a first charge transfer gate device 450 constituted by a transfer transistor TG-Tr, a second charge transfer gate device 550 constituted by a transfer transistor TG-Tr, a reset device 500 constituted by a reset transistor RST-Tr, a source follower device 600 constituted by a source follower transistor SF-Tr, and a row-select device 700 constituted by a selection transistor SEL-Tr are provided.

Further, the pixel can have a variable capacity part which is connected to a floating diffusion 300 (FD) region (floating diffusion 300 region layer) and can change the capacity of the floating diffusion 300 (FD) region in response to a capacity changing signal CS.

The photodiode (PD) 150 generates and accumulates a signal charge (here, electrons) in an amount in accordance with the incident electromagnetic radiation quantity. Below, an explanation will be given of a case where the signal charge includes electrons and each transistor is an n-type transistor, but the signal charge may be comprised of holes and some transistor may also be a p-type transistor. Further, the present embodiment is effective also in the case where each transistor is shared among a plurality of photodiodes and the case where a three-transistor (3Tr) pixel not having a selection transistor is employed.

In each pixel, as the photodiode (PD) 150, use may be made of a pinned photodiode (PPD) . On the substrate surface forming the photodiode (PD) 150, there is a surface level due to dangling bonds or other defects; therefore, a large charge (dark current) is generated by heat energy, so a correct signal can no longer be read out. In a pinned photodiode (PPD) , a charge accumulation part of the photodiode (PD) 150 is buried in the substrate, so it ispossible to reduce entry of dark current into the signal.

However, in the case where the size is relatively large and the longitudinal and lateral aspect ratio is relatively large, for example, the case of an about a 3-μm square pixel, the accumulated charge is mainly limited to the pn-junction capacitance in the vertical direction (normal line direction of the semiconductor layer 160: depth direction of the semiconductor layer 160) at a location close to the photodiode (PD) 150 part (photoelectric conversion part 170) , so it is difficult to efficiently increase the storage capacity.

Therefore, in the solid-state imaging device 100 in the presentembodiment, in the photoelectric conversion part 170 of the pinned photodiode (PPD) , in order to increase the storage capacity, a plurality of sub-areas are provided by dividing the photoelectric conversion layer (for example, n layer) so that there are a plurality of pn junction parts in the direction (horizontal direction) perpendicular to the normal line of the substrate inside the pixel. The other effects of the second embodiment of the present invention are the same as those of the first embodiment.

FIG. 5 is a top view of an example circuit layout according to the present embodiment of the present invention. As shown in FIG. 5, the photodiode (PD) 150 is divided into two parts by vertically inserted middle depth p-well (MPW) , and the transfer gate is divided into two parts as well. The reason to use a divided transfer gate is to reduce leakage current in the floating diffusion 300 region due to GIDL by decreasing gate area contacting to the floating diffusion 300 region area. The GIDL is critical for this kind of architecture because transfer gate bias is kept negative during exposure in order to suppress dark current caused by the transfer gate region. In some embodiments, the width of MPW ranges from 0.1 um to 0.5 um. The vertically inserted middle depth p-well (MPW) is the first sub-area 181 of photoelectric conversion part 170.

As shown in FIG. 5, there are four sub-pixels in a pixel set 2091. The pixel set 2091 may correspond toone pixel (P1, P2, P3…) in the pixel array 209 of the imaging system 201 in FIG. 3. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094 and a lower right sub-pixel 2095. Each sub-pixel has the first charge transfer gate device 450 and the second charge transfer gate device 550. The first charge transfer gate device 450 is connected tothe second charge transfer gate device 550 by a wiring 2099. The vertically inserted middle depth p-well of the upper left sub-pixel 2092 is connected tothe vertically inserted middle depth p-well of the lower left sub-pixel 2093. The vertically inserted middle depth p-well of the upper right sub-pixel 2094 is connected tothe vertically inserted middle depth p-well of the lower right sub-pixel 2095.

FIG. 6 is a cross-sectional view of the example circuit layout along line A-A' of FIG. 5. As shown in FIG. 6, line A-A' crosses the lower left sub-pixel 2093 and the lower right sub-pixel 2095. The lower left sub-pixel 2093 has a photodiode (PD) 150, a first charge transfer gate device 450 and a second charge transfer gate device 550. The photodiode (PD) 150 of the lower left sub-pixel 2093 includes a semiconductor layer 160, a photoelectric conversion part 170, a separation layer 180, a color filter 250, a micro lens 350, a deep trench isolation 173, an anti-reflection 183 and a metal grid 185. As shown in FIG. 6, the lower left sub-pixel 2093 shares the separation layer 180 with the lower right sub-pixel 2095. The vertically inserted middle depth p-well (MPW) electrically connects to AVSS1 through ashallow p-well (SPW) , the pinned photodiode (PPD) , and P+ source/drain. The depth of MPW ranges from more than 0.0μm and 3.0μm or less. In the present embodiment, at least one cross sectional area of the first sub-area 181 parallel to the first side 171 can be larger than another cross sectional area of the first sub-area 181 parallel to the first side 171. At least one area of the first sub-area 181 differs in doping concentration from the other areas of the first sub-area 181. Moreover, the first sub-area 181 has a middle p-well portion 1811 (MPW) and a shallow-middle p-well portion 1812. A cross sectional area of the middle p-well portion 1811 (MPW) parallel to the first side 171 can be larger than the area of the first sub-area 181 in the first side 171. As shown in FIG. 6, the middle p-well portion 1811 (MPW) is placed apart from the semiconductor layer 160. The doping concentration of the shallow-middle p-well portion 1812 is larger than the doping concentration of the middle p-well portion 1811 (MPW) .

In the present embodiment, at least one cross sectional area of the separation layer 180 parallel to the first side 171 can be larger than another cross sectional area of the separation layer 180 parallel to the first side 171. Moreover, the separation layer 180 is formed in contact with the semiconductor layer 160. The separation layer 180 has a deep p-well portion, and the cross sectional area of the deep p-well portion parallel to the first side 171 is larger than an area at a portion where the separation layer 180 makes contact with the semiconductor layer 160. As shown in FIG. 6, the deep p-well portion is placed apart from the semiconductor layer 160. In the present embodiment, at least one area of the separation layer 180 differs in doping concentration from the other areas of the separation layer 180. As shown in FIG. 6, the separation layer 180 has a shallow p-wellregion 1801 (SPW) and a deep p-will region 1802 (DPW) . The doping concentration of the shallow p-wellregion 1801 (SPW) is larger than the doping concentration of the deep p-will region 1802 (DPW) .

The deep trench isolation 173 portion is buried inside the deep p-well portion of the separation layer 180 from a side of the second side 172 of a photoelectric conversion part 170. The deep trench isolation 173 portion does not penetrate the deep p-well portion of the separation layer 180. There is the anti-reflection 183 part between the deep p-well portion of the separation layer 180 and the deep trench isolation 173 portion. The deep trench isolation 173 portion has a plate portion 1731 and a buried portion. The plate portion 1731 is placed on the second side 172 of the photoelectric conversion part 170. The plate portion 1731 covers the lower left sub-pixel 2093 and the lower right sub-pixel 2095. There is the anti-reflection 183 part between the plate portion 1731 and the photoelectric conversion part 170. The plate portion 1731 connects the deep trench isolation 173 portion of the lower left sub-pixel 2093, and the deep trench isolation 173 portion, which is not buried in the separation layer 180 that shared with the lower left sub-pixel 2093, of the lower right sub-pixel 2095.

< Control method of imaging system >

Hereinafter, a control method of the imaging system 201 according to the second embodiment of the present invention will be described in detail. The reset device 500 is constituted by a reset transistor RST-Tr. The reset transistor RST-Tr is connected between the power supply line AVDD and the floating diffusion 300 (FD) region and is controlled through the control signal RST. As shown in FIG. 4, the reset transistor RST-Tr can be connected between the power supply line AVDD and the floating diffusion 300 (FD) region and canbe controlled through the control signal RST as well. The power supply line AVDD can be connected to the source follower device 600. The power supply line AVDD can be connected to a gate of the row-select device 700. The reset transistor RST-Tr is selected and becomes a conductive state in the period when the control signal RST is the H level and resets the floating diffusion 300 (FD) region to the potential of the power supply line AVDD (or VRst) .

Note that, the present embodiment, as will be explained later, can be constituted so that first binning transistors (P1, P2…Pn, Pn+1) used as the dual conversion device 400 have functions as the reset devices 500 as well. Further, it is also possible to employ a constitution where all pixels of the plurality of (four in the present example) of pixels which are connected through the first binning transistors (Pn, Pn+1) share the reset device 500 formed by the first binning transistor (Pn+1) which discharges the floating diffusion 300 (FD) region in the reset period PR.

The source follower device 600 is constituted by a source follower transistor SF-Tr. The row-select device 700 is constituted by a selection transistor SEL-Tr. The source follower transistor SF-Tr and the selection transistor SEL-Tr (row-select device 700) are connected in series between the power supply line AVDD and the vertical signal line Vout. The gate of the source follower transistor SF-Tr is connected to the floating diffusion 300 (FD) region. The selection transistor SEL-Tr is controlled through the control signal SEL. The selection transistor SEL-Tr is selected and becomes a conductive state in the period where the control signal SEL is at the H level (high level) . Due to this, the source follower transistor SF-Tr outputs to the vertical signal line Vout, the read-out signal VSL of column output obtained by converting the charge in the floating diffusion 300 (FD) region to a voltage signal with a gain in accordance with the charge amount (potential) . These operations are carried out simultaneously and in parallel for one row's worth of the pixels since, for example, the gates of the transfer transistors TG-Tr, reset transistors RST-Tr, and selection transistors SEL-Tr are connected in units of rows.

The pixel array 209 are arranged in Y rows (R1, R2…) and in X columns (C1, C2…) as shown in FIG. 3. Y and X are positive integers. Therefore, there are Y number of each of the control lines LSEL, LRST, and LTG, and there are X vertical signal lines Vout. For example, the control lines LSEL, LRST, and LTG can be configured to one row scanning control line. One pixel (RX, RY) is the pixel set 2091 in FIG. 5.

The control circuit 205A can has a vertical scanning circuit and a timing control circuit 205A. The vertical scanning circuit drives pixels through the row scanning control line in the shutter row and read row under the control of the timing control circuit 205A. Further, the vertical scanning circuit outputs a row selection signal having row addresses of the read row for reading the signals and the shutter row for resetting the charge accumulated in the photodiode (PD) 150 according to the address signal.

The readout circuit 210 can have a reading part and a horizontal scanning circuit. In an ordinary pixel readout operation, a shutter scan is carried out by driving of the reading part by the horizontal scanning circuit. After that, the reading scan is carried out.

Next, operation timings of the shutter scan and reading scan at the time of an ordinary pixel readout operation in the present embodiment will be described.

The control signal SEL for controlling the on (conductive) state and off (non-conductive) state of the selection transistor SEL-Tr is set at an L level (low level) for a shutter scan period PSHT whereby the selection transistor SEL-Tr is held in a non-conductive state, while is set at an H level for a reading scan period PRDO whereby the selection transistor SEL-Tr is held in a conductive state. Further, in the shutter scan period PSHT, the control signal TG is set at an H level for a predetermined term in the period where the control signal RST is the H level whereby the photodiode (PD) 150 and the floating diffusion 300 (FD) region are reset through the reset transistor RST-Tr and transfer transistor TG-Tr.

In the reading scan period PRDO, the control signal RST is set at an H level whereby the floating diffusion 300 (FD) region is reset through the reset transistor RST-Tr. In the reading period PRD1 after this reset period PR, the signal in the reset state is read out. After the reading period PRD1, for apredetermined period, the control signal TG is set at an H level whereby the accumulated charge in the photodiode (PD) 150 is transferred through the transfer transistor TG-Tr to the floating diffusion 300 (FD) region. A signal in accordance with the accumulated electrons (charge) is read out in the reading period PRD2 after this transfer period PT.

Note that, in the ordinary pixel readout operation in the present embodiment, the accumulation period (exposure period) EXP is a period from when resetting the photodiode (PD) 150 and floating diffusion 300 (FD) region to switch the control signal TG to the L level in the shutter scan period PSHT up to when switching of the control signal TG to the L level again in order to end the transfer period PT in the reading scan period PRDO.

The readout circuit 210 can be constituted so as to include a plurality of column signal processing circuits 2061 (not shown) which are arranged corresponding to the column outputs of the pixel array 209 so that column parallel processing is possible among the plurality of column signal processing circuits 2061.

The readout circuit 210 can be constituted do as so include correlated double sampling (CDS) circuits or ADC (analog-to-digital converters: AD converters) , amplifiers (AMP) , and sample/hold (S/H) circuits, etc.

In this way, the read-out circuit 210, for example can include ALCs for converting the read-out signals Vout of the column outputs of the pixel array 209 to digital signals. Otherwise, in the readout circuit 210, for example, amplifiers (AMP) for amplifying read-out signals Vout of column outputs of the pixel array 209 can be arranged. Further, in the readout circuit 210, for example, sample/hold (S/H) circuits for sampling and holding the read-out signals Vout of column outputs of the pixel array 209 can be arranged.

The horizontal scanning circuit scans signals processed in the plurality of column signal processing circuits 2061 such as the ALCs in the readout circuit 210, transfers the results to the horizontal direction, and outputs the same to a not-shown signal processing circuit 206.

The timing control circuit 205A generates timing signals which are necessary for signal processing in the pixel array 209, the vertical scanning circuit, the reading part, horizontal scanning circuit, etc.

Above, the configurations and functions of the parts in the solid-state imaging device 100 were explained in brief. Next, the configuration of the dual conversion device 400 according to the present embodiment and the readout processing concerned with that, and so on, will be explained in detail. The dual conversion device 400 is constituted by a variable capacity part.

Further, as explained above, in the photoelectric conversion part 170 of the pinned photodiode (PPD) in each pixel set 2091, in order to increase the storage capacity, the photoelectric conversion layer constituted by the n layer is divided by the p-layer to provide the plurality of sub-areas (first sub-area 181 and second sub-area 182) so that there are a plurality of pn-junction parts in the direction (horizontal direction) perpendicular to the normal line of the semiconductor layer 160 inside the pixel set 2091. By forming the two sub-areas (first sub-area 181 and second sub-area 182) in the direction perpendicular to the normal line of the semiconductor layer 160 by the p layer (first conductivity type semiconductor) in the pinned photodiode (PPD) of each pixel set 2091 in this way, complete depletion can be realized even with a low bias voltage. Further, in the solid-state imaging device 100 in the present embodiment, it is possible to read out the charges accumulated in the sub-areas by the charge transfer part constituted by the two transfer transistors TG-Tr. Due to this, it is possible to increase the storage capacity while reducing noise and raising sensitivity, and it is possible to expand the dynamic range without degrading the optical characteristics.

In the present embodiment, the description was made with an example in which thesub-pixel charges each stored in all of thesub-pixels included in the pixel array 209 are sequentially read out by using the row select transistors, and the data is read out as a frame composed of all of the sub-pixels in the pixel array 209. However, alternatively an image sensor operating in a method referred to as “event driven type” instead of reading out the data as a frame can be implemented by using the pixel of the present embodiment. The event driven image sensor may output data in an asynchronous way and at any time in response to changes in the intensity of electromagnetic wave incident on the pixel set 2091. Specifically, for example, if thesub-pixel charges generated by electromagnetic wave incident on the photodiode and stored in the photodiode exceed a predetermined threshold value, the event of the electromagnetic wave intensity exceeding the threshold value or data of the electromagnetic wave intensity may be output with the coordinate of the sub-pixel and the timing information. When there is only one sub-pixel in the pixel set 2091, the sub-pixel can be read as the pixel set 2091.

As explained above, in the solid-state imaging device 100 of the present embodiment, the pinned photodiode (PPD) has the semiconductor layer 160 of the first conductivity type semiconductor, the photoelectric conversion part 170 having the first side 171 and the second side 172 opposite to the first side 171, and being formed in contact with the semiconductor layer 160 at the first side 171; and the charge transfer gate device electrically connected to the photoelectric conversion part 170, and transferring charge stored in the photoelectric conversion part 170 to floating diffusion 300 region. In addition, the photoelectric conversion part 170 at least comprises a first sub-area 181 of the first conductivity type semiconductor and a second sub-area 182 constituted by a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor. In addition, the charge transfer gate device has the first charge transfer gate device 450 and the second charge transfer gate device 550, the first charge transfer gate device 450 disposed in at least the first area surface, and the second charge transfer gate device 550 disposed in at least the second area surface. Further, in the solid-state imaging device 100 in the present embodiment, in the pinned photodiode (PPD) , in order to increase the storage capacity, the photoelectric conversion part 170 constituted by the n layer is divided by the p layer to provide a plurality of sub-areas (first sub-area 181 and second sub-area 182) so that there are a plurality of pn-junction parts (junction parts) in a direction perpendicular to the normal line of the semiconductor layer 160 inside the pixel set 2091.

In this way, in the pinned photodiode (PPD) of the first embodiment, by forming the two sub-areas (first sub-area 181 and second sub-area 182) in the direction perpendicular to the normal line of the semiconductor layer 160 by the p layer (a first conductivity type semiconductor) , in comparison with a comparative example not forming sub-areas, complete depletion can be realized even with a low bias voltage. Due to this, in the solid-state imaging device 100 in the present embodiment, it is possible to increase the storage capacity while reducing noise and increasing sensitivity and it is possible to expand the dynamic range without degrading the optical characteristics.

Moreover, full well capacity (FWC) is one of important key performance indicators for solid-state imaging device 100s. Lower full well capacity induces low dynamic range (DR) and low signal-to-noise ratio (SNR) under stronglight. Therefore, higher full well capacity is always preferred. However, other key performance indicators are competing with the full well capacity. Increasing full well capacity as much as possible with a limited area is strongly required.

According to the present embodiment of the present invention, deep part of the photodiode (FD) is one per one pixel, and there is a plurality ofthe photodiode (FD) layers located from the middle to the device side is a plural, which is realized by vertically placing p-type isolation layer as shown in FIG. 1. It expands from photosensitive surface in the device side to the middle depth of the photodiode. This structure can enhance pn junction capacitance in the photodiode, the then full well capacity will increase. In this case, the subdivided shallow photodiode (SPD) should have separated transfer gate, whose charge transfer capability is sufficiently high, and furtherimprove full well capacity (FWC) .

In addition, according to the present embodiment of the present invention, the first sub-area 181 of the photoelectric conversion part 170 makes contact with the semiconductor layer 160, and thesemiconductor type of the semiconductor layer 160 is same as thesemiconductor type of the first sub-area 181 of the photoelectric conversion part 170. Therefore, it is possible to prevent that the inserted vertical p-type layer from floating or the resistance between the p-type layer and p-well pick up from beingtoo high. Thereby, the pn junction capacitance becomes higher and full well capacity (FWC) improvement is higher.

Further, according to the first embodiment, it is possible to obtain the effect where that it is possible to output a signal for the charge (electrons) which is photoelectrically converted in one accumulation period (exposure period) while switching between a high conversion gain mode and a low conversion gain mode inside the pixel set 2091 in one reading period and thereby output both a bright signal and a dark signal, the reset noise at the time of the high conversion gain mode and low conversion gain mode can be cancelled, expansion of the dynamic range can be realized while suppressing occurrence of moving body distortion, and consequently a higher image quality can be realized.

Further, according to the present embodiment, it is possible to flexibly switch the number of floating diffusion 300 (FD) regions connected, therefore the configuration is excellent in expandability of the dynamic range. Moreover, the pixels in the pixel set 2091 shares floating diffusion 300 (FD) regions. Further, the number of transistors in each pixel set 2091 is small. Therefore it is possible to raise a PD opening ratio and raise the photoelectric conversion sensitivity and number of saturation electrons.

<< Third embodiment >>

Hereinafter, a solid-state imaging device 100A according to a third embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 9 is a top view of an example circuit layout according to the third embodiment of the present invention. As shown in FIG. 9, a first sub-area 181 of thesolid-state imaging device 100A has an x-direction portion 1813 and a y-direction portion 1814. The x-direction portion 1813 crosses the y-direction portion 1814. The first sub-area 181 is cross shape on top view. There are four sub-pixels in a pixel set 2091. The pixel set 2091 may correspond to one pixel (P1, P2, P3…) in the pixel array 209 of the imaging system 201 in FIG. 3. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094 and a lower right sub-pixel 2095. Each pixel has a first charge transfer gate device 450, a second charge transfer gate device 550, a third charge transfer gate device 650 and the fourth charge transfer gate device 750. A shallow PD layer 1822 is divided into 4 parts by x-direction and y-direction of the first sub-area 181 of each pixel. The present embodiment can further increase pn-junction capacitance in photodiode, then contribute to full well capacity further improvement. This configuration shows more robust against overlay error of pixel layers.

FIG. 10 is a circuit diagram showing an example of a pixel according to the third embodiment of the present invention. The circuit in FIG. 10 is equivalent circuit of the example circuit layout according to the third embodiment of the present invention in FIG. 9. Compared to the circuit of the second embodiment in FIG. 4, the photodiode (PD) 150 electric electrically connected to four charge transfer gate device. That is, there are 16th charge transfer gate devices in the pixel set 2091.

<< Forth embodiment >>

Hereinafter, a solid-state imaging device 100B according toa forth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 11 is a top view of an example circuit layout according to the forth embodiment of the present invention. The pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094 and a lower right sub-pixel 2095. Each pixel has a first charge transfer gate device 450 and a second charge transfer gate device 550. A shallow photodiode is divided into twoparts by a first sub-area 181. As shown in FIG. 11, the first sub-area 181 can be vertically inserted middle depth p-well (MPW) .

As shown in FIG. 11, the pixel set 2091 has an upper left sub-pixel 2092, a lower left sub-pixel 2093, an upper right sub-pixel 2094 and a lower right sub-pixel 2095. Each sub-pixel has the first charge transfer gate device 450 and the second charge transfer gate device 550. The first charge transfer gate device 450 is connected to the second charge transfer gate device 550 by a wiring 2099. The vertically inserted middle depth p-well of the upper left sub-pixel 2092 is connected to the vertically inserted middle depth p-well of the lower right sub-pixel 2095. The vertically inserted middle depth p-well of the upper right sub-pixel 2094 is connected to the vertically inserted middle depth p-well of the lower left sub-pixel 2093. The vertically inserted middle depth p-well of the upper left sub-pixel 2092, the lower left sub-pixel 2093, the upper right sub-pixel 2094 and the lower right sub-pixel 2095 is configured of cross shape on top view. The present embodiment can further increase pn-junction capacitance in photodiode, then contribute to full well capacity further improvement. This configuration shows more robust against overlay error of pixel layers.

<< Fifth embodiment >>

Hereinafter, a solid-state imaging device 100C according to a fifth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 12 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the fifth embodiment of the present invention. As shown in FIG. 12, the first charge transfer gate device 450 and the second charge transfer gate device 550 have embedded part into the photoelectric conversion part 170. When a shallow photodiode is divided into two parts by the first sub-area 181, the first charge transfer gate device 450 is embedded into different part from the second charge transfer gate device 550. As shown in FIG. 12, a gate insulator 190 is placed between the first charge transfer gate device 450 and the shallow photodiode, and between the second charge transfer gate device 550 and the shallow photodiode. This embodiment can enhance a charge transfer capability and full well capacity can be improved.

<< Sixth embodiment >>

Hereinafter, a solid-state imaging device 100D according toa sixth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 13 is a top view of an example circuit layout according to the sixth embodiment of the present invention. As shown in FIG. 13 a vertically inserted middle p-well region are excluded in the floating diffusion 300 region. That is, the vertically inserted middle p-well region is placed apart from the floating diffusion 300 region. On the first side 171 of the photoelectric conversion part 170, the first sub-area is provided to protrude from the separation layer. The second sub-area 182 is almost divided into two areas. The present embodiment can further improve fixed pattern noise caused by floating diffusion 300 region leakage.

<< Seventh embodiment >>

Hereinafter, a solid-state imaging device 100E according toa seventh embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 14 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the seventh embodiment of the present invention. As shown in FIG. 14, a deep trench isolation 173 is formed in the vertically inserted middle p-well region. Negative charge of an anti-reflection 183 part can contribute a photodiode capacitance. The anti-reflection 183 part can be film shape. The deep trench isolation 173 portion is buried inside the deep PD layer 1821 of the photoelectric conversion part 170. The deep trench isolation 173 portion is buried inside the first sub-area 181 of the photoelectric conversion part 170 from a side of the second side 172 of a photoelectric conversion part 170. The deep PD is divided into two parts by the deep trench isolation 173. The present embodiment can further improve full well capacity.

<< Eighth embodiment >>

Hereinafter, a solid-state imaging device 100F according toan eighth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 15 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the eighth embodiment of the present invention. As shown in FIG. 15, a deep trench isolation 173 has full depth. That is, the deep trench isolation 173 portion is buried inside the semiconductor layer 160 from a side of the second side 172 of a photoelectric conversion part 170. The full depth deep trench isolation 173 can be made by front-side or back-side. The back-side means the back side of the page, and the front-side means the front side of the page. Anti-blooming performance can be improved by present embodiment. In addition, a full well capacity can be further improved thanks to large anti-blooming design margin.

<< Ninth embodiment >>

Hereinafter, a solid-state imaging device 100G according toa ninth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 16 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the ninth embodiment of the present invention. In the present embodiment, the second sub-area 182 of the photoelectric conversion part 170 has a very deep p-well region 174. The very deep p-well region 174 is formed by the first conductivity type semiconductor. In the present embodiment, the very deep p-well region 174 is formed by the p type semiconductor. The very deep p-well region 174 is placed between the deep PD layer 1821 and the anti-reflection 183 part. The very deep p-well region 174makes contact with the deep PD layer 1821. The doping concentration of the very deep p-well region 174 is smaller than the doping concentration of the first sub-area 181. The very deep p-well region 174 is formed from deep PD layer 1821 to backside surface. Backside surface is the first side 171 of the photoelectric conversion part 170. That is, the very deep p-well region 174 is formed on the first side 171 of the photoelectric conversion part 170. In addition, the separation layer 180 extends to the backside surface as well. The embodiment can further increase full well capacity by increasing effective photosensitive voltage.

<< Tenth embodiment >>

Hereinafter, a solid-state imaging device 100H according toa tenth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 17 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the tenth embodiment of the present invention. Compared to the ninth embodiment, the deep trench isolation173 of the present embodiment is buried in the very deep p-well region 174. The deep trench isolation 173 of the present embodiment penetrate the very deep p-well region 174. The separation layer 180 extends to the deep PD layer 1821 of the photoelectric conversion part 170. The very deep p-well region 174 is formed from the deep PD layer 1821 to backside surface. Backside surface is the first side 171 of the photoelectric conversion part 170. The embodiment can further increase full well capacity by increasing effective photosensitive voltage.

<<Eleventh embodiment >>

Hereinafter, a solid-state imaging device 100I according toan eleventh embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 18 is a simplified cross-sectional view showing an example of the configuration of principal parts in a pixel according to the eleventh embodiment of the present invention. Compared to the tenth embodiment, the deep trench isolation 173 of the present embodiment is buried in the deep PD layer 1821. The deep trench isolation 173 of the present embodiment penetrate the deep PD layer 1821. The separation layer 180 extends to the shallow PD layer 1822 of the photoelectric conversion part 170. The very deep p-well region 174 is formed from the deep PD layer 1821 to backside surface. Backside surface is the first side 171 of the photoelectric conversion part 170. As shown in FIG. 18, depth of the very deep p-well region 174 can be equal to or smaller than the first sub-area 181. Depth of the very deep p-well region 174 means thickness of the first sub-area 181 in a direction perpendicular to a normal line of the first side 171. The embodiment can further increase full well capacity by increasing effective photosensitive voltage.

<< Twelfth embodiment >>

Hereinafter, a solid-state imaging device 100J according toa twelfth embodiment of the present invention will be described in detail with reference to the attached drawings. FIG. 19 is a simplified cross-sectional view showing an example of the configuration of principal parts in the apparatus according to the twelfth embodiment of the present invention. As shown in FIG. 19, a solid-state imaging device 100 according to twelfth embodiment of the present invention has a second integrated circuit chip 850.

FIG. 20 is schematic diagrams illustrating the solid-state imaging device 100J according to the embodiment of the present invention. First, a typical solid-state imaging device 100 can be described with reference to A in FIG. 20. The typical solid-state imaging device 100J includes a pixel array, a control circuit, and a logic circuit for signal processing, which are mounted on a single semiconductor chip. In general, an image sensor includes the pixel array and the control circuit. The pixel array can be frontside illuminations, and can be backside illuminations.

As shown in B in FIG. 20, on the other hand, a solid-state imaging device 100 according to the embodiment of the present invention includes a pixel array and a control circuit (control region) mounted on a first semiconductor chip section and a logic circuit including a signal processing circuitfor signal processing mounted on a second semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section are electrically connected to each other, and can be to form a single semiconductor chip to provide the solid-state imaging device 100.

As shown in C in FIG. 20, in the solid-state imaging device 100 according to embodiment of the present invention, the pixel array can be mounted on the first semiconductor chip section. Also, the control circuit and the logic circuit including signal processing circuit can be mounted on the second semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section can be electrically connected to each other, and can be to form a single semiconductor chip to provide the solid-state imaging device 100.

As shown in D in FIG. 20, in the solid-state imaging device 100 according to embodiment of the present invention, a pixel array can be is mounted on a first semiconductor chip section. Also, the memory circuit can be mounted on a second semiconductor chip section. Then, a control circuit and a logic circuit including signal processing circuit can be mounted on a third semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section and the third semiconductor chip section can be electrically connected, and can be to form a single semiconductor chip or two semiconductor chips to provide the solid-state imaging device 100.

As shown in E in FIG. 20, in the solid-state imaging device 100 according to embodiment of the present invention, a pixel array can be mounted on a first semiconductor chip section. Also, a pixel circuit can be mounted on a second semiconductor chip section. Then, a control circuit and a logic circuit including signal processing circuit can be mounted on a third semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section and the third semiconductor chip section can be electrically connected, and can be to form a single semiconductor chip or two semiconductor chips to provide the solid-state imaging device 100.

The solid-state imaging device 100 according to the embodiment of the present invention can be applied to both of a frontside-illuminated type image sensor and backside-illuminated type image sensor.

<<< Electronic apparatus >>>

Hereinafter, electronic apparatus according to an embodiment of the present invention will be described in detail with reference to the attached drawings. The solid-state imaging device 100 explained above can be applied as imaging device to an electronic apparatus such as a digital camera, video camera, portable terminal, or monitoring camera, camera for medical endoscope.

FIG. 21 is a block diagram of electronic apparatus according to the embodiment of the present invention. As shown in FIG. 21, the electronic apparatus 200A includes a lens 201A, an imaging element 202A, a DSP circuit 203A, a frame memory 204A, a display unit 205A, a recording unit 206A, an operation unit 207A, and a power source unit 208A. Furthermore, in the electronic device 200A, the DSP circuit 203A, the frame memory 204A, the display unit 205A, the recording unit 206A, the operation unit 207A, and the power source unit 208A are connected to each other via a bus line 209.

For example, the imaging element 202A corresponds to the solid-state imaging device 100. The DSP circuit 203A is a camera signal processing circuit for processing a signal supplied from the imaging element 202A. The DSP circuit 203A outputs image data obtained by processing the signal from the imaging element 202A. The frame memory 204A temporarily holds the image data processed by the DSP circuit 203A in frame units. The display unit 205A includes, for example, a panel type display device such as a liquid crystal panel and an organic Electro Luminescence (EL) panel and displays a moving image or a still image imaged by the imaging element 202. The recording unit 206A records the image data of the moving image or the still image imaged by the imaging element 202A to a recording medium such as a semiconductor memory or a hard disk. The operation unit 207A outputs an operation instruction regarding various functions of the electronic device 200A according to a user's operation. The power source unit 208A appropriately supplies various power sources to be an operation power source of the DSP circuit 203A, the frame memory 204A, the display unit 205A, the recording unit 206A, and the operation unit 207A to these components which are supply targets. FIG. 22 is examples of technologies to which the image sensor of the present invention is applied.

<<<Method for producing electronic apparatus>>>

Hereinafter, a method according to an embodiment of the present invention for producing electronic apparatus will be described in detail with reference to the attached drawings. FIG. 7 isa flowchart of a method for forming pixel sensor of FIG. 5. As shown in FIG. 7, the method according to an embodiment of the present invention for producing electronic apparatus has a step of forming a pixel device region isolation structure in a semiconductor substrate, a step of forming a deep photodiode well of pixel sensor in the semiconductor substrate, a step of a plurality of shallow photodiode wells in the pixel sensor well, where the a plurality of shallow photodiode wells are divided by vertically inserted middle depth p-well, a step of forming transfer transistors and pixel device transistors over a front-side of the semiconductor substrate, a step of forming a floating diffusion node in the pixel well region between the plurality of photodetectors, a step of forming an interconnect structure on the front-side of the semiconductor substrate, a step of bonding the interconnect structure to a second integrated ship, a step of forming a deep trench isolation structure in the semiconductor substrate, and a step of forming an anti-reflection layer, forming a plurality of color filters on the anti-reflection layer, forming a plurality of grid structure between color filters, and forming a plurality of microlens on the color filters.

The substrate includes a semiconductor material such as silicon or germanium. In some embodiments, the substrate can include at least one or more of other photosensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium, antimonide, semiconductor on insulator or combinations thereof.

In some embodiments, the first sub-areacan have a doping concentration between about 5x10 ¹⁶ atoms/cm ³ and about 5x10 ¹⁸ atoms/cm ³. In some embodiments, the separation layer can have a doping concentration between about 5x10 ¹⁶ atoms/cm ³ and about 5x10 ¹⁸ atoms/cm ³. In some embodiments, the deep PD layercan have a doping concentration between about 5x10 ¹⁵ atoms/cm ³ and about 5x10 ¹⁷ atoms/cm ³. In some embodiments, the peak doping concentration of the separation layercan be greater than that of the deep PD layer.

[Example]

Next, examples of the present invention will be described. The conditions in the examples are one example of conditions adopted to confirm the feasibility and effects of the present invention, but the present invention is not limited to this one example of conditions. The present invention can adopt various conditions as long as the object of the present invention is achieved without departing from the gist of the present invention.

FIG. 8 iselectrostatic potential distribution at the center of pixel simulated by 3D process and device simulation and the simulation result of full well capacity according to an example of the present invention. Device simulation in which pixel size is 1.0μm. As shown in FIG. 8, the simulation results clearly show two shallow photodiode areas (SPD) near front-side surface and the photodiode potential smoothly connects from SPD to one large deep photodiode (DPD) . Besides, obtain simulation result shows that full well capacity improves by 35%.

While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims. The control apparatus according to the embodiment of the present invention can be a robot, either with hydraulic orelectric actuators.

[Industrial Applicability]

According to the present invention, it is possible to provide a solid-state imaging device and electronic apparatus capable of further improving FWC (full well capacity) . Therefore, the present invention has high industrial applicability.

[Brief Description of the Reference Symbols]

Solid-state imaging device 100, Photodiode (PD) 150, Semiconductor layer 160, Photoelectric conversion part 170, First side 171, Second side 172, Deep trench isolation 173, Plate portion 1731, Very deep p-well region 174, Separation layer 180, First sub-area 181, Middle p-well portion 1811, Shallow-middle p-well portion 1812, Second sub-area 182, Deep PD layer 1821, Shallow PD layer 1822, Color filter 250, Micro lens 350, First charge transfer gate device 450, Second charge transfer gate device 550, Third charge transfer gate device 650, Fourth charge transfer gate device 750, Photodiode (PD) 150, Floating diffusion 300, Dual conversion device 400, Reset device 500, Source follower device 600, Row-select device 700, Current source 800, Imaging system 201, Control circuit 205, Pixel array 209, Readout circuit 210, Signal processing circuit 260, Pixel set 2091, Upper left sub-pixel 2092, Lower left sub-pixel 2093, Upper right sub-pixel 2094, Lower right sub-pixel 2095, Anti-reflection 183 part, Metal grid 185, Wiring 2099, Lens 201A, Imaging element 202A, DSP circuit 203A, Frame memory 204A, Display unit 205A, Recording unit 206A, Operation unit 207A, Power source unit 208A, Bus line 209A

Claims

A solid-state imaging device comprising:

a semiconductor layer of a first conductivity type semiconductor;

a photoelectric conversion part comprising a first side and a second side opposite to the first side, and being formed in contact with the semiconductor layer at the first side; and

a charge transfer gate device electrically connected to the photoelectric conversion part, and transferring charge stored in the photoelectric conversion part to floating diffusion region,

wherein the photoelectric conversion part at least comprises a first sub-area of the first conductivity type semiconductor and a second sub-area of a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor,

wherein on the first side of the photoelectric conversion part, the first sub-area and the second sub-areacontacts with the semiconductor layer,

wherein thickness of the first sub-area in a direction perpendicular to a normal line of the first side is smaller than thickness of the second sub-area in a direction perpendicular to a normal line of the first side, and

wherein the charge transfer gate device comprises a first charge transfer gate device and a second charge transfer gate device.
The solid-state imaging device according to Claim 1,

wherein at least one cross sectional area of the first sub-area parallel to the first side is larger than another cross sectional area of the first sub-area parallel to the first side.
The solid-state imaging device according to Claim 1 or 2,

wherein the first sub-area comprises a middle p-well portion, and

a cross sectional area of the middle p-well portion parallel to the first side is larger than area of the first sub-area in the first side.
The solid-state imaging device according to Claim 3,

wherein a thickness of the middle p-well portion in a direction perpendicular to a normal line of the first side is more than 0 and 3.0μm or less.
The solid-state imaging device according to any one of Claims 1 to 4, further comprising:

a separation layer formed in a said portion of the photoelectric conversion part,

wherein the separation layer is of a first conductivity type semiconductor.
The solid-state imaging device according to Claim 5,

wherein at least one cross sectional area of the separation layer parallel to the first side is larger than another cross sectional area of the separation layer parallel to the first side.
The solid-state imaging device according to Claim 5 or 6,

wherein the separation layer is formed in contact with the semiconductor layer, and comprises a deep p-well portion, and

a cross sectional area of the deep p-well portion parallel to the first side is larger than an area at a portion where the separation layer contacts with the semiconductor layer.
The solid-state imaging device according to any one of Claims 5 to 7,

wherein at least one area of the separation layerdiffers in doping concentration from the other areas of the separation layer.
The solid-state imaging device according to any one of Claims 5 to 8, further comprising:

a deep trench isolation portion buried inside the separation layer from a side of the second side of a photoelectric conversion part.
The solid-state imaging device according to Claim 9,

wherein the deep trench isolation portion is buried inside the semiconductor layer.
The solid-state imaging device according to Claim 9 or 10,

wherein the deep trench isolation portion is buried inside the second sub-area.
The solid-state imaging device according to any one of Claims 9 to 11,

wherein the deep trench isolation portion is junction isolation or STI isolation.
The solid-state imaging device according to any one of Claims 1 to 12,

wherein the first charge transfer gate device and the second charge transfer gate device electrically connect at the opposite side of the semiconductor layer from the photoelectric conversion part.
The solid-state imaging device according to any one of Claims 1 to 13,

wherein at least one area of the first sub-areadiffers in doping concentration from the other areas of the first sub-area.
The solid-state imaging device according to any one of Claims 1 to 14,

wherein at least one area of the second sub-area differs in doping concentration from the other areas of the second sub-area.
The solid-state imaging device according to any one of Claims 1 to 15,

wherein the first charge transfer gate and the second charge transfer gate have an embedded portion in the semiconductor layer.
The solid-state imaging device according to any one of Claims 1 to 16, further comprising:

a second separation layer being formed in contact with the second side of the photoelectric conversion part, and being of a first conductivity type semiconductor.
The solid-state imaging device according to any one of Claims 1 to 17,

wherein at least one cross sectional area of the second sub-area parallel to the first side is simply connected.
The solid-state imaging device according to any one of Claims 1 to 18, further comprising:

acircuit comprising;

a floating diffusion electrically connected to the first charge transfer gate device and the second charge transfer gate device,

a dual conversion device electrically connected to the floating diffusion, and

a reset device electrically connected to the floating diffusion through the dual conversion device.
The solid-state imaging device according to any one of Claims 1 to 19,

wherein thecircuit further comprises a source follower device electrically connected to the floating diffusion, and a row-select device electrically connected to the source follower device.
The solid-state imaging device according to any one of Claims 1 to 20,

wherein on the first side of the photoelectric conversion part, the second sub-area at least comprises a first area surface and a second area surface placed apart from the first area surface, at least part of the first sub-area contacts with the first area surface, and at least part of the first sub-area contacts with the second area surface, and

wherein the first charge transfer gate device disposed in at least the first area surface, and the second charge transfer gate device disposed in at least the second area surface..
An electronic apparatus comprising:

a solid-state imaging device according to any one of Claims 1 to 21.