JP2019068373A - Solid state image sensor, manufacturing method of solid state image sensor, and electronic equipment - Google Patents

Abstract

To provide a solid state image sensor capable of including a global shutter function in the case of backside-illumination, and inhibiting sensitivity deterioration even when a horizontal overflow structure is employed, and to provide a manufacturing method thereof, and electronic equipment.SOLUTION: A solid state image sensor 100 has a photodiode part of photosensitive section and a light shield 2150, as a charge transfer part, for shielding vertical CCD substantially completely, so that a global shutter function can be provided in the case of backside-illumination. The light shield 2150 is formed as DTI in at least a p-type separation layer of second conductivity type, and is formed to block incoming radiation of light at least to the element region of a charge transfer path gate, especially to the n-semiconductor region. Fundamentally, the light shield 2150 is constituted of a first embedded light shield 2151, a second embedded light shield 2152, and a third non-embedded light shield 2153.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a solid-state imaging device using a photoelectric conversion element that detects light and generates charge, a method of manufacturing the solid-state imaging device, and an electronic device.

A charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor is put to practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates electric charge.
CCD image sensors and CMOS image sensors are part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones. Widely applied.

Although a CCD image sensor and a CMOS image sensor use a photodiode as a photoelectric conversion element, the transfer method of the photoelectrically converted signal charge is different.
In the CCD image sensor, signal charges are transferred to an output unit by a vertical transfer unit (vertical CCD, VCCD) and a horizontal transfer unit (horizontal CCD, HCCD), and then converted into an electrical signal and amplified.
On the other hand, in the CMOS image sensor, the charge converted for each pixel including the photodiode is amplified and output as a read signal.

  The basic configuration of the CCD image sensor will be described below.

  FIG. 1 is a diagram showing a basic configuration of an interline transfer (IT) type CCD image sensor.

An IT (Interline Transfer) type CCD image sensor 1 basically includes a photosensitive unit 2, a horizontal transfer unit (horizontal CCD) 3, and an output unit 4.
The photosensitive units 2 are arranged in a matrix, and vertically transfer the signal charges of the plurality of pixel units 21 and the plurality of pixel units 21 that convert incident light into signal charges of a charge amount according to the light quantity in units of columns. It has a vertical transfer unit (vertical CCD) 22 as a charge transfer unit shielded from light.
The horizontal CCD 3 sequentially transfers the signal charges of one line shifted from the plurality of vertical CCDs 22 horizontally in the horizontal scanning period.
The output unit 4 converts the transferred signal charge into a signal voltage, includes floating diffusion (FD: Floating Diffusion) which is a floating diffusion layer for charge detection, and outputs a signal obtained by the FD to a signal processing system (not shown). Do.

  In the IT type CCD image sensor 1, the vertical CCD functions as an analog memory, repeats line shifting and horizontal transfer of the horizontal CCD 3, and sequentially outputs signals (frame signals) of all pixels from the output unit 4.

  The IT type CCD image sensor 1 is capable of progressive reading (progressive scanning), but has a structure in which high-speed transfer is difficult because signal charges are transferred by the horizontal CCD 3.

  FIG. 2 is a diagram showing a basic configuration of a frame interline transfer (FIT) type CCD image sensor.

In the FIT (Frame Interline Transfer) type CCD image sensor 1A, the charge storage portion (storage portion) 5 shielded from light is disposed between the output stage of the vertical CCD 22 of the photosensitive portion 2 of the IT type CCD image sensor 1 and the horizontal CCD 3. Have the following configuration.
In the FIT type CCD image sensor 1A, the vertical CCDs 22 of the photosensitive unit 2 receiving the signal charges (bundles) from the pixel unit 21 simultaneously transfer all the signal charges to the storage unit 5 completely shielded by high speed frame transfer.

As described above, in the FIT type CCD image sensor 1A, since the signal charges read from the pixel section 21 in the photosensitive section 2 are simultaneously transferred to the storage section 5 by the vertical CCD 22, the IT type CCD image sensor 1 of FIG. Faster transfer is possible compared with.
However, since the FIT type CCD image sensor 1A forms the storage section 5, the chip area is about twice as large as that of the IT type CCD image sensor.

The basic configuration of the CCD image sensor has been described above.
The above-described CCD image sensor is characterized in that it is capable of global shutter readout which starts accumulation of photocharges simultaneously for all pixels.

  However, the IT type CCD image sensor 1 is capable of progressive reading, but has the disadvantage that high-speed transfer is difficult because the horizontal CCD 3 transfers signal charges.

  The FIT type CCD image sensor 1A is capable of high-speed transfer as compared to the IT type CCD image sensor 1, but the chip area is about twice as large as that of the IT type CCD image sensor because the storage section 5 is formed.

  On the other hand, a normal CMOS image sensor is capable of high-speed transfer of signals but has a disadvantage that it can not read out global shutters.

In addition, as described in Non-Patent Document 1, the CMOS image sensor that improves the defect that the global shutter can not be read realizes the global shutter in a strict sense because it is configured to select and read four pixels. It is not done.
As described above, since the CMOS image sensor can not strictly realize the global shutter and simultaneous readout can not be realized, it is difficult to completely eliminate the subject blurring at the time of moving object shooting.
In addition, in the CMOS image sensor, parasitic capacitance is increased by coupling pixels, which causes a decrease in detection gain.
Due to these things, in the CMOS image sensor, global shutter readout and readout gain are traded off, and it is difficult to connect and read out many pixels. In other words, the CMOS image sensor is limited in pixel addition.
In the CMOS image sensor, it is necessary to form a bump structure in the pixel array in order to form a laminated structure, which may lead to layout restrictions and deterioration of pixel characteristics such as dark current and white flaws.
In addition, CMOS image sensors have the disadvantage that kTC noise increases.

  Therefore, in order to solve these problems, a solid-state imaging device has been proposed that enables high-speed readout with a small chip area, has few layout restrictions, and can suppress deterioration of pixel characteristics such as white flaws. (See Patent Document 1).

This solid-state imaging device, as disclosed in Patent Document 1, includes a photosensitive unit including a plurality of charge transfer units for transferring signal charges of a plurality of photoelectric conversion elements arranged in a matrix in a row unit, and charge transfer Unit converts the transferred signal charge into an electrical signal and outputs the converted signal charge, a peripheral circuit unit that performs predetermined processing on the electrical signal by the converted output unit, and a peripheral circuit unit of the electrical signal by the converted output unit And a second substrate on which a peripheral circuit portion is formed.
Then, the first substrate and the second substrate are stacked, and the relay unit includes the conversion output unit formed on the first substrate and the peripheral circuit unit formed on the second substrate as a photosensitive region of the photosensitive unit. It is electrically connected by the connection part through the board outside.

Patent No. 6144425

ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3 “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160 dB Parasitic Light Sensitivity In-Pixel Storage Node”

However, in the solid-state imaging device described in Patent Document 1, since the transfer path is not completely shielded from light, and the transfer path has sensitivity when the back side is illuminated, it has a global shutter function. Is difficult.
In addition, in the case of the surface irradiation structure, when laminated, the through electrode passes through the light receiving unit, and the light receiving area is reduced, and an amplification unit for transmitting a signal to the second substrate and a transfer unit are provided. It is difficult to read blocks.
In addition, in the case of surface irradiation, the lateral overflow structure is accompanied by sensitivity degradation.

  The present invention enables high-speed readout with a small chip area, has few layout restrictions, and is capable of suppressing deterioration of pixel characteristics such as white flaws, as well as global shutter when backside illumination is performed. It is an object of the present invention to provide a solid-state imaging device capable of having a function, a method of manufacturing a solid-state imaging device, and an electronic device.

  In addition, according to the present invention, high-speed reading is possible with a small chip area, there are few layout restrictions, and deterioration of pixel characteristics such as white flaws can be suppressed, and surface irradiation structure and lamination are also possible. It is an object of the present invention to provide a solid-state imaging device capable of performing block readout even when being integrated, a method of manufacturing a solid-state imaging device, and an electronic device.

  In addition, the present invention adopts a horizontal overflow structure as well as enables high-speed reading with a small chip area, has few layout restrictions, and can suppress deterioration of pixel characteristics such as white defects. It is an object of the present invention to provide a solid-state imaging device, a method of manufacturing a solid-state imaging device, and an electronic device capable of suppressing sensitivity deterioration even in cases.

  A solid-state imaging device according to a first aspect of the present invention includes a plurality of photoelectric conversion units arranged in a matrix and a plurality of charge transfer path units transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows. A pixel cell having a photosensitive portion, the photosensitive portion being formed on a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side and separated by a separation layer The pixel cell includes a first conductivity type semiconductor layer formed to be embedded in the substrate, and the photoelectric conversion unit having a photoelectric conversion function and a charge storage function of received light, and the photoelectric conversion A second conductive separation layer formed on the side of the first conductive semiconductor layer of the semiconductor device, and the second conductive separation layer on the second substrate surface side of the second conductive separation layer and stored in the photoelectric conversion unit A charge transfer gate unit capable of transferring a signal charge, and the separation of the second conductivity type A charge transfer path gate portion capable of transferring the signal charges transferred by the charge transfer gate portion in the row direction or the column direction, and formed at least in the second conductive separation layer. And at least a light blocking portion for blocking light from entering the element region of the charge transfer path gate portion.

  A method of manufacturing a solid-state imaging device according to a second aspect of the present invention includes a plurality of photoelectric conversion units arranged in a matrix and a plurality of charge transfer paths transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows. And forming a photosensitive portion on the substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side. And forming the pixel cell separated by the separation layer, wherein the step of forming the pixel cell includes forming the first conductive type semiconductor layer so as to be embedded in the substrate and performing a photoelectric conversion function of the received light. And forming a photoelectric conversion part having a charge storage function, forming a second conductive separation layer on the side of the first conductive semiconductor layer of the photoelectric conversion part, and separating the second conductive separation. Is accumulated in the photoelectric conversion unit on the second substrate surface side of the layer Forming a charge transfer gate portion capable of transferring signal charges; and transferring the signal charges transferred by the charge transfer gate portion to the second substrate surface side of the second conductive separation layer in a row direction or a column direction Forming a transferable charge transfer path gate portion, and forming at least the second conductive separation layer a light shielding portion for blocking incidence of light to at least an element region of the charge transfer path gate portion; including.

  An electronic apparatus according to a third aspect of the present invention includes a solid-state imaging device, and an optical system for forming an image on a photosensitive portion of the solid-state imaging device, wherein the solid-state imaging devices are arranged in a matrix. The photosensitive unit includes a photoelectric conversion unit and a plurality of charge transfer path units for transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows, and the photosensitive unit includes a first substrate surface side; A pixel substrate formed on a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface and including pixel cells separated by a separation layer, wherein the pixel cells are formed to be embedded in the substrate (1) A second conductivity type formed on the side of the first conductivity type semiconductor layer of the photoelectric conversion portion including the conductivity type semiconductor layer, the photoelectric conversion function of received light and the charge storage function, and the photoelectric conversion portion A separation layer, and the second conductive separation layer formed on the second substrate surface side A charge transfer gate portion capable of transferring the signal charge stored in the photoelectric conversion portion, and a signal charge formed on the second substrate surface side of the second conductive separation layer and transferred by the charge transfer gate portion A charge transfer path gate portion capable of transferring in the row direction or column direction, and a light blocking portion formed in at least the second conductive separation layer and blocking light from entering at least the element region of the charge transfer path gate portion; ,including.

According to the present invention, it is possible to provide a global shutter function when backside illumination is performed.
Further, according to the present invention, it is possible to read out a block even in the case of lamination with a surface irradiation structure.
Further, according to the present invention, it is possible to suppress the sensitivity deterioration even when the horizontal overflow structure is adopted.
Further, according to the present invention, high-speed reading can be performed with a small chip area, and moreover, there are few layout restrictions, and deterioration of pixel characteristics such as white defects can be suppressed.

It is a figure which shows the basic composition of IT type | mold CCD image sensor. It is a figure which shows the basic composition of a FIT type | mold CCD image sensor. It is a figure which expand | deploys and shows the structural example of the solid-state imaging device concerning the 1st Embodiment of this invention on a plane. It is a figure which shows typically the 1st example of the board | substrate laminated structure of the solid-state imaging device concerning this embodiment. It is a figure which shows typically the 2nd example of the board | substrate laminated structure of the solid-state imaging device concerning this embodiment. It is a figure for demonstrating the actual arrangement | positioning relationship of the photosensitive part of the 1st board | substrate and the peripheral circuit part of a 2nd board | substrate which are laminated | stacked in the solid-state imaging device concerning the 1st embodiment. It is a figure which shows an example of the layout of the pixel cell array which concerns on the 1st Embodiment of this invention. FIG. 8A is a simplified cross-sectional view and a potential diagram showing a configuration example of a main part of the pixel cell according to the first embodiment of the present invention, and is a simplified cross-sectional view and a potential diagram along the line aa of FIG. It is the simplified sectional view and potential diagram which show the structural example of the principal part of the pixel cell which concerns on the 1st Embodiment of this invention, Comprising: It is the simplified sectional view and potential diagram which followed the bb line of FIG. It is the simplified sectional view and potential diagram which show the structural example of the principal part of the pixel cell which concerns on the 1st Embodiment of this invention, Comprising: It is the simplified sectional view and potential diagram which followed the cc line of FIG. It is a figure which shows an example of the charge transfer of the pixel cell array which concerns on the 1st Embodiment of this invention. It is a figure showing an example of basic composition of a conversion output part concerning this embodiment. It is a figure which shows an example of the layout diagram and potential diagram of a pixel cell array containing the conversion output part which concerns on the 1st Embodiment of this invention. It is a simplified sectional view for explaining a schematic example of 1st composition of the 1st substrate and 2nd substrate which were laminated concerning this embodiment, and a relay part. It is a simplified sectional view for explaining a schematic example of 2nd composition of the 1st substrate and 2nd substrate which were laminated concerning this embodiment, and a relay part. It is a simplified sectional view for explaining the concrete example of composition of the 1st substrate and the 2nd substrate which were laminated concerning this embodiment, and a relay part. It is a simplified sectional view for explaining an example of composition of a solid-state imaging device concerning a 2nd embodiment of the present invention. It is a figure showing an example of a layout diagram and a potential diagram of a pixel cell array concerning a 3rd embodiment of the present invention. It is a figure which expand | deploys and shows a structural example of a part of solid-state imaging device concerning the 3rd Embodiment of this invention on a plane. It is a simplified sectional view for explaining an example of composition of a solid-state imaging device concerning a 4th embodiment of the present invention. It is a figure showing an example of composition of electronic equipment carrying a camera system to which a solid imaging device concerning an embodiment of the present invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First Embodiment
FIG. 3 is a plan view showing a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 4 is a view schematically showing a first example of the substrate stack structure of the solid-state imaging device according to the present embodiment.
FIG. 5 is a view schematically showing a second example of the substrate stack structure of the solid-state imaging device according to the present embodiment.
FIG. 6 is a view for explaining the actual arrangement relationship between the photosensitive portion of the first substrate and the peripheral circuit portion of the second substrate stacked in the solid-state imaging device according to the first embodiment.

An image sensor similar to, for example, a FIT (Frame Interline Transfer) type CCD image sensor can be applied to the solid-state imaging device 100.
However, the solid-state imaging device 100 does not have a charge storage unit (storage unit) and a horizontal transfer unit (HCCD) provided in a normal FIT type CCD image sensor.

Then, the solid-state imaging device 100 substantially completely shields the photodiode portion of the photosensitive portion and the vertical CCD as the charge transfer portion so as to be able to have a global shutter function when the back surface is illuminated, and thus parasitically It has a light shielding portion that suppresses the sensitivity.
The light shielding portion is formed as DTI (Deep Trench Isolation) in at least the second conductivity type (for example, p-type in this embodiment) separation layer, and light to at least the element region of the charge transfer path gate portion, particularly, the n − semiconductor region It is formed to block the incidence of

The solid-state imaging device 100 has a structure in which a first substrate 110, a second substrate 120, and a third substrate 130 are stacked.
In the solid-state imaging device 100, for example, as shown in FIGS. 4 and 5, the second substrate 120 is stacked on the third substrate 130, and the first substrate 110 is stacked on the second substrate 120. .
The substrates to be stacked are bonded, for example, as shown in FIG. 4 or joined by pressure bonding or micro bumps as shown in FIG.
The electrical connection between the substrates is realized by a through silicon via (TSV) 140 as a connection portion, a micro bump, and a bonding portion 150 such as pressure bonding.

  In the example of FIG. 4, electrical connection between each substrate is made through the through vias 140 penetrating the stacked first substrate 110, the second substrate 120, and the third substrate 130. The bump BMP is bonded to the exposed portion on the third substrate 130 side.

  In the example of FIG. 5, the through via 140-1 is formed in the first substrate 110, and the through via 140-2 is formed in the second substrate 120. The through via 140-1 of the first substrate 110 and the through via 140-2 of the second substrate 120 are bonded by a bonding portion 150 formed by pressure bonding or micro bumps. Then, the bonding pad 160 is bonded to the exposed portion on the upper surface side of the through via 140-1 of the first substrate 110.

In the present embodiment, on the first substrate 110, an imaging element unit 200 having a function of accumulating and transferring signal charges obtained by imaging and converting the signal charges into electric signals and outputting the electric signals is formed.
On the second substrate 120, a peripheral circuit unit 300 that performs predetermined processing on the electrical signal obtained by the imaging device unit 200 is formed.

  In FIG. 3 and FIG. 6, as the peripheral circuit unit 300 formed (mounted) on the second substrate 120, an analog electrical signal (analog) output from the first substrate 110 side and relayed by the relay unit 230 An analog-to-digital converter (ADC) 310 for converting data) into a digital signal (digital data) and a digital memory 320 for storing converted digital data are illustrated.

In the present embodiment, as the imaging device unit 200, a photosensitive unit 210 having an imaging function on the first substrate 110, and conversion for converting signal charges transferred in the column direction by the photosensitive unit 210 into electrical signals (voltage signals) An output unit 220 is formed.
In the present embodiment, the relay unit 230 for relaying the transfer of the electrical signal by the conversion output unit 220 to the peripheral circuit unit 300 between the first substrate 110 and the second substrate 120 is basically both substrates. Are formed over the

The solid-state imaging device 100 controls driving of the photosensitive unit 210, the conversion output unit 220, and the like, and performs signal processing and a power supply unit (hereinafter referred to as signal processing) that performs predetermined processing on the electrical signal output from the peripheral circuit unit 300. It has a processing unit 400).
The signal processing unit 400 of FIG. 3 includes a timing generator 410 formed of an FPGA or the like, an image processing circuit (image processing IC) 420, and a power supply circuit (power supply IC) 430.

  Note that the signal processing unit 400 including the timing generator 410, the image processing circuit (image processing IC) 420, and the power supply circuit (power supply IC) 430 is a separate substrate or the second substrate 120 or the third substrate 130. It is also possible to form it and to stack and mount it. This configuration also allows the small camera system to be incorporated into a single package.

The photosensitive portion 210 formed on the first substrate 110 includes a photoelectric conversion portion (pixel portion) 211 including a photodiode (PD) which is a photoelectric conversion element arranged in a matrix (m rows and n columns) shape, and a plurality of It includes vertical transfer units (vertical CCDs: VCCDs) 212 (-1 to -4) which are a plurality of charge transfer units for transferring signal charges of photoelectric conversion elements of the pixel unit 211 in units of columns (or rows).
In the photosensitive unit 210, the vertical transfer unit 212 is shielded by a light shielding unit (not shown), is transfer-driven by a transfer pulse such as two or four phases by the signal processing unit 400, and transfers signal charges by the pixel unit 211 in the column direction. .

3 and 6, in order to simplify the drawings, photoelectric conversion units (pixel units 9211 and vertical transfer units 212 are formed in a matrix of six rows and four columns (m = 6, n = 4 matrix) An example is shown where it is deployed.
In FIGS. 3 and 6, four columns of vertical transfer units 212-1 to 212-4 are arranged.
Then, the vertical transfer units 212-1 to 212-4 transfer signal charges in the Y direction of the orthogonal coordinate system shown in FIGS. 3 and 6.

(Example of structure of pixel cell)
In the first embodiment, as described above, the photosensitive unit 210 includes the plurality of photoelectric conversion units 211 arranged in a matrix and the vertical CCDs 212 which are a plurality of charge transfer units. Specifically, the pixel cells PXLC including the photoelectric conversion unit 211 and a part of the vertical CCD 212 are arranged in a matrix.

  FIG. 7 is a view showing an example of the layout of the pixel cell array according to the first embodiment of the present invention.

FIGS. 8A to 8D are a simplified cross-sectional view and a potential diagram showing an example of the configuration of the main part of the pixel cell according to the first embodiment of the present invention, and are taken along line aa of FIG. A simplified cross-sectional view and a potential diagram.
FIG. 8A shows a simplified cross-sectional view.
FIG. 8B shows an accumulation state in which the charge transfer gate portion 2140 and the charge transfer path gate portion 2120 are controlled to be nonconductive.
FIG. 8C shows a first reading state in which the charge transfer gate unit 2140 and the charge transfer path gate unit 2120 are controlled to be conductive.
FIG. 8D shows a second reading state in which the charge transfer gate unit 2140 is controlled to be nonconductive and the charge transfer path gate unit 2120 is controlled to be conductive.

9 (A) to 9 (D) are a simplified cross-sectional view and a potential diagram showing a configuration example of the main part of the pixel cell according to the first embodiment of the present invention, and taken along the line b-b of FIG. A simplified cross-sectional view and a potential diagram.
FIG. 9A shows a simplified cross-sectional view.
FIG. 9B shows a state in which the gates 2122 and 2124 of the charge transfer path gate unit 2120 are controlled to be nonconductive and the gate 2123 is controlled to be conductive.
FIG. 9C shows a first vertical transfer state in which the gate 2122 of the charge transfer path gate unit 2120 is controlled to be nonconductive and the gates 2123 and 2124 are controlled to be conductive.
FIG. 9D shows a second vertical transfer state in which the gates 2122 and 2123 of the charge transfer path gate unit 2120 are controlled to be nonconductive and the gates 2122 and 2124 are controlled to be conductive.

10 (A) to 10 (D) are a simplified cross-sectional view and a potential diagram showing a configuration example of the main part of the pixel cell according to the first embodiment of the present invention, and taken along the line c-c in FIG. A simplified cross-sectional view and a potential diagram.
FIG. 10A shows a simplified cross-sectional view.
FIG. 10B shows an accumulation state in which the lateral overflow gates 2181 and 2182 are controlled to be nonconductive.
FIG. 10C shows a global reset state in which the lateral overflow gates 2181 and 2182 are controlled to be conductive.
FIG. 10D shows a global reset state in which the lateral overflow gate 2181 is controlled to be nonconductive and the lateral overflow gate 2182 is controlled to be conductive.

FIGS. 11A to 11E are diagrams showing an example of charge transfer of the pixel cell array according to the first embodiment of the present invention.
11A shows an accumulation state, FIG. 11B shows a first readout state, FIG. 11C shows a second readout state, and FIG. 11D shows a first vertical transfer. FIG. 11E shows the second vertical transfer state.

  In FIG. 7, in order to simplify the drawing, a matrix of eight pixel cells PXLC00, PXLC01, PXLC10, PXLC11, PXLC20, PXLC21, PXLC30, and PXLC31 in four rows and two columns (m = 4, n = 2 An example of arranging in a matrix) is shown.

  Each pixel cell PXLC forming the photosensitive portion 200 has a first substrate surface 1101 side (for example, the back surface side) to which light L is irradiated, and a second substrate surface 1102 side facing the first substrate surface 1101 side and Are formed on a substrate (in this example, the first substrate 110) and separated by the separation layer 2130.

  In the pixel cell PLXC of this example, the photodiode 2110 forming the photoelectric conversion unit 211, the charge transfer path gate unit 2120 forming a part of the vertical CCD 212, the separation layer 2130, the charge transfer gate unit 2140, the light shielding unit 2150, A color filter unit 2160 and a microlens (ML) 2170 are included.

(Configuration of photodiode)
The photodiode 2110 is a first conductive type formed to be embedded in a semiconductor substrate having a first substrate surface 1101 side and a second substrate surface 1102 opposite to the first substrate surface 1101 side (this The embodiment includes an n-type semiconductor layer (n layer in this embodiment) 2111 and is formed to have a photoelectric conversion function and a charge storage function of received light.
A second conductivity type (p-type in this embodiment) separation layer 2130 is formed on the side portion in the direction (X direction) orthogonal to the normal to the substrate of the photodiode 2110.

As described above, in the present embodiment, the embedded photodiode (PPD) is used as the photodiode (PD) in each pixel PXLC.
Since surface states due to defects such as dangling bonds exist on the surface of the substrate forming the photodiode (PD), a large amount of charge (dark current) is generated by thermal energy, and the correct signal can not be read out.
In the embedded photodiode (PPD), it is possible to reduce the mixing of dark current into a signal by embedding the charge storage portion of the photodiode (PD) in the substrate.

In the photodiode 2110 of FIG. 8, the n layer (first conductive type semiconductor layer) 2111 is configured to have a three-layer structure in the normal direction of the substrate 110 (the Z direction of the orthogonal coordinate system in the figure). There is.
In this example, an n--layer 2112 is formed on the first substrate surface 1101 side, and an n--layer 2113 is formed on the second substrate surface 1102 side of the n--layer 2112. An n − layer 2114 is formed on the second substrate surface 1102 side of 2113, and ap + layer 2115 is formed on the second substrate surface 212 side of the n − layer 2114.
In addition, the p + layer 2116 is formed on the first substrate surface 1101 side of the n − − − layer 2112.
The p + layer 2116 is uniformly formed not only over the photodiode 2110 but also over the separation layer 2120 and further the other pixel cells PXLC.

  A color filter portion 2160 is formed on the light incident side of the P + layer 2116, and further corresponds to a part of the photodiode 2110 and the separation layer 2130 on the light incident side of the color filter portion 2160. The micro lens 2170 is formed on the

  These configurations are examples, and may be a single layer structure, or may be a laminated structure of two layers or four or more layers.

(Configuration of separation layer in X direction (column direction))
In the p-type separation layer 2130 in the X direction (column direction) in FIG. 8, a direction in contact with the n layer 2111 of the photodiode 2110 and orthogonal to the normal of the substrate (X direction of orthogonal coordinate system in the drawing) The first p layer (second conductive type semiconductor layer) 2131 is formed on the right side of the second layer.
Furthermore, in the p-type separation layer 230, the second p layer (second conductivity type semiconductor layer) 2132 is on the right side of the first p layer 2131 in the X direction, and the normal direction (orthogonal in the figure) of the substrate 110. It is configured to have a two-layer structure in the Z direction of the coordinate system.
In this example, in the second p layer 2132, the p layer 2133 is formed on the first substrate surface 1101 side, and the p − layer 2134 is formed on the second substrate surface 1102 side of the p layer 2133.

  These configurations are an example, and may be a single layer structure, or may be a laminated structure of three layers or four or more layers.

  A p + layer 2116 similar to the photodiode 2110 is formed on the first substrate surface 1101 side of the first p layer 2131 and the second p layer 2132 of the p type separation layer 2130.

A charge transfer gate portion 2140 is formed on the second substrate surface 1102 side of the first p layer 2131 of the p type separation layer 2130.
A gate 2141 is formed on the second substrate surface 1102 side of the first p layer 2131 of the p-type isolation layer 2130 via a gate insulating film.

  The charge transfer gate unit 2140 is controlled to be conductive (on) and non-conductive (off) in accordance with the control signal TG supplied to the gate 2141, and the signal charge stored in the photodiode 2110 is controlled during the conductive state. Transfer to the charge transfer path gate unit 2120.

A charge transfer path gate portion 2120 is formed on the second substrate surface 1102 side of the second p layer 2132 of the p type separation layer 2130.
On the second substrate surface 1102 side of the second p layer 2132 of the p type separation layer 2130, an n − layer 2121 which is a first conductivity type semiconductor layer is formed to extend in the Y direction.
Then, as shown in FIGS. 8 and 9, on the second substrate surface 1102 side of the second p layer 2132 of the p-type isolation layer 2130, the gates 2122 (V1) and 2123 (V2) via the gate insulating film. , 2124 (V3) are formed in the Y direction.

  The charge transfer path gate unit 2120 is controlled to be conductive (on) and non-conductive (off) according to control signals V1, V2, and V3 supplied to the gates 2122, 2123, and 2124. The signal charges transferred in the Y direction of the CCD 212 are transferred to the charge transfer path gate unit 2120 of the next stage.

(Structure of the light shield)
In each pixel cell PXLC, the light shielding portion 2150 is at least in the second conductivity type separation layer 2130 so as to block the incidence of light on the charge transfer path gate portion 2120, particularly the n− layer 2121 as an element region. It is formed.
Preferably, it is formed outside the substrate on the side of the first substrate surface 1101 of the substrate 110 so as to cooperate with the light shielding portion in the second conductive separation layer 2130.

  The light shielding portion 2150 shown in FIG. 8 basically includes a first embedded light shielding portion 2151, a second embedded light shielding portion 2152, and a third non-embedded light shielding portion 2153.

  The first embedded light shielding portion 2151 is the second conductive separation layer 2130 within the element region width in which the charge transfer gate portion 2140 is formed, and more specifically, the first p layer of the second conductive separation layer 2130. At 2131, it is formed as DTI (Deep Trench Isolation) embedded in the depth direction (Z direction) from the first substrate surface 1101 side toward the second substrate surface 1102 side.

  The second embedded light shielding portion 2152 is the second conductive separation layer 2130 adjacent to the pixel cell outside the element region width where the charge transfer path gate portion 2120 is formed, specifically, the second conductive separation layer The second p layer 2132 of 2130 is formed as a DTI embedded in the depth direction (Z direction) from the first substrate surface 1101 side toward the second substrate surface 1102 side.

  The first buried light shielding portion 2151 and the second buried light shielding portion 2152 are formed of a light shielding material, for example, W (tungsten), Al (aluminum), Cu (copper) or the like.

The third non-embedded light shielding portion 2153 is a charge transfer path gate which is sandwiched between the first embedded light shielding portion 2151 and the second embedded light shielding portion 2152 in the X direction outside the substrate on the first substrate surface 1101 side of the substrate 110. It is formed to face the first p layer 2131 and the second p layer 2132 on the first substrate surface 1101 side of the second conductive separation layer 2130 in the element region where the portion 2120 is formed.
In the present embodiment, the third non-embedded light shielding portion 2153 is a grid which is arranged on the light irradiation side and is embedded in the color filter portion 2160 in the boundary portion of the microlens 2170 of the adjacent pixel cell PXLC to be long in the X direction. It is also used as (Grid).

Since the light shielding portion 2150 having the above configuration is provided, most of the light condensed by the microlens 2170 in the light L irradiated from the first substrate surface 1101 side (for example, the back surface side) is a pixel The light is incident on the photodiode 2110 of the cell PXLC, photoelectrically converted and accumulated.
In addition, the light which is condensed by the microlens 2170 obliquely at a large angle and is incident on the separation layer 2130 side is the second embedded light shielding of the separation layer 2130 of the pixel cell PXLC adjacent on the left side in FIG. The light is reflected by the portion 2152 and the incidence of the irradiation light to the n − layer 2121 as the element region of the charge transfer path gate portion 2120 is blocked. Then, the irradiation light is reflected by the second embedded light shielding portion 2152 so as to return to the photodiode 2110, is photoelectrically converted, and is accumulated as a signal charge.
Similarly, the light which is condensed by the microlens 2170 and is obliquely incident at a large angle and is incident on the separation layer 2130 side is the first embedded light shielding portion 2151 of the separation layer 2130 of the self-pixel cell PXLC in FIG. Thus, the incident light to the n− layer 2121 as the element region of the charge transfer path gate portion 1120 is blocked. Then, the irradiation light is reflected by the first embedded light shielding portion 2151 so as to return to the photodiode 2110, is photoelectrically converted, and is accumulated as a signal charge.
The third non-embedded light-shielding portion 2153 prevents the light L emitted toward the separation layer 2130 from being incident on the separation layer 2130, in particular, to the n− layer 2121 as an element region of the charge transfer path gate portion 2120. Be done.

As described above, the light to be emitted is reflected back to the photodiode 2110 by the first embedded light shielding portion 2151 and the second embedded light shielding portion 2152 formed in the separation layer 2130, and also to the separation layer 2130. The light L emitted toward the light is reflected by the third non-embedded light shielding portion 2153, and the incident light to the n− layer 2121 as an element region of the charge transfer path gate portion 1120 is blocked.
As a result, the vertical CCD 212, which is a charge transfer path, is prevented from having sensitivity, and it becomes possible to have a global shutter function. Further, the irradiation light is transmitted to the first embedded light shielding portion 2151 and the second embedded light shielding portion Since the light is reflected back to the photodiode 2110 by the light source 2152 and used as a stored charge, an efficient photoelectric conversion function can be realized.

(Horizontal overflow drain structure)
The solid-state imaging device 10 according to the first embodiment can be back-illuminated and can suppress sensitivity deterioration. Therefore, the signal charge overflowing from the photodiode 2110 that is a photoelectric conversion unit is possible. Lateral Overflow Drain structure is adopted.

In the first embodiment, as shown in FIGS. 7 and 10, two pixel cells PXLC adjacent in the Y direction (row direction) are configured to share one horizontal overflow drain portion 2180. .
In the example of FIG. 7, pixel cells PXLC00 and PXLC10, pixel cells PXLC01 and PXLC11, pixel cells PXLC20 and PXLC30, and pixel cells PXLC21 and PXLC31 are configured to share one lateral overflow drain portion 2180. There is.

  The lateral (horizontal) overflow drain portion 2180 of the first embodiment is formed in the pixel cell PXLC adjacent in the Y direction, and in the example of FIG. 10, in the separation layer 2130 Y in the Y direction separating the pixel cells PXLC00 and PXLC10. There is.

(Configuration of separation layer in Y direction (column direction))
In the p-type separation layer 2130Y in the Y direction (column direction) of FIG. 10, the second p layer (second conductivity type semiconductor layer) 2132Y is in the normal direction of the substrate 110 (the Z direction of the orthogonal coordinate system in the drawing). ) Is configured to have a two-layer structure.
In this example, in the second p layer 2132Y, the p layer 2133Y is formed on the first substrate surface 1101 side, and the p − layer 2134Y is formed on the second substrate surface 1102 side of the p layer 2133.

  These configurations are an example, and may be a single layer structure, or may be a laminated structure of three layers or four or more layers.

The gate electrode is formed on the second substrate surface 1102 side of the second p layer 2132 of the p-type separation layer 2130Y in the Y direction on the pixel cell PXLC 00 side of the lateral overflow gate portion 2180-00 on the pixel cell PXLC 00 side. A lateral overflow gate 2181 is formed which forms a part.
On the second substrate surface 1102 side on the pixel cell PXLC01 side of the second p layer 2132 of the p-type separation layer 2130Y in the Y direction, a gate insulating film is interposed to form lateral overflow gate portion 2180-10 on the pixel cell PXLC01 side. A lateral overflow gate 2182 is formed which forms part.
Then, an n − layer 2183 which is a first conductivity type semiconductor layer as a lateral overflow drain is formed on the second substrate surface 1102 side of the second p layer 2132 between the lateral overflow gates 2181 and 2182. There is.
The lateral (lateral) overflow drain portion 2180 is controlled to be conductive (on) and non-conductive (off) according to control signals LO supplied to the lateral overflow gates 2181 and 2182, and the photodiode 2110 is turned on. Drain the signal charge that overflows from the

(Structure of the light shielding portion related to the separation layer 2130Y in the Y direction)
In each pixel cell PXLC, the light blocking portion 2150 associated with the separation layer 2130Y in the Y direction blocks incident light to at least the lateral (lateral) overflow drain portion 2180, particularly the n− layer 2183 as an element region, It is formed in at least the second conductive separation layer 2130Y.
Preferably, it is formed outside the substrate on the side of the first substrate surface 1101 of the substrate 110 so as to cooperate with the light shielding portion in the second conductive separation layer 2130Y.

  The light shielding portion 2150Y shown in FIG. 10 is basically the fourth embedded light shielding portion 2154 corresponding to the first embedded light shielding portion 2151 and the second embedded light shielding portion 2152, similarly to the light shielding portion 2150 shown in FIG. 2155 and a third non-embedded light shielding portion 2156 (corresponding to the third non-embedded light shielding portion 2153 in FIG. 8).

  The fourth embedded light shielding portion 2154 is a second conductive separation layer 2130 Y within the element region width in which the lateral overflow gate 2181 forming a part of the lateral overflow gate portion 2180-00 on the pixel cell PXLC 00 side, specifically Specifically, in the second p-layer 2132 of the second conductive separation layer 2130Y, it is formed as a DTI embedded in the depth direction (Z direction) from the first substrate surface 1101 to the second substrate surface 1102 side. It is done.

  The fourth embedded light shielding portion 2155 is a second conductivity type separation layer 2130 Y in the element region width in which the lateral overflow gate 2182 which forms a part of the lateral overflow gate portion 2180-10 on the pixel cell PXLC 01 side, Specifically, in the second p-layer 2132 of the second conductive separation layer 2130Y, it is formed as a DTI embedded in the depth direction (Z direction) from the first substrate surface 1101 to the second substrate surface 1102 side. It is done.

The fourth embedded light shielding portions 2154 and 2154 are formed of a light shielding material, for example, W (tungsten), Al (aluminum), Cu (copper) or the like.
Alternatively, a similar shielding effect can be obtained with polysilicon or a high refractive index material, for example, a ferroelectric film such as TaO.

The third non-embedded light shielding portion 2156 is formed with an n + layer 2183 as a lateral overflow drain sandwiched in the Y direction by the fourth buried light shielding portions 2154 and 2155 outside the substrate on the first substrate surface 1101 side of the substrate 110 It is formed to face the second p layer 2132Y on the first substrate surface 1101 side of the second conductive separation layer 2130 in the element region.
In this embodiment, the third non-embedded light shielding portion 2156 is arranged on the light irradiation side, and is embedded in the boundary portion of the microlens 2170 of the adjacent pixel cell PXLC so as to be long in the color filter portion 2160 in the Y direction. It is also used as (Grid).

Since the light shielding portion 2150Y having the above configuration is provided, most of the light condensed by the microlens 2170 in the light L irradiated from the first substrate surface 1101 side (for example, the back surface side) is a pixel The light is incident on the photodiode 2110 of the cell PXLC, photoelectrically converted and accumulated.
In addition, the light which is condensed by the microlens 2170 and is obliquely incident at a large angle and is incident on the separation layer 2130 side is the fourth embedded light shielding of the separation layer 2130 of the pixel cell PXLC adjacent on the left side in FIG. The light is reflected by the portion 2155, and the incident light to the n + layer 2183 as an element region of the lateral overflow drain portion is blocked. Then, the irradiation light is reflected by the fourth embedded light shielding unit 2155 so as to return to the photodiode 2110, is photoelectrically converted, and is accumulated as a signal charge.
Similarly, the light which is condensed by the microlens 2170 and is obliquely incident at a large angle and is incident on the separation layer 2130 side is the fourth embedded light shielding portion 2154 of the separation layer 2130 Y of the self-pixel cell PXLC in FIG. Thus, the incident light on the n + layer 2183 as an element region of the lateral overflow drain portion is blocked. Then, the irradiation light is reflected by the second embedded light shielding portion 2154 so as to return to the photodiode 2110, is photoelectrically converted, and is accumulated as a signal charge.
In addition, the light L emitted toward the separation layer 2130 Y is incident on the separation layer 2130 Y by the third non-embedded light shielding portion 2156, particularly, the n + layer 2183 as an element region of the lateral (lateral) overflow drain portion 2180. It is blocked.

Thus, the light to be irradiated is reflected by the fourth embedded light shielding portions 2154 and 2155 formed in the separation layer 2130 Y so as to return to the photodiode 2110, and the light to be emitted toward the separation layer 2130. L is reflected by the third non-embedded light shielding portion 2156, and the incident light to the n + layer 2183 as an element region of the lateral overflow drain portion is blocked.
Thereby, the sensitivity deterioration of the lateral overflow drain portion 2180 is suppressed, and it becomes possible to have a global shutter function, and the irradiation light is reflected so as to return to the photodiode 2110 by the fourth embedded light shielding portions 2154 and 2155. Since it is used as stored charge, it is possible to realize an efficient photoelectric conversion function.

(Configuration of conversion output unit)
The conversion output unit 220 formed on the first substrate 110 converts the signal charges transferred by the plurality of vertical transfer units 212-1 to 212-n (n = 4 in this example) of the photosensitive unit 210 into electric signals. And output to the relay unit 230.
The conversion output unit 220 includes four conversion output units 220-1 to 220 corresponding to the vertical transfer units 212-1 to 212-4 of n (in this example, 4) columns formed on the first substrate 110. -4 is arranged.

FIG. 12 is a diagram showing a basic configuration example of the conversion output unit according to the present embodiment.
FIG. 12 shows a configuration example of the conversion output unit 220-1 of one column, but conversion output units 220-2 to 220-4 of other columns also have the same configuration as that of FIG.

13A to 13D are diagrams showing an example of a layout diagram and a potential diagram of a pixel cell array including a conversion output unit according to the first embodiment of the present invention.
FIG. 13A shows a layout diagram.
FIG. 13B shows the FD reset state in which the gate 2122 and the output gate 213 of the charge transfer path gate unit 2120 are in a non-conductive state, and the gate 2123 and the reset gate (RG) 222 are controlled in a conductive state.
FIG. 13C shows an FD reset state in which the gate 2122 of the charge transfer path gate unit 2120, the output gate 213, and the reset gate (RG) 222 are controlled to be nonconductive and the gate 2123 is controlled to be conductive.
FIG. 13D shows a reading state in which the gates 2122 and 2123 and the reset gate (RG) 222 of the charge transfer path gate unit 2120 are controlled to be nonconductive and the output gate 213 is controlled to be conductive.

The conversion output unit 220-1 is connected to the output gate OG 213-1 at the output end 213-1 of the vertical transfer unit 212-1.
The conversion output unit 220-1 in FIGS. 12 and 13A includes a floating diffusion (FD: floating diffusion layer) 221, a reset gate (RG) 222, and a reset drain 223.

In the conversion output unit 220-1, a reset drain voltage VRD (VDD) is applied to the reset drain 223, and a reset pulse PRG is applied to the reset gate 222 in a detection cycle of signal charges.
Then, the signal charge stored in the floating diffusion 221 is converted into a signal voltage which is an electric signal, and is sent to the relay unit 230 as a CCD output signal SOUT.

  The relay unit 230 is a second one of the electrical signals transferred by the plurality of vertical transfer units 212 of the photosensitive unit 210 formed on the first substrate 110 and converted into each of the conversion output units 220-1 to 220-4. The transfer to the peripheral circuit unit 300 formed on the substrate 120 is relayed.

The relay unit 230 according to the first embodiment includes, as an example, the conversion output units 220-1 to 220-4 formed on the first substrate 110 and the peripheral circuit unit 300 formed on the second substrate 120. In the area EPARA outside the photosensitive area PARA of the photosensitive section 210, electrical connections are made by connection sections 231 (-1 to -4) passing through the substrate.
In the first embodiment, the connection parts 231-1 to 231-4 are formed by, for example, micro bumps or through vias (TSVs). In the following description, the connection portion may be referred to as a through via.

  In the present embodiment, as described below, in the relay unit 230, at least one of the regions corresponding to the outside of the photosensitive region of the first substrate 110 and the second substrate 120, the conversion output units 220-1 to 220. A source follower circuit is formed which amplifies the electrical signal of -4.

[Schematic Configuration Example of Stacked First Substrate and Second Substrate, and Relay Part]
Here, a schematic configuration example of the relay unit having the stacked first and second substrates and the source follower circuit will be described.

[First configuration example]
FIG. 14 is a simplified cross-sectional view for describing a schematic first configuration example of the stacked first and second substrates and the relay portion according to the present embodiment.

In the first configuration example, the source follower circuit 240 is formed on the first substrate 110A and the second substrate 120A.
The source follower circuit 240 includes an amplifying unit 241 and a current source unit 242 connected in series between the power supply unit OD and the reference potential.

  The amplification unit 241 and the current source unit 242 are formed of MOSFETs, and the gate of the MOSFET forming the amplification unit 241 forms the input end TI 240 of the source follower circuit 240, and the connection side (source side) with the current source unit 242 An output end TO 240 of the source follower circuit 240 is formed.

  In the first configuration example, the amplification unit 241 of the source follower circuit 240 is formed on the first substrate 110A, and the current source unit 242 is formed on the second substrate 120A.

In the relay unit 230A, the floating diffusion (FD) 221 of the conversion output unit 220A formed on the first substrate 110A and the input end (gate) TI 240 of the amplification unit 241 of the source follower circuit 240 are connected. The output terminal TO 240 of the amplification unit 241 and the current source unit 242 formed on the second substrate 120 A are connected via the connection unit 231.
Then, the source follower circuit 240 outputs the signal amplified from the output terminal TO 240 side of the amplification unit 241 connected to the current source unit 242 to the peripheral circuit unit 300.

In this example, basically, in the pixel unit 211, the vertical transfer unit (vertical CCD) 212 is adjacent, and progressive reading is possible.
Further, the source follower circuit 240 is disposed corresponding to the vertical transfer unit (vertical CCD) 212, and the peripheral circuit unit 300 including the ADC 310 and the digital memory 320 is disposed on the second substrate 120A. The read out signal charges can be transferred to the memory at high speed while maintaining the synchronization.
In the example of FIG. 14, an amplifier (amplifier) 330 that amplifies the output signal of the source follower circuit 240 is connected to the input stage of the ADC 310 in the second substrate 120A.

[Second configuration example]
FIG. 15 is a simplified cross-sectional view for describing a schematic second configuration example of the stacked first and second substrates and the relay portion according to the present embodiment.

The difference between this second configuration example and the first configuration example described above is as follows.
In the second configuration example, a sample and hold circuit 340 is disposed on the output side of the amplifier 330 in place of the ADC on the second substrate 120B.

Also in this example, basically, in the pixel unit 211, the vertical transfer unit (vertical CCD) 212 is adjacent, and progressive reading is possible.
Note that by providing the amplifier 330 as a line buffer unit separately from the floating diffusion (FD) 221, it is possible to suppress a decrease in detection sensitivity due to a decrease in capacitance of the FD unit.

[Specific Configuration Example of Stacked First Substrate and Second Substrate, and Relay Part]
Here, a specific configuration example of the first substrate 110C, the second substrate 120C, and the relay portion in the third configuration example outlined above will be described.

FIG. 16 is a simplified cross-sectional view for describing a specific configuration example of the stacked first and second substrates and the relay unit according to the present embodiment.
FIG. 16 shows a portion corresponding to the vertical transfer unit 212 in one column and the conversion output unit 220 and the relay unit 230 corresponding thereto.
The solid-state imaging device 10C according to the first embodiment is configured as a back-illuminated image sensor to which light L is emitted from the first substrate surface 1101 side (back surface side) of the first substrate 110C. It has a laminated structure in which the second substrate surface 1102 side (surface side) of 110 C and the front surface side of the second substrate 120 C are bonded.

In the present embodiment, the first substrate 110C is formed of a first conductivity type substrate, for example, an n-type substrate 111, and the second substrate 120C is formed of a second conductivity type substrate, for example, a p-type substrate 121.
In the first substrate 110 </ b> C, the p well (p-WELL) 112 is formed in the n-type substrate (n-SUB) 111, and the n ⁻ layer 113 is formed on the surface of the p well 112.
An array of the pixel cells PXLC described above is formed in the regions of the n-type substrate (n-SUB) 111 and the p-well (p-WELL) 112.
At one end of the n ⁻ layer 113 in the Y direction, an n ⁺ layer 114-1 is formed as a drain of the transistor for the amplification unit 241 of the source follower circuit 240. The n ⁺ layer 114-1 is formed to be connected to the through via 141-1 as a relay portion via the wiring layer WR.
A transfer electrode (transfer gate) 116-1 of the vertical transfer portion 212 and a gate electrode 116-2 for the amplification portion 241 are formed at predetermined intervals on the n ⁻ layer 113 via the gate insulating film 115. ing.
Then, an insulating film 117 is formed on the n-type substrate 111, the p well 112, the n ^- layer 113, the n ⁺ layer 114-1, the gate insulating film 115, and the transfer electrodes 116-1 and 16-2. It is done.

A penetrating via (penetrating electrode) 141-1 is formed (embedded) penetrating the insulating film 117 and joining the penetrating via 142-1 on the side of the second substrate 120C to be described later and the bonding portion 151. .
An insulating film 118 is formed on the wall of the p-well 112 and the n-type substrate 111 in which the through vias 141-1 are formed.
Bonding pads 161-1 and 161-2 are connected to the ends of the through vias 141-1. The bonding pad 161-2 is disposed outside the surface of the first substrate 110C facing the second substrate 120C, and is connected to the through via 242-1 on the second substrate 1120C side by the bonding portion 151. It is joined with -1.

In the second substrate 120C, an n well (n-WELL) 122 is formed in a p-type substrate (p-SUB) 121, and a p well (p-WELL) 123 is formed in the n well 122. The p ⁺ layer 124-1 and the n ⁺ layers 125-1 and 125-2 serving as the drain and source of the transistor for the current source portion 242 of the source follower circuit 240 are formed on the surface of the p well 123.
In the example of FIG. 13, the n ⁺ layer 125-2 is formed to be connected to the through via 141-2 as a relay portion via the wiring layer WR.
In the example of FIG. 14, the n ⁺ layer 125-2 is formed to be connected by the through via 141-2 or the wiring layer WR immediately below the bonding pad 162-1 as a relay portion.
In addition, p ⁺ layers 124-2 and 142-3 for forming a peripheral circuit, an n ⁻ layer 126 and the like are formed on the surface portion of the n well 122.
A gate electrode 128 is formed on the upper portions of the n ⁺ layers 125-1 and 125-2 and the p ⁺ layers 124-2 and 142-3 with the gate insulating film 127 interposed therebetween.
The p-type substrate 121, the n well 122, the p well 123, the p ⁺ layers 124-1, 124-2, 142-3, the n ⁺ layers 125-1, 125-2, the n ⁺ layer 126, the gate insulating film 127 An insulating film 129 is formed on the gate electrode 128 and the like so as to cover them.

  Further, in the example of FIG. 16, the through vias 142-1 and 142-2 penetrating the first substrate 110 </ b> C and the second substrate 120 </ b> C are formed.

As described above, according to the first embodiment, the first substrate 110 includes the pixel portion 211 including the photodiode (PD) which is a photoelectric conversion element arranged in a matrix, and a plurality of pixel portions A photosensitive unit 210 including a vertical transfer unit 212 which is a plurality of charge transfer units for transferring the signal charges of the photoelectric conversion element 211 in units of columns is formed.
Furthermore, on the first substrate 110, at the output end of the vertical transfer unit 212, the conversion output unit 220 converts signal charges into electric signals and outputs the electric signals for each vertical transfer unit (or for each of a plurality of vertical transfer units). Is formed.
Then, the solid-state imaging device 100 substantially completely shields the photodiode portion of the photosensitive portion and the vertical CCD as the charge transfer portion so as to be able to have a global shutter function when the backside is illuminated. It has 2150.
The light shielding portion 2150 is formed as DTI in at least the p-type separation layer of the second conductivity type, and is formed to block the incidence of light on at least the element region of the charge transfer path gate portion, in particular, the n − semiconductor region. ing.
Preferably, it is formed outside the substrate on the side of the first substrate surface 1101 of the substrate 110 so as to cooperate with the light shielding portion in the second conductive separation layer 2130.
The light shielding portion 2150 basically includes a first embedded light shielding portion 2151, a second embedded light shielding portion 2152, and a third non-embedded light shielding portion 2153.

Therefore, according to the first embodiment, the irradiated light is reflected back to the photodiode 2110 by the first embedded light shielding portion 2151 and the second embedded light shielding portion 2152 formed in the separation layer 2130. The light irradiated toward the separation layer 2130 is reflected by the third non-embedded light shielding portion 2153, and the incident light is incident on the n-layer 2121 as an element region of the charge transfer path gate portion 1120. It is blocked.
As a result, the vertical CCD 212, which is a charge transfer path, is prevented from having sensitivity, and it becomes possible to have a global shutter function. Further, the irradiation light is transmitted to the first embedded light shielding portion 2151 and the second embedded light shielding portion Since the light is reflected back to the photodiode 2110 by the light source 2152 and used as a stored charge, an efficient photoelectric conversion function can be realized.

Further, according to the first embodiment, since backside irradiation can be performed and sensitivity deterioration can be suppressed, the signal charge overflowed from the photodiode 2110 which is a photoelectric conversion unit is discharged. A lateral overflow drain (Lateral Overflow Drain) structure is adopted.
Then, the light blocking portion 2150 related to the separation layer 2130Y in the Y direction is configured to block the incidence of light on at least the lateral (lateral) overflow drain portion 2180, particularly the n− layer 2183 as an element region in each pixel cell PXLC. , And at least in the second conductive separation layer 2130Y.
Preferably, it is formed outside the substrate on the side of the first substrate surface 1101 of the substrate 110 so as to cooperate with the light shielding portion in the second conductive separation layer 2130Y.
The light shielding portion 2150Y basically includes a first embedded light shielding portion 2151, fourth embedded light shielding portions 2154 and 2155 corresponding to the second embedded light shielding portion 2152, and a third non-embedded light shielding portion 2156. There is.

Therefore, according to the first embodiment, the irradiated light is reflected back to the photodiode 2110 by the fourth embedded light shielding portions 2154 and 2155 formed in the separation layer 2130Y, and the separation layer The light L emitted toward the light source 2130 is reflected by the third non-embedded light shielding portion 2156, and the incident light is prevented from being incident on the n + layer 2183 as an element region of the lateral overflow drain portion.
Thereby, the sensitivity deterioration of the lateral overflow drain portion 2180 is suppressed, and it becomes possible to have a global shutter function, and the irradiation light is reflected so as to return to the photodiode 2110 by the fourth embedded light shielding portions 2154 and 2155. Since it is used as stored charge, it is possible to realize an efficient photoelectric conversion function.

Further, according to the first embodiment, the output gate OG 213 is formed at the input stage of the conversion output unit 220, and the conversion output unit 220 includes the floating diffusion (FD) 221, the reset gate (RG) 222, and the reset drain. (RG) 223 is formed.
On the second substrate 120, peripheral circuits 300 such as an ADC 310, a digital memory 320, an amplifier 330, and a sample-and-hold circuit 340 are formed which perform predetermined processing on electric signals obtained by the imaging device 200. .
A relay unit 230 including a source follower circuit 240 relaying transfer of the electrical signal to the peripheral circuit unit 300 by the conversion output unit 220 between the first substrate 110 and the second substrate 120 basically covers both substrates. Or one of the substrates.
Then, the floating diffusion (FD) 221 or the line buffer unit of the conversion output unit 220 formed on the first substrate 110 is connected to the input end of the amplification unit 241 of the source follower circuit 240 by the relay unit 230, and the amplification unit 241 The output signal of is supplied to the peripheral circuit unit 300.
The connection between the first substrate 110 and the second substrate 120 is electrically connected by a connection part through the substrate in an area EPARA outside the photosensitive area PARA of the photosensitive part 210.

Therefore, according to the first embodiment, the following effects can be further obtained.
According to the first embodiment, progressive reading from the pixel unit 211 to the vertical transfer unit (vertical CCD) 212 is possible, and the signal charge read by progressive reading is converted into an electric signal by the conversion output unit 220. Then, they are transferred to the peripheral circuit unit 300 formed on the second substrate through the source follower circuit 240.
In this embodiment, the present embodiment can provide a progressive readout image sensor capable of high-speed transfer with high SN.
In addition, since the connection portion of the laminated substrate is formed outside the pixel array (outside the photosensitive region of the photosensitive portion 210), it is possible to form an image sensor with few layout restrictions and no deterioration in pixel characteristics such as white defects. Become.
In other words, according to the first embodiment, it is possible to realize an image sensor that can be driven at high speed by global readout without forming a special structure in the pixel array, that is, without causing deterioration of SN. It becomes.
Further, since the relay portion 230 including the connection portion is formed outside the pixel array, it is possible to form a pixel in which the occurrence of the decrease in sensitivity and the increase in dark current does not occur.

Second Embodiment
FIG. 17 is a simplified cross-sectional view for describing a configuration example of a solid-state imaging device according to a second embodiment of the present invention.

The difference between a solid-state imaging device 100D according to the second embodiment and the solid-state imaging device 100 according to the first embodiment described above is as follows.
The solid-state imaging device 100D according to the second embodiment is provided with a so-called phase difference detection function by making the adjacent pixel cells PXLC (left and right) asymmetric.

  The solid-state imaging device 100D according to the second embodiment includes the first pixel cell PXLC1 and the second pixel cell PXLC1 adjacent to each other with the charge transfer path gate portion 2120D forming a part of the vertical CCD 212 as one charge transfer path. It has a pixel cell PXLC2.

  The first pixel cell PXLC1 and the second pixel cell PXLC2 are adjacent to each other with one second conductivity type separation layer 2130D forming one charge transfer path interposed therebetween.

  In the first pixel cell PXLC1, the first photodiode 2110D1 has the first sensitivity, and the first charge transfer gate portion 2140D1 and the first charge transfer path gate portion 2120D1D are formed from the first photodiode 2110D1. It is formed on the second substrate surface 1102 side of one of the second conductive separation layers 2130D1 and 2130D3.

  In the second pixel cell PXLC2, the second photodiode 2110D2 has a second sensitivity different from the first sensitivity, and the second charge transfer gate unit 2140D2 and the second charge transfer path gate unit 2120D2 have a second sensitivity. It is formed on the second substrate surface 1102 side of one second conductive separation layer 2130D2, 2130D3 from the two photodiodes 2110D2.

The light shielding portion 2150D is embedded in the depth direction in the second conductive separation layers 2130D1 and 2130D2 in the element region width in which the first charge transfer gate portion 2140D1 and the second charge transfer gate portion 2140D2 are formed, respectively. And two fifth embedded light shields 2157.2158.
The light shielding portion 2150D is formed between the element regions in which the first charge transfer path gate portion 2120D1 and the second charge transfer path gate portion 2120D2 are formed, specifically, between the n− layers 2121D1 and 1211D2. The mold separation layer 2130D3 includes a sixth embedded light shielding portion 2159 embedded in the depth direction.
Further, in the light shielding portion 2150D, the charge transfer path gate portion 2120D1.2120D2 is formed at least between the fifth embedded light shielding portions 2157 and 2158 outside the substrate on the first substrate surface 1101 side of the first substrate 110D. And a third non-embedded light shielding portion 2159 formed to face the second conductive separation layer 2130D in the element region.

  According to the second embodiment, it is possible not only to obtain the same effect as that of the first configuration example described above but also to have a phase difference detection function, and realize a wide dynamic range while reading noise It is possible to prevent the influence of the image quality and to improve the image quality.

Second Embodiment
FIGS. 18A to 18D are diagrams showing an example of a layout diagram and a potential diagram of a pixel cell array according to a third embodiment of the present invention.
FIG. 18A shows a layout diagram.
FIG. 18B shows the FD reset state in which the gate 2122 and the output gate 213 of the charge transfer path gate unit 2120 are in a non-conductive state, and the gate 2123 and the reset gate (RG) 222 are controlled in a conductive state.
FIG. 18C shows an FD reset state in which the gate 2122 of the charge transfer path gate unit 2120, the output gate 213, and the reset gate (RG) 222 are controlled to be nonconductive and the gate 2123 is controlled to be conductive.
FIG. 18D shows a reading state in which the gates 2122 and 2123 and the reset gate (RG) 222 of the charge transfer path gate unit 2120 are controlled to be nonconductive and the output gate 213 is controlled to be conductive.

  FIG. 19 is a plan view showing a partial configuration example of a solid-state imaging device according to a third embodiment of the present invention.

The difference between a solid-state imaging device 100E according to the third embodiment and the solid-state imaging device 100 according to the first embodiment described above is as follows.
In the solid-state imaging device 100E of the third embodiment, in the first substrate 110E, the conversion output unit 220E is disposed for each of one or a plurality of pixel cells PXLC. In the example of FIG. 18, the conversion output unit 220E is disposed for every three pixel cells PXLC.
The output of each conversion output unit 220E is connected to the peripheral circuit unit 300 including the ADC and the like on the second substrate 120E side through the connection unit 230E.

According to the third embodiment, the same effects as those of the first embodiment described above can be obtained, and of course, the charge-to-voltage converter is provided in the pixel cell, and the second substrate 120E is stacked. From the provision of signal storage and readout units. Low noise readout and massively parallel readout are possible, ultrafast readout, and parasitic sensitivity during global shutter operation can be reduced.
As a result, it is possible to optimize the exposure time in an arbitrary area in the pixel array, and to enable wide dynamic range imaging.
In addition, it becomes possible to control the accumulation period for each pixel, and for example, can have a white balance function.

Fourth Embodiment
FIG. 20 is a simplified cross-sectional view for describing a configuration example of a solid-state imaging device according to a fourth embodiment of the present invention.

The difference between the solid-state imaging device 100F according to the fourth embodiment and the solid-state imaging device 100 according to the first embodiment described above is as follows.
The solid-state imaging device 100F of the fourth embodiment is configured as a front side illumination type, not a back side illumination type.

In the fourth embodiment, the light shielding portion 2150F is formed of a first embedded light shielding portion 2151F and a second embedded light shielding portion 2152F outside the substrate on the first substrate surface 1101 side of the first substrate 110F. It is formed to extend outside the substrate on the side of the first substrate surface 1101 of the substrate 110.
Also, instead of the p + layer 2116, an n--layer 2117 is formed.

  According to the fourth embodiment, substantially the same effect as that of the first embodiment described above can be obtained.

  The solid-state imaging devices 100 and 100A to 100F described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, portable terminals, surveillance cameras, and medical endoscope cameras.

Fifth Embodiment
FIG. 21 is a view showing an example of the configuration of an electronic apparatus equipped with a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 21, the electronic device 400 includes the CCD / CMOS stacked solid-state imaging device 410 according to the present invention to which the solid-state imaging devices 100 and 100A to 100F according to the present embodiment are applicable.
Further, the electronic device 400 has an optical system (lens or the like) 420 for guiding incident light to the pixel region of the CCD / CMOS stacked solid-state imaging device 410 (forming an object image).
The electronic device 400 has a signal processing circuit (PRC) 430 that processes an output signal of the CCD / CMOS stacked solid-state imaging device 410.

The signal processing circuit 430 performs predetermined signal processing on the output signal of the CCD / CMOS stacked solid-state imaging device 410.
The image signal processed by the signal processing circuit 430 can be displayed as a moving image on a monitor including a liquid crystal display or the like, or can be output to a printer, or can be recorded directly on a recording medium such as a memory card. Is possible.

As described above, by mounting the solid-state imaging devices 100 and 100A to 100F described above as the CCD / CMOS stacked solid-state imaging device 410, it is possible to provide a high-performance, small-sized, low-cost camera system. .
And, electronic equipment such as surveillance cameras, medical endoscope cameras, etc. used for applications where restrictions on the mounting size, number of connectable cables, cable length, installation height etc. are required for camera installation requirements Can be realized.

  100, 100A to 100F: solid-state imaging device, 110, 110A to 110F: first substrate, 120, 120A to 120F: second substrate, 140: through via (TSV), 200 · · Image pickup device unit, 210 · · · photosensitive unit (imaging unit), 211 · · · pixel unit, 212-1 to 212-4 · charge transfer unit (vertical transfer unit, VCCD), 213 to 213 -4-Output end part, PXLC-Pixel cell, 220, 220-1 to 220-4-Conversion output unit, 230--Relay unit, 231, 231-1 to 231-4- · · · Connection portion, 240 ... source follower circuit, 241 ... amplification portion, 242 ... current source portion, TI 240 ... input end, TO 240 ... output end, 2110 ... photodiode, 2120 ... Charge transfer path gate 2130: separation layer, 2140: charge transfer gate portion, 2150: light shielding portion, 2160: color filter portion, 2170: microlens, 2180: horizontal overflow drain portion, 310. ADC 320 digital memory 330 amplifier (amplifier) 340 sample and hold circuit 400 electronic device 410 CCD / CMOS stacked solid-state imaging device 420 Optical system 430 Signal processing circuit (PRC).

Claims (17)

A photosensitive unit including a plurality of photoelectric conversion units arranged in a matrix and a plurality of charge transfer path units transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows;
The photosensitive unit is
A pixel cell formed on a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side and separated by a separation layer,
The pixel cell is
The photoelectric conversion unit including a first conductive type semiconductor layer formed to be embedded in the substrate and having a photoelectric conversion function of received light and a charge storage function;
A second conductive separation layer formed on the side of the first conductive semiconductor layer of the photoelectric conversion unit;
A charge transfer gate portion formed on the second substrate surface side of the second conductivity type separation layer and capable of transferring the signal charge stored in the photoelectric conversion portion;
A charge transfer path gate portion which is formed on the second substrate surface side of the second conductivity type separation layer and can transfer signal charges transferred by the charge transfer gate portion in the row direction or the column direction;
A light shielding portion formed in at least the second conductive separation layer to block light from entering at least an element region of the charge transfer path gate portion. The light shielding portion is
A first buried light shielding portion embedded in a depth direction in the second conductivity type separation layer within an element region width in which the charge transfer gate portion is formed;
The second buried type light shielding portion embedded in the depth direction is included in the second conductive type separation layer on the adjacent pixel cell side outside the element region width in which the charge transfer path gate portion is formed. The solid-state imaging device according to 1. The light shielding portion is
At least the first embedded light shielding portion and the second embedded light shielding portion outside the substrate on the first substrate surface side of the substrate, the element region in which the charge transfer path gate portion is formed The solid-state imaging device according to claim 2, further comprising a third light shielding portion formed to face the two-conductivity type separation layer. The light shielding portion is
The first embedded light shielding portion and the second embedded light shielding portion are formed to extend outside the substrate on the first substrate surface side of the substrate outside the substrate on the first substrate surface side of the substrate. The solid-state imaging device according to claim 2. At least one of the pixel cells is
A lateral overflow drain portion formed on the second substrate surface side of the second conductivity type separation layer and discharging a signal charge overflowed from the photoelectric conversion portion;
The light shielding portion is
5. The device according to claim 1, wherein the second conductive separation layer in the element region width in which the horizontal overflow drain portion is formed includes a fourth embedded light shielding portion embedded in the depth direction. Solid-state imaging device. The first pixel cell and the second pixel cell in adjacent columns or rows across one of the charge transfer paths,
The first pixel cell and the second pixel cell are
Adjacent to one another across the one second conductive separation layer forming the one charge transfer path,
The first pixel cell is
The first photoelectric conversion unit has a first sensitivity, and the first charge transfer gate unit and the first charge transfer path gate unit are the second one of the first photoelectric conversion unit and the second photoelectric conversion unit. Formed on the second substrate surface side of the conductive separation layer,
The second pixel cell is
The second photoelectric conversion unit has a second sensitivity different from the first sensitivity, and the second charge transfer gate unit and the second charge transfer path gate unit are the second photoelectric conversion unit. The solid-state imaging device according to any one of claims 1 to 5, wherein the solid-state imaging device is formed on the second substrate surface side of the one second conductive separation layer. The light shielding portion is
In the second conductivity type separation layer in the element region width in which the first charge transfer gate portion and the second charge transfer gate portion are respectively formed, two fifth buryings embedded in the depth direction A light shield,
Sixth buried light shielding embedded in a depth direction in the second conductivity type separation layer between element regions in which the first charge transfer path gate portion and the second charge transfer path gate portion are respectively formed The solid-state imaging device according to claim 6. The light shielding portion is
At least the first embedded light shielding portion and the second embedded light shielding portion outside the substrate on the first substrate surface side of the substrate, the element region in which the charge transfer path gate portion is formed The solid-state imaging device according to claim 7, further comprising a third light shielding portion formed to face the two conductivity type separation layer. The solid-state imaging device according to any one of claims 1 to 8, further comprising: a conversion output unit that converts the signal charge transferred to the charge transfer unit into an electric signal and outputs the electric signal. The solid-state imaging device according to claim 9, wherein the conversion output unit is disposed in accordance with the number of columns or rows. The solid-state imaging device according to claim 9, wherein the conversion output unit is disposed for each of one or a plurality of pixel cells. A peripheral circuit unit that performs predetermined processing on the electrical signal by the conversion output unit;
A relay unit relaying transfer of the electric signal to the peripheral circuit unit by the conversion output unit;
A first substrate on which the photosensitive unit and the conversion output unit are formed;
And a second substrate on which the peripheral circuit portion is formed,
At least the first substrate and the second substrate are stacked,
The relay unit is
Electrically connecting the conversion output portion formed on the first substrate and the peripheral circuit portion formed on the second substrate by a connection portion through the substrate outside the photosensitive region of the photosensitive portion The solid-state imaging device according to claim 10. A peripheral circuit unit that performs predetermined processing on the electrical signal by the conversion output unit;
A relay unit relaying transfer of the electric signal to the peripheral circuit unit by the conversion output unit;
A first substrate on which the photosensitive unit and the conversion output unit are formed;
And a second substrate on which the peripheral circuit portion is formed,
At least the first substrate and the second substrate are stacked,
The relay unit is
The solid according to claim 11, wherein the conversion output portion formed on the first substrate and the peripheral circuit portion formed on the second substrate are electrically connected by a connection portion passing through the substrate. Imaging device. The relay unit is
The solid-state imaging device according to claim 12, wherein a source follower unit that amplifies an electric signal by the conversion output unit is formed on at least one of the first substrate and the second substrate. The source follower unit
The amplifier unit includes an amplifier unit and a current source unit connected in series, the amplifier unit is formed on the first substrate, the current source unit is formed on the second substrate, and is connected to the current source unit. Outputting the signal amplified from the output end side of the amplification unit to the peripheral circuit unit;
The relay unit is
The conversion output unit formed on the first substrate is connected to the input end of the amplification unit of the source follower unit, and the output end of the amplification unit and a current source unit formed on the second substrate are The solid-state imaging device according to claim 14, which is connected via the connection unit. Forming a photosensitive unit including a plurality of photoelectric conversion units arranged in a matrix and a plurality of charge transfer path units for transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows;
In the process of forming the photosensitive portion,
Forming a pixel cell separated by a separation layer on a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side,
In the process of forming the pixel cell,
Forming a first conductivity type semiconductor layer so as to be embedded in the substrate, and forming the photoelectric conversion portion having a photoelectric conversion function of received light and a charge storage function;
Forming a second conductive separation layer on the side of the first conductive semiconductor layer of the photoelectric conversion unit;
Forming a charge transfer gate portion capable of transferring the signal charge stored in the photoelectric conversion portion on the second substrate surface side of the second conductivity type separation layer;
Forming a charge transfer path gate portion capable of transferring the signal charge transferred by the charge transfer gate portion in the row direction or the column direction on the second substrate surface side of the second conductivity type separation layer;
Forming at least the second conductive separation layer with a light shielding portion for blocking incidence of light to at least an element region of the charge transfer path gate portion. A solid-state imaging device,
And an optical system for forming an image on a photosensitive portion of the solid-state imaging device,
The solid-state imaging device is
The photosensitive unit includes a plurality of photoelectric conversion units arranged in a matrix and a plurality of charge transfer path units for transferring signal charges of the plurality of photoelectric conversion units in units of columns or rows,
The photosensitive unit is
A pixel cell formed on a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side and separated by a separation layer,
The pixel cell is
The photoelectric conversion unit including a first conductive type semiconductor layer formed to be embedded in the substrate and having a photoelectric conversion function of received light and a charge storage function;
A second conductive separation layer formed on the side of the first conductive semiconductor layer of the photoelectric conversion unit;
A charge transfer gate portion formed on the second substrate surface side of the second conductivity type separation layer and capable of transferring the signal charge stored in the photoelectric conversion portion;
A charge transfer path gate portion which is formed on the second substrate surface side of the second conductivity type separation layer and can transfer signal charges transferred by the charge transfer gate portion in the row direction or the column direction;
An electronic apparatus, comprising: a light shielding portion formed in at least the second conductive separation layer and blocking at least light from entering the device region of the charge transfer path gate portion.

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