KR20130133824A - Cmos image sensor pixel and controlling timing sequence thereof - Google Patents

Abstract

The present invention is a type of CMOS image sensor pixel and its control timing sequence, in which four pixels of a CMOS image sensor pixel array are arranged in a 2x2 pixel array to form a group of pixel units, of which the first column and the second are Two pixels in a column each share a selection transistor, a source follower transistor, a reset transistor and an active region in the column, and the first and second columns are arranged in a back-to-back manner; Multiple groups of pixel units are arranged in a two-dimensional pixel array in the vertical and horizontal directions. In the pixel array, the pixels in the same row realize the interconnection of the device through the second layer metal connection line, and the pixels in the uniform column realize the interconnection of the device through the first layer metal connection line; The first layer metal connection line is a signal output line, a column controller timing sequence control line and a power supply control line, and the second layer metal connection line is a low decoder timing sequence output control line. Since the structure of the present invention can improve the light utilization efficiency of the pixel sensor having a small area and improve the sensitivity, it is possible to effectively improve the image quality of the pixel image sensor having a small area.

Description

CMOS image sensor pixel and its control timing sequence {CMOS IMAGE SENSOR PIXEL AND CONTROLLING TIMING SEQUENCE THEREOF}

This application is filed with the Chinese Patent Office on April 15, 2011, and has the application number 201110095448.2, and claims the priority of the Chinese patent application entitled "CMOS Image Sensor Pixel and Its Control Timing Sequence". The entire contents are incorporated in this application by reference.

The present invention relates to a type of CMOS image sensor, and more particularly to a type of CMOS image sensor pixel and its control timing sequence.

Image sensors are now widely used in digital cameras, mobile phones, medical devices, vehicles and other applications. In particular, the rapid development of CMOS (complementary metal oxide semiconductor) image sensors has driven the need for high resolution image sensors with low power and small size.

Since the arrangement method of the CMOS image sensor pixel structure in the prior art depends on the structural characteristics of the pixel itself, taking 4T2S as an example, the array generally has a first layer metal, a second layer metal, and a third layer metal serving as device connection lines. Multiple rows of first-layer metal or second-layer metal connections are required between pixels in adjacent rows, and multiple columns of second-layer metal or first-layer metal connections are required between pixels in adjacent columns. .

The prior art includes at least the following disadvantages:

The small sized pixel sensor has a small photosensitive area and low sensitivity, so that information transmission is not clear enough in dark light. In particular, when the first layer metal, the second layer metal, and the third layer metal are used as the device connection lines, the height of the medium on the surface of the photodiode Si (sphere) is relatively high, which affects the incident of light to the photodiode. Multiple metal connections between pixels in adjacent rows and adjacent columns lower the aperture ratio of the metal window and block some light rays from entering the photodiode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS image sensor pixel having a relatively large metal window aperture ratio and high sensitivity, and a control timing sequence thereof.

The object of the present invention is realized through the following technical solutions:

The CMOS image sensor pixel of the present invention includes a photodiode, a charge transfer transistor, a select transistor, a source follower transistor, a reset transistor, and an active region.

Specifically, four pixels are arranged in a 2 × 2 pixel array to form a group of pixel units, in which two pixels in the first and second columns are selected transistors, source follower transistors, reset transistors, and the like. The active area is shared, and the first and second columns are arranged in a back-to-back manner.

A plurality of groups of pixel units are arranged in a two-dimensional pixel array in the vertical and horizontal directions, and the pixels in the same row realize the interconnection of the device through the second layer metal connecting line, and the pixels in the uniform column are connected through the first layer metal connecting line. Realize the interconnection of devices.

Device arrangement method of two pixels in the first column

The selection transistor SX1 and the source follower transistor SF1 are positioned on the photodiode PD11 of the pixel 11, and the reset transistor RX1 is disposed on the photodiode PD11 and the pixel 21 of the pixel 11. Located between the photodiode PD21.

Device arrangement method of two pixels in the second column

The selection transistor SX2 and the source follower transistor SF2 are positioned under the photodiode PD22 of the pixel 22, and the reset transistor RX2 is formed of the photodiode PD12 and the pixel 22 of the pixel 12. Located between the photodiode PD22.

In the device arrangement scheme of the two pixels in the first column, the selection transistor SX1 is positioned on the left side of the source follower transistor SF1.

In the device arrangement scheme of the two pixels in the second column, the selection transistor SX2 is positioned to the right of the source follower transistor SF2.

In the device arrangement scheme of the two pixels in the first column, the active region FD1 is disposed between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21 on the right side of the reset transistor RX2. Located.

In the device arrangement scheme of the two pixels in the second column, the active region FD2 is disposed between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22 on the left side of the reset transistor RX2. Located.

In the device arrangement method of two pixels in the first column, the active region FD1 and the source follower transistor SF1 grid electrode are connected by a first layer metal connection line.

In the arrangement method of the two pixels in the second column, the active region FD2 and the source follower transistor SF2 grid electrode are connected by a first layer metal connection line.

The CMOS image sensor pixel may include a pixel array composed of a plurality of groups of the pixel units.

In the control timing sequence of the CMOS image sensor pixel of the present invention, the control timing sequence includes a CMOS image sensor pixel array row decoder timing sequence and a column controller timing sequence.

The first layer metal connection line is a signal output line, a column controller timing sequence control line, and a power supply control line.

The second layer metal connection line is a row decoder timing sequence output control line.

As can be seen from the above description, the CMOS image sensor pixel of the present invention adopts the structure of 4T2S (four transistors and two pixels share a selection transistor, a source follower transistor, and a reset transistor). Four pixels are arranged in a 2 × 2 pixel array to form a group, of which two pixels in the first and second columns each share a selection transistor, a source follower transistor, and a reset transistor in the column, The first and second columns are arranged in a back-to-back manner.

The CMOS image sensor pixel array of the present invention uses only the first layer metal and the second layer metal as interconnects of the device, and does not use the third layer metal as the device interconnects, thereby lowering the height of the medium of the photoelectric diode Si (silicon) surface. More light can be incident on the photodiode. The CMOS image sensor pixel structure of the present invention and the arrangement of each transistor can be realized by arranging only two second layer metal connection lines between pixels of adjacent rows and only one layer metal connection lines between pixels of adjacent columns. . Such a metal lead structure can effectively improve the metal window opening ratio.

In addition, based on the pixel structure of the present invention, two control timing sequences, that is, a CMOS image sensor pixel array row decoder timing sequence and a column controller timing sequence, may be used.

Since the CMOS image sensor pixel structure of the present invention can improve the light utilization efficiency of a small area pixel sensor to improve sensitivity, the image quality of the small area pixel image sensor can be effectively improved.

1 is an explanatory diagram of a 4T2S back-to-back structure composed of four pixels among specific embodiments of a CMOS image sensor pixel provided by the present invention.
FIG. 2 is a circuit explanatory diagram of a 4T2S back-to-back structure composed of four pixels among specific embodiments of a CMOS image sensor pixel provided by the present invention.
FIG. 3 is an explanatory diagram of a 6 × 4 pixel array of specific embodiments of a CMOS image sensor pixel provided by the present invention. FIG.
FIG. 4 is an explanatory diagram of a 6x4 pixel array circuit of specific embodiments of a CMOS image sensor pixel provided by the present invention. FIG.
5 is an explanatory diagram of a pixel array to which a row decoder and a column controller are added, according to a specific embodiment of a CMOS image sensor pixel provided by the present invention.
FIG. 6 is an explanatory diagram of a row decoder timing sequence and a column controller timing sequence of a pixel array among specific embodiments of a CMOS image sensor pixel provided by the present disclosure.

A preferred specific embodiment of the CMOS image sensor pixel and its control timing sequence of the present invention is a photoelectric diode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, an active region, as shown in Figs. And a first layer metal lead and a second layer metal lead. The pixels 11 and 21 located in the pixel array column 1 share the active region FD1 with the selection transistor SX1, the source follower transistor SF1, and the reset transistor RX1, and the pixels 12 and 22 located in the pixel array column 2 are selected. The active region FD2 is shared with the transistor SX2, the source follower transistor SF2, and the reset transistor RX2. Among them, the selection transistor SX1 and the source follower transistor SF1 are positioned above the photodiode diode PD11 of the pixel 11, and the reset transistor RX1 is positioned between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21. The selection transistor SX2 and the source follower transistor SF2 are located under the photodiode diode PD22 of the pixel 22, the reset transistor RX2 is located between the photodiode diode PD11 of the pixel 12 and the photodiode diode PD11 of the pixel 22, the pixel 11 and the pixel 21 and the pixel 12 and The pixel 22 forms a back-to-back structure in the horizontal direction.

The selection transistor SX1 is located on the left side of the source follower transistor SF1, and the selection transistor SX2 is located on the right side of the source follower transistor SF2.

The active region FD1 is positioned between the photodiode diode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21, to the right of the reset transistor RX1, and the active region FD2 is between the photodiode diode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22, the reset transistor. It is located on the left side of RX2.

The grid electrode of the active region FD1 and the source follower transistor SF1 is connected by a first layer metal line, and the grid electrode of the active region FD2 and the source follower transistor SF2 is connected by a first layer metal line.

The power source first layer metal connection line Vdd connects the drain electrodes of SF1 and SF2.

The first layer metal connection line SC1 connects the source electrode of the selection transistor SX1, the grid electrode of the reset transistor RX1 and the source electrode, and the first layer metal connection line SC2 is the source electrode of the selection transistor SX2, the grid electrode of the reset transistor RX2, and A source electrode is connected, and the first layer metal connection line SC1 and the first layer metal connection line SC2 are a source output line and a column controller timing sequence control line.

The second layer metal connection line SX connects the grid electrode of the selection transistor SX1 and the selection transistor SX2.

The second layer metal connection line TX1 connects the grid electrode of the charge transfer transistor TX11 and the charge transfer transistor TX12, and the second layer metal connection line TX2 connects the charge electrode of the transfer transistor TX21 and the grid electrode of the charge transfer transistor TX22.

The second layer metal connection line SX, the second layer metal connection line TX1 and the second layer metal connection line TX2 are row decoder timing sequence output control lines.

The present invention solves the problem of low sensitivity of a pixel having a small area of a conventional image sensor.

Specific Example 1

As shown in FIG. 1, the CMOS image sensor pixel adopts a 4T2S structure, and includes four pixels, and the photodiodes of pixels 11, 12, 21 and 22 are PD11, PD12, PD21, and PD22, respectively. . TX1 and TX2 are charge transfer transistors of pixels 11 and 12, respectively, TX21 and TX22 are charge transfer transistors of pixels 21 and 22, respectively, and SX1, SF1 and RX1 are select transistors and source polos of pixels 11 and 21, respectively. AX transistors and reset transistors, and SX2, SF2, and RX2 are select transistors, source follower transistors, and reset transistors of pixels 12 and 22, respectively. The pixels 11 and 21 share the active region FD1 (Floating Diffusion) with the transistors SX1, SF1, and RX1, and the pixels 12 and 22 share the active region FD2 with the transistors SX2, SF2, RX2. The shared pixels 11 and 21 and the shared pixels 12 and 22 form a back-to-back structure in the horizontal direction.

The metal interconnects used for CMOS image sensor pixels are described below. The grid poles of the active regions FD1 and SF1 are connected by a first layer metal line, and the grid poles of the active regions FD2 and SF2 are connected by a first layer metal line. The first layer metal connecting line Vdd of the power source connects the drain electrodes of SF1 and SF2. The SC1 line is the first layer metal connection line, which connects the source electrode of SX1, the grid electrode of RX1 and the source electrode, and the first layer metal connection line of SC1 is a signal output line and a column controller timing sequence control line. . The SC2 line is the first layer metal connection line, which connects the source electrode of SX2, the grid electrode of RX2 and the source electrode, and the SC2 first layer metal connection line is a signal output line and a column controller timing sequence control line. SX line is a 2nd layer metal connection line, and connects the grid electrode of SX1 and SX2. The TX1 line connects the grid poles of TX11 and TX12 as the second layer metal connection line, and the TX2 line connects the grid poles of TX21 and TX22 as the second layer metal connection line. The SX second layer metal lead, the TX1 second layer metal lead and the TX2 second layer metal lead are all low decoder timing sequence output control lines.

As illustrated in FIG. 2, the above description is a diagram illustrating a structure of a structure in which four groups of pixels form a back-to-back format, wherein the four pixels are recorded as one group, and the plurality of groups of back-to-back type pixels are vertical and horizontal. To form a two-dimensional pixel array.

Specific Example 2

3 is an explanatory diagram of a 6 × 4 pixel array diagram, and a circuit diagram corresponding to the explanatory diagram of the pixel array diagram illustrated in FIG. 3 is as illustrated in FIG. 4.

Among the pixel arrays shown in FIGS. 3 and 4, the grid poles of the respective pixel FD regions and the corresponding source follower transistors are connected by a first layer metal connection line, and the power supply Vdd line uses a first layer metal connection line. Lines SC1 to SC6 are first-layer metal connection lines, and serve as signal output lines and column controller timing sequence control lines. The second layer metal connecting line SX1 connects the grid poles of SX11 to SX16, the second layer metal connecting line TX1 connects the grid poles of TX11 to TX16, and the second layer metal connecting line TX2 connects the grid poles of TX21 to TX26. The second layer metal connecting line TX3 connects the grid poles of TX31 to TX36, and the second layer metal connecting line TX4 connects the grid poles of TX41 to TX46. This two-dimensional pixel array uses only two layers of metal interconnects, only two rows of second-layer metal interconnects between pixels in adjacent rows, and only two columns of first-layer metal interconnects between pixels in adjacent columns. . The present invention effectively improves the sensitivity of a small-sized pixel sensor by increasing the metal window aperture ratio using only two layers of metal.

Specific Example 3

Details of CMOS image sensor pixel array signal acquisition are as follows:

5 is an explanatory diagram of a pixel array to which a row decoder and a column controller are added. The row decoder is provided on the left side of the pixel array (may be installed on the right side of the array). The column controller is disposed above the pixel array, and the signal reading device is disposed at the bottom of the pixel array. The position of the decoder, controller and signal reading device is by no means unique in the present invention and can be adjusted according to the specific design arrangement of the chip. 5 illustrates the specific positions of the array pixels in detail, and specific numbers of the decoder timing sequence output control line and the column controller timing sequence control line are indicated. m and n are non-negative integers representing the positions of the pixel rows and columns of the pixel array, respectively. For example, the pixels 2m + 1 and 2n + 1 indicate that the position of this pixel is located in the 2m + 1th row and the 2n + 1th column. The metal connection line Vdd is a power supply line. When the sensor is operating normally, Vdd is a power supply voltage. The metal leads SC are both signal output leads and column controller timing sequence control lines, while the metal leads SX and TX are low decoder timing sequence output control lines.

6 is an explanatory diagram of a row decoder output timing sequence and a column controller timing sequence adopted by a CMOS image sensor pixel array, in which all pixel arrays of the present invention use N-type transistors. When the N-type transistor grid pole is set to a high level, that is, when the signal controlling the transistor grid pole is set to a high level, it indicates that the transistor is turned on, and when the N-type transistor grid pole is set to a low level, that is, the grid of this transistor When the signal controlling the pole is set at the low level, it indicates turning off the transistor. The length of the N-type transistor operating time, that is, the length of time that the signal controlling the grid pole of the transistor is set to a high level is determined by the specific situation in which the sensor is operated, and when the signal reading device at the bottom of the pixel array reads the signal, The SC line is converted from the column controller timing sequence control line to the signal output line so that the signal reading device reads out the signal through the signal output line. In FIG. 6, a signal reading device reads a pixel signal in a diagonal rectangle. When the pixel signal is read by the signal reading device, the signal output line is converted into a column controller timing sequence control line.

When the CMOS image sensor pixel array of the present invention operates normally, it adopts a low scrolling exposure method, and the pixels in the 2m + 1st row start exposure first, then the pixels in the 2m_2th row start exposure, and then 2m_3 Second row, followed by 2m + 4th row. The order in which the exposure ends is the same as the order in which the exposure starts, and the order of reading the pixel signals in each row is also the same as the order in which the pixel exposure starts in each row. When the sensor collects the same frame pixel array signal, the exposure time of the pixels in each row is the same.

Hereinafter, timing sequence control of one row of pixels will be described in detail. The exposure time of the low pixel begins with the first high level falling edge of the TX signal and ends with the next high level falling edge of the TX signal. Prior to the start of the exposure time, the charge stored in the potential well of the pixel photodiode must be removed, i.e. the SX signal is at low level and the TX and SC signals are set from low level to high level to turn on the charge transfer transistor and the reset transistor. After the charge stored in the pixel photodiode potential well is removed, first turn off the charge transfer transistor, then turn off the reset transistor, i.e., the SX signal is at low level, and the TX and SC signals are from low level to low level. If set to, then the pixel photodiode starts exposure. Before the exposure time expires, a reset signal of the pixel must be collected. First, when the SX signal and the TX signal are placed at the low level, and the SC signal is set from the low level to the high level, the corresponding FD region of the pixel is reset to the high level, After the FD region is reset to high level, the SC signal is set from high level to low level and the reset transistor is turned off. Then, the SC line is converted from the column controller control line to the signal output line, the TX signal is kept at low level, the SX signal is set from low level to high level to turn on the selection transistor, and the signal output line is passed to the signal reading device. The signal of each pixel of the corresponding entire row is read, stored and recorded as signal 1. After the signal 1 is read, the SX signal is held at a high level, and when the signal reading device stops reading the pixel signal, the SC line is converted from the output line to the column controller control line, and the SC signal is set to the low level. When the SC signal is at low level, the SX signal is at high level, and the TX signal is set from low level to high level, it turns on the charge transfer transistor and transfers the photoelectric charge in the photodiode potential well to the corresponding FD region of the pixel.

After the photoelectric charge in the pixel photodiode potential well is transferred to the corresponding FD region of the pixel, turning off the charge transfer transistor, i.e., the SC timing sequence is at a low level, the SX timing sequence is at a high level, and the TX timing sequence is Is set from the high level to the low level, the exposure time ends. Then, the SC line is converted from the column controller control line to the signal output line, and the signal of each pixel of the corresponding entire row is read by the signal reading device through the signal output line and recorded as signal 2. After reading signal 2, when the signal reading device stops reading the pixel signal, the SX timing sequence is set from high level to low level, and the SC line is converted from the signal output line to the column controller control line.

The timing sequence control scheme adopted by the CMOS image sensor pixel array of the present invention is by no means unique, for example, in a process in which a signal reading device reads the same pixel signals 1 and 2 of the same frame after the signal output line. After reading signal 1, first turn the select transistor off by setting the SX timing sequence from high level to low level, then turn on the select transistor by setting the SX timing sequence again from low level to high level before reading signal 2, The reading device can read signal 2. The photoelectric signal collected by the sensor pixel is read and written by the signal reading device, and the true photoelectric signal is the difference value signal between the signal 1 and the signal 2.

The foregoing descriptions are merely specific exemplary embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art may change within the technical scope disclosed by the present invention. Alternatively, replacement can be easily conceived, which all should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims (10)

In a CMOS image sensor pixel comprising a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, and an active region,
Four pixels are arranged in a 2 × 2 pixel array to form a group of pixel units, of which two pixels in the first and second columns are selected transistors, source follower transistors, reset transistors, and active regions in the columns, respectively. The first column and the second column are arranged in a back-to-back manner;
A plurality of groups of pixel units are arranged in a two-dimensional pixel array in the vertical and horizontal directions, and the pixels in the same row realize the interconnection of the device through the second layer metal connecting line, and the pixels in the uniform column are connected through the first layer metal connecting line. CMOS image sensor pixels, which realize device interconnection.
The method of claim 1,
A device arrangement method of two pixels in the first column is
The selection transistor SX1 and the source follower transistor SF1 are positioned on the photodiode PD11 of the pixel 11, and the reset transistor RX1 is disposed on the photodiode PD11 and the pixel 21 of the pixel 11. Located between photoelectric diode PD21;
The device arrangement method of two pixels in the second column is
The selection transistor SX2 and the source follower transistor SF2 are positioned under the photodiode PD22 of the pixel 22, and the reset transistor RX2 is formed of the photodiode PD12 and the pixel 22 of the pixel 12. CMOS image sensor pixels, which are located between the photodiode diodes PD22.
3. The method of claim 2,
In the device arrangement scheme of the two pixels in the first column, the selection transistor SX1 is located to the left of the source follower transistor SF1;
The CMOS image sensor pixel of claim 2, wherein the selection transistor SX2 is positioned to the right of the source follower transistor SF2.
The method of claim 3, wherein
In the device arrangement scheme of the two pixels in the first column, the active region FD1 is disposed between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21 on the right side of the reset transistor RX2. Located;
In the device arrangement scheme of the two pixels in the second column, the active region FD2 is disposed between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22 on the left side of the reset transistor RX2. CMOS image sensor pixel, characterized in that located.
5. The method of claim 4,
In the device arrangement scheme of the two pixels in the first column, the active region FD1 and the source follower transistor SF1 grid electrode are connected by a first layer metal connection line;
2. The CMOS image sensor pixel of claim 2, wherein an active region (FD2) and a source follower transistor (SF2) grid electrode are connected by a first metal connection line.
The method according to any one of claims 1 to 5,
And said CMOS image sensor pixel comprises a pixel array comprised of a plurality of said pixel units.
A control timing sequence of a CMOS image sensor pixel according to any one of claims 1 to 5,
The control timing sequence includes a CMOS image sensor pixel array row decoder timing sequence and a column controller timing sequence.
8. The method of claim 7,
The first layer metal connection line is a signal output line, a column controller timing sequence control line, and a power supply control line;
And the second layer metal connection line is a row decoder timing sequence output control line.
The method according to claim 6,
The control timing sequence includes a CMOS image sensor pixel array row decoder timing sequence and a column controller timing sequence.
The method of claim 9,
The first layer metal connection line is a signal output line, a column controller timing sequence control line, and a power supply control line;
And the second layer metal connection line is a row decoder timing sequence output control line.

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