JP5735169B2 - CMOS image sensor pixel and control sequence thereof - Google Patents

Description

  This application is filed with the Chinese Patent Office on February 27, 2012. The priority of the Chinese patent application is “CMOS image sensor pixel readout circuit structure and its control sequence”. The entire content of which is claimed and incorporated herein by reference.

TECHNICAL FIELD The present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor pixel and its control sequence.

  Currently, image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications. In particular, due to the rapid development of CMOS (complementary metal oxide semiconductor) image sensors, there is an increasing demand for low output, small size, high resolution image sensors.

  The arrangement of the CMOS image sensor pixel structure in the prior art depends on the structural characteristics of the pixel itself, taking 4T2S as an example, and the array generally includes a first layer metal, a second layer metal and a third layer metal. The metal of the first layer needs to be interconnected as an element, and the pixels of the first layer of the plurality of rows or the metal of the second layer need to be connected between the pixels of the adjacent rows. It is necessary to connect the metal of the first layer, the metal of the second layer, or the metal of the third layer in a plurality of rows or a plurality of columns, respectively, between the pixels in or between adjacent columns.

  The prior art described above includes at least the following drawbacks.

  Since the photosensitive area of the small pixel sensor is small and the sensitivity is low, information transfer under dark light is not clear enough. In particular, when the first layer metal, the second layer metal, and the third layer metal are interconnected as an element, the height of the medium on the surface of the photodiode Si (silicon) is relatively high and adjacent to each other. Multiple metal lines between the pixels in the rows and adjacent columns lower the metal window aperture ratio and hinder the entrance of some light rays into the photodiode.

  An object of the present invention is to provide a small CMOS image sensor pixel having a relatively large metal window aperture ratio and high sensitivity, and a control sequence thereof.

  The object of the present invention is realized by the following technical technique.

  The CMOS image sensor pixel of the present invention includes a pixel array including a plurality of sets of pixel cells, and each set of pixel cells includes a 2 × 2 pixel array structure in which four pixels are arranged, and includes a first column and a first column. Two pixels of the two columns each share a selection transistor, a source follower transistor, a reset transistor and a floating active region in the column, and the first column 4 and the second column form a staggered arrangement structure. To do.

  The plurality of sets of pixel cells are arranged so as to form a two-dimensional pixel array in a vertical and horizontal direction, and pixels in the same row in the two-dimensional pixel array realize element connection by a metal wire of a second layer, In the pixels in the same column, the elements are connected by the metal wire of the first layer.

  The arrangement method of the elements of the two pixels in the first column is as follows.

  The selection transistor SX1, the source follower transistor SF1, and the reset transistor RX1 are located between the photodiode PD01 of the pixel 01 and the photodiode PD11 of the pixel 11.

  The arrangement method of the elements of the two pixels in the second column is as follows.

  The selection transistor SX2, the source follower transistor SF2, and the reset transistor RX2 are located between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22.

  In the arrangement method of the elements of the two pixels in the first column, the selection transistor SX1 is located on the upper left side of the photodiode PD01 and the lower left side of the photodiode PD11, and is located on the left side of the source follower transistor SF1.

  In the arrangement method of the elements of the two pixels in the second column, the selection transistor SX2 is located on the upper right side of the photodiode PD12 and the lower right side of the photodiode PD22, and is located on the right side of the source follower transistor SF2.

  In the arrangement method of the elements of the two pixels in the first column, the source follower transistor SF1 is located immediately above the photodiode PD01 and immediately below the photodiode PD11.

  In the arrangement method of the elements of the two pixels in the second column, the source follower transistor SF2 is located immediately above the photodiode PD11 and directly below the photodiode PD22.

  In the arrangement method of the elements of the two pixels in the first column, the floating active region FD1 is located between the photodiode PD01 of the pixel 01 and the photodiode PD11 of the pixel 11, and is located on the left side of the reset transistor RX1. .

  In the arrangement method of the elements of the two pixels in the second column, the floating active region FD2 is located between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22, and is located on the right side of the reset transistor RX2. .

  In the arrangement method of the elements of the two pixels in the first column, the floating active region FD1 is connected to the gate of the source follower transistor SF1 by the metal line of the first layer.

  In the arrangement method of the elements of the two pixels in the second column, the floating active region FD2 is connected to the gate of the source follower transistor SF2 by the metal line of the first layer.

  The above described CMOS image sensor pixel control sequence of the present invention includes a CMOS image sensor pixel array row decoder sequence and a column controller sequence.

  The first-layer metal lines are a column power supply control line, a column signal output line, and a column controller sequence control line.

  The second layer metal line is a row decoder sequence output control line.

  As can be seen from the above description, the CMOS image sensor pixel according to the present invention employs a 4T2S structure (four transistors, two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region). Four pixels are arranged in a 2 × 2 pixel array to form one set. Two pixels in the first column and the second column share a selection transistor, a source follower transistor, a reset transistor, and a floating active region, respectively, and the first column and the second column are arranged in a staggered manner. The In addition, only the first layer metal and the second layer metal are used to interconnect the elements. The third layer metal is not used as an element interconnect, and the height of the medium on the surface of the photodiode Si (silicon) can be lowered and more light can be incident on the photodiode. According to the CMOS image sensor pixel structure and the arrangement method of each transistor of the present invention, only two rows of second-layer metal lines are arranged between adjacent row pixels, and the first of two columns at the maximum between adjacent column pixels. The function can be realized by arranging the metal wires of the layers. This metal wire structure effectively increases the metal window aperture ratio. Also, based on the pixel structure of the present invention, two types of control sequences can be used: a CMOS image sensor pixel array row decoder sequence and a column controller sequence.

  Since the CMOS image sensor pixel structure of the present invention can improve the sensitivity by increasing the light utilization efficiency of the small area pixel sensor, the image quality of the small area pixel image sensor can be effectively increased.

FIG. 1 is a schematic layout diagram of a 4T2S cross-type structure composed of four pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 2 is a circuit schematic diagram of a 4T2S crossing structure of four pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 3 is a schematic diagram of a 6 × 4 pixel array layout in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 4 is a schematic diagram of a 6 × 4 pixel array circuit in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 5 is a schematic diagram of a pixel array with a row decoder and a column controller in a specific embodiment of a CMOS image sensor pixel provided by the present invention. FIG. 6 is a schematic diagram of a row decoder sequence and a column controller sequence of a pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention.

  Next, together with the drawings in the embodiments of the present invention, technical techniques in the embodiments of the present invention will be described clearly and completely.

  A preferred specific embodiment of the CMOS image sensor pixel and its control sequence of the present invention is as shown in FIGS.

  A photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, a floating active region, a first layer metal line, and a second layer metal line are included. The pixel 01 and the pixel 11 located in the pixel array column 1 share the selection transistor SX1, the source follower transistor SF1, the reset transistor RX1, and the floating active region FD1. The pixel 12 and the pixel 22 located in the pixel array column 2 share the selection transistor SX2, the source follower transistor SF2, the reset transistor RX2, and the floating active region FD2. The selection transistor SX1, the source follower transistor SF1, and the reset transistor RX1 are located between the photodiode PD01 of the pixel 01 and the photodiode PD11 of the pixel 11. The selection transistor SX2, the source follower transistor SF2, and the reset transistor RX2 are located between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22. As for the pixel 01 and the pixel 11, the pixel 12 and the pixel 22 form a cross structure in the horizontal direction.

  The selection transistor SX1 is located on the upper left side of the photodiode PD01 and the lower left side of the photodiode PD11, and is located on the left side of the source follower transistor SF1.

  The selection transistor SX2 is located on the upper right side of the photodiode PD12 and on the lower right side of the photodiode PD22, and is located on the right side of the source follower transistor SF2.

  The source follower transistor SF1 is located immediately above the photodiode PD01 and directly below the photodiode PD11.

  The source follower transistor SF2 is located immediately above the photodiode PD11 and directly below the photodiode PD22.

  The floating active region FD1 is located between the photodiode PD01 of the pixel 01 and the photodiode PD11 of the pixel 11, and is located on the left side of the reset transistor RX1.

  The floating active region FD2 is located between the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22, and is located on the right side of the reset transistor RX2.

  The floating active region FD1 is connected to the gate of the source follower transistor SF1 by a metal line of the first layer.

The floating active region FD2 is connected to the gate of the source follower transistor SF2 by the first layer metal line.

  The metal line Vdd of the first layer of the power supply is connected to the drains of SX1, SX2, RX1 and RX2.

  The first-layer metal line SC1 is connected to the source of the source follower transistor SF1 and the gate of the reset transistor RX2, and the first-layer metal line SC2 is connected to the source of the source follower transistor SF2 and the gate of the reset transistor RX1. Connected to.

  The first-layer metal line SC1 and the first-layer metal line SC2 are a signal output line and a column controller sequence control line.

  The second-layer metal line S1 is connected to the gate of the selection transistor SX1. The second-layer metal line S2 is connected to the gate of the selection transistor SX2.

  The metal line T1 of the second layer is connected to the gates of the charge transfer transistor TX11 and the charge transfer transistor TX12. The second-layer metal line T2 is connected to the gate of the charge transfer transistor TX22.

  The second-layer metal line S1 and the second-layer metal line S2, the second-layer metal line T1 and the second-layer metal line T2 are row decoder sequence output control lines.

  The present invention solves the problem that a conventional image sensor has low sensitivity of a small area pixel.

  As shown in FIG. 1, the CMOS image sensor pixel adopts a 4T2S structure, includes four pixels, and the photodiodes of the pixel 01, the pixel 11, the pixel 12, and the pixel 22 are PD01, PD11, PD12, and PD22, respectively. . TX01 and TX11 are charge transfer transistors of the pixel 01 and the pixel 11, respectively, and TX12 and TX22 are charge transfer transistors of the pixel 12 and the pixel 22, respectively. SX1, SF1, and RX1 are a selection transistor, a source follower transistor, and a reset transistor of the pixel 01 and the pixel 11, respectively. SX2, SF2, and RX2 are a selection transistor, a source follower transistor, and a reset transistor of the pixel 12 and the pixel 22, respectively. Pixel 01 and pixel 11 jointly use transistors SX1, SF1, RX1 and floating active region FD1 (Floating Diffusion), and pixel 12 and pixel 22 jointly use transistors SX2, SF2, RX2 and floating active region FD2. The shared pixel 01 and the pixel 11 and the shared pixel 12 and the pixel 22 form a cross structure in the horizontal direction.

  The metal interconnections used in CMOS image sensor pixels are as follows. The floating active region FD1 is connected to the gate of the transistor SF1 by a metal line of the first layer. The floating active region FD2 is connected to the gate of the transistor SF2 by the metal line of the first layer. The metal line Vdd of the first layer of the power supply is connected to the drains of SX1, SX2, RX1 and RX2. The SC1 line is a first layer metal line connected to the source of SF1 and connected to the gate of RX2, and the SC1 first layer metal line is a signal output line and also a column controller sequence control line. The SC2 line is a first layer metal line connected to the source of SF2 and connected to the gate of RX1, and the SC2 first layer metal line is a signal output line and also a column controller sequence control line. The S1 line is a second layer metal line and is connected to the gate of SX1. The S2 line is a second-layer metal line and is connected to the gate of SX2. The T1 line is a second-layer metal line and is connected to the gates of TX11 and TX12. The T2 line is a second layer metal line and is connected to the gate of TX22. The S1 second layer metal line, the S2 second layer metal line, the T1 second layer metal line, and the T2 second layer metal line are all row decoder sequence output control lines.

  FIG. 2 is a schematic diagram of a crossed circuit structure including the four pixels described above. As shown in FIGS. 3 and 4, the above-described four pixels are set as one set, and a plurality of sets of intersecting pixels are arranged in a two-dimensional pixel array in the vertical and horizontal directions.

  FIG. 3 is a schematic diagram of a 6 × 4 pixel array layout. A circuit schematic diagram corresponding to the pixel array layout schematic diagram shown in FIG. 3 is as shown in FIG.

  In the pixel arrays shown in FIG. 3 and FIG. 4, the FD region of each pixel is connected to the corresponding source follower transistor gate and the first layer metal line, and the power supply Vdd line is the first layer metal line. Is used. The SC0 to SC5 lines are metal lines of the first layer, and are connected as signal output lines and column controller sequence control lines to the source of the source follower transistor and the gate of the reset transistor of the corresponding column pixel, respectively. The second-layer metal lines S1 to S4 are respectively connected to the gates of the selection transistors of the corresponding row pixels, and the second-layer metal lines T1 to T4 are respectively connected to the gates of the transfer transistors of the corresponding row pixels. Is done. In this two-dimensional pixel array, interconnections are made using only two layers of metal, there are only two rows of second-layer metal lines between adjacent row pixels, and a maximum of 2 between adjacent column pixels. It has metal lines in the first layer of the row. The present invention effectively increases the sensitivity of small area pixel sensors by using only two layers of metal and a high metal window aperture ratio.

  Details of the CMOS image sensor pixel array signal acquisition are as follows.

  FIG. 5 is a schematic diagram of a pixel array with a row decoder and a column controller. The row decoder is placed on the left side of the pixel array (may be placed on the right side of the array), the column controller is placed on the top of the pixel array (may be placed on the bottom of the array), and the signal readout element is placed on the pixel array. Put on the bottom of the. The positions of the decoder, the controller, and the signal reading element are not the only methods of the present invention, and may be adjusted according to the specific design layout of the chip. In the schematic shown in FIG. 5, specific positions of the array pixels are specified in detail, and specific numbers of decoder sequence output control lines and column controller sequence control lines are also specified in detail. m and n are non-negative integers and represent the row and column positions of the pixels of the pixel array, respectively. For example, the pixel (m + 1, n + 1) indicates that the position of this pixel is in the (m + 1) th row and the (n + 1) th column. The metal line Vdd is a power supply line, and when the sensor is operating normally, Vdd is a power supply voltage. The metal line SC is a signal output line and a column controller sequence control line, and the metal lines S and T are row decoder sequence output control lines.

  FIG. 6 is a schematic diagram of a row decoder output sequence and a column controller sequence employed in the CMOS image sensor pixel array. The pixel array of the present invention employs all N-type transistors. When the gate of the N-type transistor is placed at a high level, that is, when the sequence line of the gate of this transistor is controlled to be placed at a high level, this indicates that the transistor is on. When the gate of an N-type transistor is placed at a low level, that is, when the sequence line of the gate of this transistor is controlled to be placed at a low level, it indicates that the transistor is turned off. The control of the length of the ON time of the N-type transistor, that is, the length of time for which the sequence line of the gate of the transistor is placed at a high level depends on the specific situation of the operation of the sensor. When the signal readout element at the bottom of the pixel array reads the signal, the SC line is converted from the column controller sequence control line to the signal output line, and the signal readout element reads the signal through the signal output line. The SC sequence in FIG. 6 represents the SC control line sequence of all the columns of the pixel array, and a rectangle having diagonal lines indicates an operation in which the signal reading element reads the pixel signal, and signal 1 corresponds to the sequence read signal of the sequence SHR. Signal 2 corresponds to the sequence read signal of sequence SHS. After the pixel signal is read by the signal readout element, the signal output line is converted into a column controller sequence control line.

  When the CMOS image sensor pixel array of the present invention operates normally, a row scroll type exposure method is adopted, pixels in the mth row start exposure first, then pixels in the (m + 1) th row start exposure, It becomes m + 2 line, m + 3 line, m + 4 line, and m + 5 line. The order of the end of exposure between the pixels in the row is the same as the order of the exposure start. The signal reading order between the pixels in the row is also the same as the exposure start sequence of the row pixels. When the sensor collects pixel array signals for the same frame, the exposure times for the pixels in each row are equal.

  Next, the signal reading operation for the pixels in the (m + 1) th row will be described in detail. The exposure time of the pixels in the (m + 1) th row is from the first high level falling of the T <m + 1> sequence line to the next high level falling of the T <m + 1> sequence line. Prior to the start of the exposure time, the charge placed in the potential well of the pixel photodiode needs to be removed, ie, the S <m + 1> sequence line and the S <m + 2> sequence line are at a low level, and T <m + 1 > Sequence line and SC sequence line are placed from low level to high level, and the charge transfer transistor and reset transistor of the (m + 1) th row pixel are turned on. After the charge placed in the potential well of the pixel photodiode is removed, the charge transfer transistor is first turned off and then the reset transistor is turned off, that is, S <m + 1> sequence line and S <m + 2> sequence. The line is at the low level, and the T <m + 1> sequence line and the SC sequence line are placed at the low level in order from the high level. At this time, the pixel photodiodes in the (m + 1) th row start exposure. During pixel exposure, the T <m + 1> sequence line is always low. Prior to the end of the exposure time, it is necessary to collect the pixel reset signal. First, the T <m + 1> sequence line is at a low level, the S <m + 1> sequence line is at a high level, and the S <m + 2> sequence line. And the SC sequence line is placed from the low level to the high level, the pixel reset transistor and the selection transistor in the (m + 1) th row are turned on, and the corresponding FD region of the pixel is reset to the high level. After resetting the FD region to high level, the SC sequence line is put from high level to low level, the reset transistor is closed, and the S <m + 1> sequence and S <m + 2> sequence line remain high and do not change. The SC line is then converted from the column controller control line to the signal output line, the T <m + 1> sequence line remains low, the S <m + 1> sequence line and the S <m + 2> sequence line remain high, and the signal output The signal readout element reads the signal of each pixel in the (m + 1) th row using the SHR sequence line via the line SC and stores it as a signal 1. After reading signal 1, the S <m + 1> sequence line and the S <m + 2> sequence line remain high, the SC line remains as the signal output line, and the T <m + 1> sequence line is placed from low to high. The transfer transistor is turned on. After the photoelectric charge in the potential well of the photodiode has moved to the corresponding FD region of the pixel and the photoelectric charge in the potential well of the pixel photodiode has moved to the corresponding FD region of the pixel, the charge transfer transistor is turned off, That is, the SC line is kept as a signal output line, the S <m + 1> sequence line and the S <m + 2> sequence line are at a high level, the T <m + 1> sequence line is placed from a high level to a low level, and the exposure time is finish. Next, the signal readout element reads the signal of each pixel in the (m + 1) th row through the signal output line SC and through the SHS sequence to obtain a signal 2. After reading signal 2, the signal readout element stops reading the pixel signal, the S <m + 1> sequence is placed from the high level to the low level, the S <m + 2> sequence remains at the high level, and the SC line outputs the signal. Converted from line to column controller control line.

  The signal reading operation for the pixels in the (m + 2) th row repeats the signal reading operation for the pixels in the (m + 1) th row described above after the pixel signal reading in the (m + 1) th row is completed. The pixel signal reading operations of the (m + 3) th row, the (m + 4) th row, and the (m + 5) th row all repeat the signal reading operation for the pixels of the previous row after the reading of the pixel signals of the previous row is completed. Completion of reading all the row pixel signals in the array is referred to as completion of signal reading of one frame.

  The sequence control method employed in the CMOS image sensor pixel array of the present invention is not the only method. For example, when reading the signal 1 and the signal 2 of the same pixel in the same frame in order through the signal output line, the signal reading element first reads the signal 1, and then first places the S sequence from a high level to a low level. Before the selection transistor is turned off and the signal 2 is read, the signal sequence may be read by the signal read element after the S sequence is further turned on from the low level to the high level. The photoelectric signal collected by the sensor pixel is read and recorded by the signal reading element, and the actual photoelectric signal is a difference signal between the signal 1 and the signal 2.

  The above is only a preferred specific embodiment of the present invention, and the protection scope of the present invention is not limited to this. Any change or replacement readily conceivable by those skilled in the art within the technical scope disclosed in the present invention shall fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (8)

A pixel array including a plurality of sets of pixel cells, each set of pixel cells including a 2 × 2 pixel array structure in which four pixels are arranged, and two of the first column and the second column Each pixel shares a selection transistor, a source follower transistor, a reset transistor, and a floating active region in the column, and the two pixels in the first column and the two pixels in the second column are in the column direction. It is shifted and placed
Arranging the plurality of sets of pixel cells in a two-dimensional pixel array vertically and horizontally;
The pixels in the same row in the two-dimensional pixel array realize element connection by a second layer metal line, and the pixels in the same column realize element connection by a first layer metal line. CMOS image sensor pixel. The arrangement method of the elements of the two pixels in the first column is:
The selection transistor (SX1), the source follower transistor (SF1), and the reset transistor (RX1) are located between the photodiode (PD01) of the pixel (01) and the photodiode (PD11) of the pixel (11),
The arrangement of the elements of the two pixels in the second column is as follows:
The selection transistor (SX2), the source follower transistor (SF2), and the reset transistor (RX2) are located between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22). The CMOS image sensor pixel according to claim 1. In the arrangement method of the elements of the two pixels in the first column, the selection transistor (SX1) is located on the upper left side of the photodiode (PD01) and the lower left side of the photodiode (PD11), and the source follower transistor (SF1). Located on the left side of
In the arrangement method of the elements of the two pixels in the second column, the selection transistor (SX2) is located on the upper right side of the photodiode (PD12) and the lower right side of the photodiode (PD22), and the source follower transistor (SF2). The CMOS image sensor pixel according to claim 2, wherein the CMOS image sensor pixel is located on a right side of. In the arrangement method of the elements of the two pixels in the first column, the source follower transistor (SF1) is located immediately above the photodiode (PD01) and directly below the photodiode (PD11),
The element follower transistor (SF2) is located immediately above the photodiode (PD11) and directly below the photodiode (PD22) in the arrangement of the elements of the two pixels in the second column. A CMOS image sensor pixel as described. In the arrangement method of the elements of the two pixels in the first column, the floating active region (FD1) is located between the photodiode (PD01) of the pixel (01) and the photodiode (PD11) of the pixel (11). And located on the left side of the reset transistor (RX1),
In the arrangement method of the elements of the two pixels in the second column, the floating active region (FD2) is located between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22). The CMOS image sensor pixel according to claim 4, wherein the pixel is located on the right side of the reset transistor (RX2). In the arrangement method of the elements of the two pixels in the first column, the floating active region (FD1) is connected to the gate of the source follower transistor (SF1) by the metal line of the first layer,
The floating active region (FD2) is connected to the gate of the source follower transistor (SF2) by a metal line of the first layer in the arrangement of elements of two pixels in the second column. 5. The CMOS image sensor pixel according to 5.  The control sequence of a CMOS image sensor pixel according to any one of claims 1 to 6, wherein the control sequence includes a CMOS image sensor pixel array row decoder sequence and a column controller sequence. The metal wires of the first layer are a column power supply control line and a column signal output line, and are also a column controller sequence control line,
8. The control sequence of a CMOS image sensor pixel according to claim 7, wherein the second-layer metal line is a row decoder sequence output control line.

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