JP5635728B2 - 半導体装置、及びテスト方法 - Google Patents

半導体装置、及びテスト方法 Download PDF

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Publication number
JP5635728B2
JP5635728B2 JP2008234863A JP2008234863A JP5635728B2 JP 5635728 B2 JP5635728 B2 JP 5635728B2 JP 2008234863 A JP2008234863 A JP 2008234863A JP 2008234863 A JP2008234863 A JP 2008234863A JP 5635728 B2 JP5635728 B2 JP 5635728B2
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JP
Japan
Prior art keywords
circuit
state
switch
power supply
supply line
Prior art date
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Expired - Fee Related
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JP2008234863A
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English (en)
Japanese (ja)
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JP2010067900A (ja
JP2010067900A5 (enExample
Inventor
野田　浩正
浩正 野田
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PS4 Luxco SARL
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PS4 Luxco SARL
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Priority to JP2008234863A priority Critical patent/JP5635728B2/ja
Priority to US12/585,233 priority patent/US8330487B2/en
Publication of JP2010067900A publication Critical patent/JP2010067900A/ja
Publication of JP2010067900A5 publication Critical patent/JP2010067900A5/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2008234863A 2008-09-12 2008-09-12 半導体装置、及びテスト方法 Expired - Fee Related JP5635728B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008234863A JP5635728B2 (ja) 2008-09-12 2008-09-12 半導体装置、及びテスト方法
US12/585,233 US8330487B2 (en) 2008-09-12 2009-09-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008234863A JP5635728B2 (ja) 2008-09-12 2008-09-12 半導体装置、及びテスト方法

Publications (3)

Publication Number Publication Date
JP2010067900A JP2010067900A (ja) 2010-03-25
JP2010067900A5 JP2010067900A5 (enExample) 2011-09-15
JP5635728B2 true JP5635728B2 (ja) 2014-12-03

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ID=42006665

Family Applications (1)

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JP2008234863A Expired - Fee Related JP5635728B2 (ja) 2008-09-12 2008-09-12 半導体装置、及びテスト方法

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US (1) US8330487B2 (enExample)
JP (1) JP5635728B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5061212B2 (ja) * 2010-03-29 2012-10-31 株式会社日立製作所 半導体装置およびその制御方法
CN102420519B (zh) * 2011-12-22 2013-11-27 东南大学 一种自适应调整功率管栅宽的控制电路
KR20180127776A (ko) * 2017-05-22 2018-11-30 에스케이하이닉스 주식회사 전원 게이팅 회로를 포함하는 반도체 장치 및 이의 리페어 방법
KR102420005B1 (ko) * 2017-12-21 2022-07-12 에스케이하이닉스 주식회사 파워 게이팅 제어 회로
US11303274B1 (en) * 2020-11-16 2022-04-12 Micron Technology, Inc. Sub-threshold current reduction circuit switches and related apparatuses and methods

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3239581B2 (ja) * 1994-01-26 2001-12-17 富士通株式会社 半導体集積回路の製造方法及び半導体集積回路
JP3725911B2 (ja) * 1994-06-02 2005-12-14 株式会社ルネサステクノロジ 半導体装置
JPH09261013A (ja) * 1996-03-19 1997-10-03 Fujitsu Ltd Ｄフリップフロップ回路
JP4390304B2 (ja) * 1998-05-26 2009-12-24 株式会社ルネサステクノロジ 半導体集積回路装置
JP3926037B2 (ja) 1998-07-16 2007-06-06 エルピーダメモリ株式会社 ダイナミック型ｒａｍ
JP3187775B2 (ja) * 1998-08-10 2001-07-11 日本電気株式会社 論理回路
JP4390305B2 (ja) 1999-01-04 2009-12-24 株式会社ルネサステクノロジ 半導体装置
JP2001053599A (ja) * 1999-08-12 2001-02-23 Nec Corp 半導体集積回路
JP4910259B2 (ja) * 2001-07-25 2012-04-04 日本テキサス・インスツルメンツ株式会社 半導体集積回路
JP2003168735A (ja) * 2001-11-30 2003-06-13 Hitachi Ltd 半導体集積回路装置
JP3951773B2 (ja) * 2002-03-28 2007-08-01 富士通株式会社 リーク電流遮断回路を有する半導体集積回路
JP4052923B2 (ja) * 2002-10-25 2008-02-27 株式会社ルネサステクノロジ 半導体装置
JP4549026B2 (ja) * 2003-01-14 2010-09-22 富士通セミコンダクター株式会社 半導体集積回路
US7276932B2 (en) * 2004-08-26 2007-10-02 International Business Machines Corporation Power-gating cell for virtual power rail control
US7659746B2 (en) * 2005-02-14 2010-02-09 Qualcomm, Incorporated Distributed supply current switch circuits for enabling individual power domains
KR20080034429A (ko) * 2005-07-08 2008-04-21 제트모스 테크놀로지 인코포레이티드 소스 트랜지스터 구성 및 제어 방법
US7219244B2 (en) * 2005-08-25 2007-05-15 International Business Machines Corporation Control circuitry for power gating virtual power supply rails at differing voltage potentials
JP2007208004A (ja) * 2006-02-01 2007-08-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置及び電子装置
JP5141337B2 (ja) * 2008-03-31 2013-02-13 富士通株式会社 半導体装置および半導体装置の試験方法

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Publication number Publication date
JP2010067900A (ja) 2010-03-25
US8330487B2 (en) 2012-12-11
US20100066406A1 (en) 2010-03-18

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