JP5629926B2 - 半導体パッケージおよびその製造方法 - Google Patents

半導体パッケージおよびその製造方法 Download PDF

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Publication number
JP5629926B2
JP5629926B2 JP2010179978A JP2010179978A JP5629926B2 JP 5629926 B2 JP5629926 B2 JP 5629926B2 JP 2010179978 A JP2010179978 A JP 2010179978A JP 2010179978 A JP2010179978 A JP 2010179978A JP 5629926 B2 JP5629926 B2 JP 5629926B2
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JP
Japan
Prior art keywords
lid
semiconductor package
cavity
peripheral wall
metallized layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010179978A
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English (en)
Japanese (ja)
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JP2012039022A5 (enExample
JP2012039022A (ja
Inventor
白石　晶紀
晶紀 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010179978A priority Critical patent/JP5629926B2/ja
Publication of JP2012039022A publication Critical patent/JP2012039022A/ja
Publication of JP2012039022A5 publication Critical patent/JP2012039022A5/ja
Application granted granted Critical
Publication of JP5629926B2 publication Critical patent/JP5629926B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Pressure Welding/Diffusion-Bonding (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2010179978A 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法 Active JP5629926B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010179978A JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010179978A JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Publications (3)

Publication Number Publication Date
JP2012039022A JP2012039022A (ja) 2012-02-23
JP2012039022A5 JP2012039022A5 (enExample) 2013-08-08
JP5629926B2 true JP5629926B2 (ja) 2014-11-26

Family

ID=45850656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010179978A Active JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Country Status (1)

Country Link
JP (1) JP5629926B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5979994B2 (ja) 2012-06-12 2016-08-31 新光電気工業株式会社 電子装置
JP6155617B2 (ja) * 2012-12-13 2017-07-05 セイコーエプソン株式会社 電子デバイス、電子機器および移動体
CN114361122B (zh) * 2021-08-11 2025-03-11 华为技术有限公司 功率模块的封装结构及封装方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010178113A (ja) * 2009-01-30 2010-08-12 Kyocera Kinseki Corp 圧電デバイス

Also Published As

Publication number Publication date
JP2012039022A (ja) 2012-02-23

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