JP5593308B2 - 促進された導電性を有する非パンチスルー半導体チャネルを備えた半導体素子及び製法 - Google Patents
促進された導電性を有する非パンチスルー半導体チャネルを備えた半導体素子及び製法 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Description
この出願は、一般的に半導体素子と当該素子を製造する方法に関するものである。
前記基板層上の前記第一導電型の半導体材料の第一層、
前記第一層上の前記第一導電型の半導体材料の上昇領域であって、上部表面と第一及び第二テーパー状側壁とを含む上昇領域、
前記上昇領域の前記第一及び第二側壁と前記上昇領域に隣接した前記第一層の前記上部表面上の前記第一導電型と異なる第二導電型半導体材料、及び
前記上昇領域の前記上部表面上の前記第一導電型の半導体材料の第三層
を含み、
前記上昇領域が、前記第三層に隣接した、第一平均ドーパント濃度をもつ第一の部分と、前記第一の部分と前記第一層との間で、第二平均ドーパント濃度をもつ第二の部分とを含み、前記第一平均ドーパント濃度が前記第二平均ドーパント濃度より低く、前記第二平均ドーパント濃度が前記第一層の平均ドーパント濃度より高い
半導体素子が提供される。
前記第二層は、前記第三層に隣接する、第一平均ドーパント濃度をもつ第一の部分と、前記第一の部分と前記第一層との間の、第二平均ドーパント濃度をもつ第二の部分とを含み、前記第一平均ドーパント濃度が前記第二平均ドーパント濃度より低く、前記第二平均ドーパント濃度が前記第一層の前記平均ドーパント濃度よりも高い。
[1] J.N. Merret,I.Sankin, V. Bonderenko CE. Smith, D. Kajfez, and J.R.B. Casady, “RF and DC Characterization of Self−aligned L−band 4H−SiC Static induction Trasnsistor,” Materials Science Form Vols. 527−529 (2006) pp. 1223−1226
[2] J.H. Zhao, K. Tone, X. Li, P. Alexandrov, L. Fursin and M. Weiner, “3.6mΩ・cm2, 1726V 4H−SiC normally off trenched−and−implanted vertical JFETs and circuit appliactions”, IEE Proc.−Circuits Devices Syst., Vol. 151,No.3 June 2004.
[3] P. Sannuti, X. Li, F. Yan, K. Sheng, J.H. Zhao, “Channel electron mobility in 4H−SiC lateral junction field effect transistors”, Solid−State Electronics 49 (2005) 1900−1904
[4] W. Shockley, “A Unipolar”Field−Effect” Transistor”, Proceedings of the IRE Volume 40, Issue 11, Nov. 1952, pp., 1365−1376
[5] I. Sankin, ”Edge termination and RESURF TECHNOLOGY IN POWER SILICON CARBIDE DEVICES”, Ph. D. Disertation, Mississippi State University, 2006, AAT 321369, p. 110.
[6]M. Nagata, T. Msuhara, N. Hashimoto, H. Masuda, “A short−channel, punch−through−breakdown−free MOS transistor”, International Electron Devices Meeting, 1971 Volume 17, 1971 Page(s): 2−3
[7] Legacy CACE User’s Guide AixRecipe; Recipe Language for AIXTRON systems, Copyright 1994−2004, AIXTRON AG, Kaskerstrasse 15−17 D−52072 Aachen, Germany.
Claims (21)
- 第一導電型の半導体材料の基板層を含み、
前記基板層上の前記第一導電型の半導体材料の第一層を含み、
前記第一層上の前記第一導電型の半導体材料の上昇領域を含み、該上昇領域は、上部表面と第一及び第二テーパー状側壁とを含み、
前記上昇領域の前記第一及び第二側壁と前記上昇領域に隣接した前記第一層の前記上部表面上の前記第一導電型と異なる第二導電型の半導体材料を含み、
該第二導電型の半導体材料が前記第一導電型の半導体材料と整流接合を形成し、
そして、前記上昇領域の前記上部表面上の前記第一導電型の半導体材料の第三層を含み、
前記上昇領域の第一導電型の半導体材料が、前記第三層に隣接して配置された、第一平均ドーパント濃度をもつ第一の部分と、前記第一の部分と前記第一層との間に配置された、第二平均ドーパント濃度をもつ第二の部分とを含み、前記第一平均ドーパント濃度が前記第二平均ドーパント濃度より低く、前記第二平均ドーパント濃度が前記第一層の平均ドーパント濃度より高いことを特徴とする半導体素子。 - 前記上昇領域が、前記上昇領域の前記第一の部分と第二の部分との間で第三平均ドーパント濃度をもつ第三の部分をさらに備え、前記第三平均ドーパント濃度が前記第一層平均ドーパント濃度より高く、前記第三ドーパント濃度が前記第二平均ドーパント濃度より低いことを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第三の部分が、前記上昇領域の前記上部表面に対して垂直方向に0.25μmから0.75μmの厚さを有することを特徴とする請求項2記載の素子。
- 前記上昇領域の前記第三の部分の前記ドーパント濃度が前記上昇領域の前記上部表面に対して垂直方向に不均一であり、前記上昇領域の前記第二の部分に隣接する前記上昇領域の前記第三の部分の前記ドーパント濃度が、前記第一層に隣接する前記上昇領域の前記第三の部分における前記ドーパント濃度より高いことを特徴とする請求項2記載の素子。
- 前記第三平均ドーパント濃度が1x1016cm−3から1x1017cm−3であることを特徴とする請求項2記載の素子。
- 前記半導体材料が広いバンドギャップ半導体材料であることを特徴とする請求項1記載の素子。
- 前記半導体材料がSiCであることを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第一の部分の前記平均幅が、前記上昇領域の前記上部表面に平行な方向に0.3μm乃至1.7μmであることを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第一の部分が、前記上昇領域の前記上部表面に対して垂直方向に0.25μmから1μmの厚さを有することを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第二の部分が、前記上昇領域の前記上部表面に対して垂直方向に0.5μmから3μmの厚さを有することを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第一の部分における前記ドーパント濃度が一様であり、前記上昇領域の前記第二の部分における前記ドーパント濃度が前記上昇領域の前記上部表面に対して垂直方向に階段状の関係で、または、線形関係で変化することを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第一と前記第二の部分における前記ドーパント濃度が、前記上昇領域の前記上部表面に対して垂直方向に線形関係で変化することを特徴とする請求項1記載の素子。
- 前記素子が接合型電界効果トランジスタ(JFET)、スタティック誘導トランジスタ(SIT)、接合型電界効果サイリスタ、又はJFET電流リミッタであることを特徴とする請求項1記載の素子。
- 前記素子が2.4MV/cm以下の印加電場での挙動を通じてパンチスルーを示すことを特徴とする請求項1記載の素子。
- 前記上昇領域の前記第一側壁上及び前記第一側壁に隣接する前記第一層の前記上部表面上の前記第二導電型の前記半導体材料上の第一ゲートコンタクトと、
前記上昇領域の前記第二側壁上及び前記第二側壁に隣接する前記第一層の前記上部表面上の前記第二導電型の前記半導体材料上の第二ゲートコンタクトと、
前記第三層上のソースコンタクトと、
前記第一層に対向する前記基板層上のドレインコンタクトと
をさらに備えてなることを特徴とする請求項1記載の素子。 - 請求項15の前記半導体素子を備えることを特徴とする回路。
- 前記第一及び第二ゲートコンタクトが電気的に結合されるか、または、電気的に結合されず、および/または、前記回路が集積回路であることを特徴とする請求項16記載の回路。
- 請求項15に記載のとおりの第一及び第二の半導体素子を備え、前記第一素子のソースコンタクトが第二素子のゲートコンタクトと電気的に結合されてなることを特徴とする回路。
- 半導体素子を製造する製法であって、
前記製法は、
第一導電型の半導体材料の第三層を介して選択的にエッチングする工程を含み、前記第三層は前記第一導電型の半導体材料の第二層上にあり、前記第二層は前記第一導電型の半導体材料の第一層上にあり、前記第一層は前記第一導電型の半導体材料の基板層上にあり、前記第三層を介して選択的にエッチングする工程は、下の前記第二層内に選択的にエッチングする工程を含み、これにより前記第一導電型半導体材料の上昇領域が形成され、前記上昇領域は前記第三層の半導体材料を含む上部表面と、前記第二層の半導体材料を含むテーパー状の側壁とを有し、
前記製法は、さらに、
前記上昇領域の前記側壁上、及び前記上昇領域に隣接する前記第一層の前記上部表面上に前記第二層の半導体材料内にドーパントを選択的に打ち込む工程を含み、これにより、前記上昇領域の前記側壁上及び前記上昇領域に隣接する前記第一層の前記上部表面上の前記第一導電型とは異なる第二導電型の半導体材料の領域を形成し、該第二導電型の半導体材料が前記第一導電型の半導体材料と整流接合を形成し、
前記上昇領域の第一導電型の半導体材料が、前記第三層に隣接する、第一平均ドーパント濃度をもつ第一の部分と、前記第一の部分と前記第一層との間の、第二平均ドーパント濃度をもつ第二の部分とを含み、前記第一平均ドーパント濃度が前記第二平均ドーパント濃度より低く、前記第二平均ドーパント濃度が前記第一層の前記平均ドーパント濃度よりも高い
ことを特徴とする製法。 - 前記上昇領域が、前記第二層の前記第一層と前記第二の部分との間で第三平均ドーパント濃度をもつ第三の部分をさらに備え、前記第三平均ドーパント濃度が前記第一層平均ドーパント濃度より高く、前記第三ドーパント濃度が前記第二平均ドーパント濃度より低いことを特徴とする請求項19記載の製法。
- 前記第二層を形成するために、前記第一層上に前記第一導電型の半導体材料をエピタキシャル成長させる工程と、前記第三層を形成するために、前記第二層上に前記第一導電型の半導体材料をエピタキシャル成長させる工程とをさらに含み、
前記第一層上の前記第一導電型の半導体材料をエピタキシャル成長させる工程が、前記表面を前記第一導電型の前記半導体材料を形成するために反応する複数のガスと接触させる工程を含み、前記複数のガスの中の一又は二以上の前記濃度がエピタキシャル成長中に変化して、前記第二層における前記ドーパント濃度が不均一であることを特徴とする請求項19記載の製法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/117,121 US7977713B2 (en) | 2008-05-08 | 2008-05-08 | Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making |
US12/117,121 | 2008-05-08 | ||
PCT/US2009/042983 WO2009137578A2 (en) | 2008-05-08 | 2009-05-06 | Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making |
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JP (1) | JP5593308B2 (ja) |
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EP2289103A4 (en) | 2013-07-31 |
KR20110018891A (ko) | 2011-02-24 |
CA2722942A1 (en) | 2009-11-12 |
US20090278177A1 (en) | 2009-11-12 |
TW200952175A (en) | 2009-12-16 |
CN102084484A (zh) | 2011-06-01 |
TWI415258B (zh) | 2013-11-11 |
AU2009244273A1 (en) | 2009-11-12 |
WO2009137578A3 (en) | 2010-03-04 |
EP2289103A2 (en) | 2011-03-02 |
US20110217829A1 (en) | 2011-09-08 |
US8507335B2 (en) | 2013-08-13 |
US7977713B2 (en) | 2011-07-12 |
JP2011521446A (ja) | 2011-07-21 |
WO2009137578A2 (en) | 2009-11-12 |
CN102084484B (zh) | 2013-06-05 |
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