JP5518624B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a printed wiring board, and more particularly to a printed wiring board having a filled via structure, and a manufacturing method thereof.

  Conventionally, a blind via hole method has been used as one of methods for forming an interlayer conduction path of a printed wiring board. In this method, a conductive metal layer serving as an interlayer conductive path is formed on the inner wall of the bottomed via hole by plating the inner wall of the bottomed via hole opened at a predetermined position (hereinafter referred to as a bottomed via hole). Is the method. However, since the conductive metal layer tends to be thin at the bottom peripheral edge of the bottomed via hole, the conduction reliability of the blind via may be lowered.

  As a method for solving this problem, a via fill plating method is known in which an open bottomed via hole is filled (also referred to as filling) with plating metal (see, for example, Patent Documents 1 and 2).

  Here, the manufacturing method of the flexible printed wiring board by the conventional via fill plating method is demonstrated concretely using FIG.

  FIG. 7 is a process sectional view showing a method for manufacturing a flexible printed wiring board having a bottomed via hole (filled via structure) filled by a via fill plating method according to the prior art.

(1) First, a double-sided copper clad laminate 54 having copper foils 52 and 53 (each 5 μm thick, for example) on the front and back surfaces of a flexible insulating base material 51 (for example 25 μm thick) is prepared. Then, a photosensitive dry film type resist film is laminated on the surface of the double-sided copper-clad laminate 54. Next, development is performed after irradiating the resist film with an exposure pattern of a perfect circle (for example, φ100 μm). As a result, a resist film having a regular circular opening is formed on the copper foil 52.

(2) Next, the copper foil 52 is etched using a resist film having a regular circular opening as a mask. Thereafter, the resist film is peeled off. Thereby, as shown in FIG. 7 (1), a circular metal mask 55 for shielding the laser is formed on the copper foil 52.

(3) Next, a laser beam in an irradiation range larger than that of the metal mask 55 is irradiated onto the metal mask 55 to perform conformal laser processing. As a result, as shown in FIG. 7 (2), a bottomed via hole 56 with the copper foil 53 exposed on the bottom surface is formed at a predetermined position of the double-sided copper clad laminate 54.

(4) Next, a desmear process is performed in the bottomed via hole 56 to remove the resin residue. Thereafter, a conductive process is performed in the bottomed via hole 56 to form a conductive film.

(5) Next, copper is filled into the bottomed via hole 56 by an electrolytic plating method using a copper sulfate plating solution containing an additive for via fill plating. Thereby, the filled via 57 is formed as shown in FIG. A surface layer plating 58 is formed on the copper foil 52 during via fill plating. The thickness of the surface layer plating 58 increases as the time required for via fill plating increases. For example, the thickness of the surface plating 58 is about 25 μm when a sufficient amount of copper is filled in the bottomed via hole 56.

  Further, as shown in FIG. 7 (3), dimples 59 are formed on the filled via 57. When mounting an electronic component, a solder ball of the electronic component may be placed on the dimple 59. At this time, if the amount of the dimple 59 is large, an air gap is generated, which may impair the connection reliability with the electronic component. For this reason, the amount of depression of the dimple 59 is required to be smaller than a predetermined value (for example, a value defined in the specification).

(6) Next, a photofabrication technique is performed on the double-sided copper clad laminate 54 subjected to via filling shown in FIG. 7 (3). Thereby, as shown in FIG. 7 (4), the surface layer plating 58 and the copper foil 52 are processed into a predetermined pattern to form a circuit wiring pattern 60. Note that the photofabrication method includes a series of steps such as formation of a resist layer on the surface plating layer, exposure, development, etching, and removal of the resist layer.

  Since the thickness of the conductor film to be processed (surface plating 58 and copper foil 52) is relatively large at about 30 μm, it is difficult to make the pitch of the circuit wiring pattern 60 formed in this step smaller than, for example, 150 μm.

  As can be seen from the above, conventionally, when a conductor is filled in a bottomed via hole by a via fill plating method, a fine circuit wiring pattern can be formed because the thickness of the surface plating formed on the substrate surface is large. It was difficult.

  In order to solve this problem, it is conceivable to reduce the time required for via fill plating by reducing the diameter of the bottomed via hole by reducing the diameter of the bottomed via hole, thereby reducing the thickness of the surface plating. . However, there is a concern that the reliability of interlayer connection of filled vias may decrease due to the reduced diameter.

  In addition, as a means for reducing the surface plating thickness, a via fill plating method using PR electrolysis is known (for example, see Patent Document 3). However, the power source for PR electroplating is expensive, and there is a concern that the product cost increases due to an increase in capital investment.

  Further, as a problem other than the thickness of the surface plating, there is a variation in the dimple dent amount. In the via fill plating method, the thickness of the surface layer plating and the amount of dimple depression are closely related. Due to the characteristics of electrolytic plating, it is inevitable that the thickness of the surface plating varies to some extent within the sheet surface on which a plurality of printed wiring boards are produced. Due to the thickness distribution of the surface plating, the dimple dent amount also varies. That is, as shown in FIG. 8, in the sheet 61, when the surface plating 58 is thin, the dent amount of the dimple 59 is large (left side in FIG. 8), and the dent amount of the dimple 59 decreases as the surface plating 58 becomes thicker (FIG. 8). 8 middle). And when the surface layer plating 58 becomes more than a certain thickness, the dimple 59 becomes convex (right side in FIG. 8). Such a convex shape becomes unstable when an electronic component is mounted and must be avoided.

  As described above, it is also demanded to reduce the variation in the amount of dimple depression on the filled via.

Japanese Patent Laid-Open No. 03-159298 Japanese Patent No. 4056492 Japanese Patent Application Laid-Open No. 07-336017

  An object of the present invention is to reduce the thickness of the surface plating layer as much as possible and to reduce the variation in the amount of dimple depressions on the filled via as much as possible.

According to one aspect of the present invention, a substrate to be processed having an insulating layer and first and second metal layers provided on a front surface and a back surface of the insulating layer, respectively, is prepared, and a protruding portion directed inward is provided. Forming a first shape metal mask on the first metal layer, and performing conformal laser processing using the metal mask, the second metal layer is exposed on the bottom surface, and the cross section is By forming a bottomed via hole having a first shape and removing a part of the first metal layer and the insulating layer therebelow at the peripheral edge of the metal mask, the cross section does not have a protrusion. Forming an upper via hole having a second shape, corresponding to a lower portion of the bottomed via hole, exposing the second metal layer on a bottom surface, and forming a lower via hole having a transverse cross section of the first shape; Communicate with this lower via hole The step-bottomed via hole composed of the upper via hole is filled with a plating metal by an electrolytic plating method to form a filled via that electrically connects the first metal layer and the second metal layer. A method of manufacturing a featured printed wiring board is provided.

  According to another aspect of the present invention, the insulating layer, the first and second metal layers provided on the front surface and the back surface of the insulating layer, respectively, and the second metal layer exposed on the bottom surface, A first lower shape via hole having an inward protruding portion, a lower via hole communicating with the lower via hole, having a diameter larger than the diameter of the lower via hole, and having a cross section having no protruding portion. The first metal layer is formed of a step-bottomed via hole having an opening surface in the first metal layer, and a plated metal filled in the step-bottomed via hole. And a filled via for electrically connecting the second metal layer and the printed wiring board.

  Due to these features, the present invention has the following effects.

  When filling the plating metal into the step-bottomed via hole composed of the upper via hole and the lower via hole, the cross sectional shape of the lower via hole has an inward projection, so the deposition amount of the plating metal depends on the characteristics of via fill plating Will increase. Therefore, the time for filling the plated metal in the lower via hole can be shortened compared to the conventional case. As a result, the total time required for via fill plating is shortened, and the thickness of the surface plating formed on the first metal layer can be reduced.

  Furthermore, since the diameter of the upper via hole is larger than that of the lower via hole, and the upper via hole has no protrusion, the plating speed when filling the upper via hole is lower than when filling the lower via hole. . Thereby, it is possible to avoid the formation of the convex portion on the filled via and to reduce the variation in the amount of depression of the formed dimple.

  In addition, since the circumference of the first shape is longer than when there is no protrusion, the resistance to the thermal stress of the filled via is increased, and the interlayer connection reliability is improved.

It is a figure which shows the manufacturing method of the flexible printed wiring board which has the filled via structure which concerns on the 1st Embodiment of this invention. It is a figure which shows the manufacturing method of the flexible printed wiring board which has the filled-via structure based on the 1st Embodiment of this invention following FIG. 1A. It is a figure which shows the manufacturing method of the flexible printed wiring board which has the filled-via structure based on the 1st Embodiment of this invention following FIG. 1B. It is a figure which shows the manufacturing method of the flexible printed wiring board which has the filled-via structure based on the 1st Embodiment of this invention following FIG. 1C. It is a figure which shows the manufacturing method of the flexible printed wiring board which has the filled-via structure based on the 1st Embodiment of this invention following FIG. 1D. It is a figure for demonstrating the bottomed via hole which concerns on embodiment of this invention. It is a figure for demonstrating the via filling process which concerns on embodiment of this invention. It is a figure which shows the relationship between plating time and the plating thickness in a via | veer. It is a figure which shows the manufacturing method of the multilayer flexible printed wiring board which has the filled via structure which concerns on the 2nd Embodiment of this invention. It is a figure which shows the manufacturing method of the multilayer flexible printed wiring board which has the filled-via structure based on the 2nd Embodiment of this invention following FIG. 5A. It is a figure which shows the modification about the shape of the cross section of a lower side via hole. It is a figure which shows the manufacturing method of the multilayer flexible printed wiring board which has a filled via structure by a prior art. It is a figure for demonstrating the dispersion | variation in the sheet | seat surface of the dimple formed on the filled via | veer. It is a figure for demonstrating the via fill plating with respect to the bottomed via hole which concerns on a comparative example.

  Before describing the embodiment of the present invention, a comparative example will be described.

  As can be seen from the above description, in order to reduce the thickness of the surface plating and to reduce the pitch of the circuit wiring pattern, it is necessary to shorten the time required for via fill plating.

  In view of this, the present inventors first considered using the property that the plated metal is likely to be deposited in a square portion in the via fill plating method (electrolytic plating method). Specifically, as can be seen from FIGS. 9A and 9B, a bottomed via hole 62 having a non-circular shape such as a polygonal cross section is formed, and a filled via is formed using a via fill plating method. I thought. In this case, the plating deposition amount increases in the bottomed via hole 62, and the time for filling the conductor in the bottomed via hole 62 is shortened. As a result, the thickness of the surface plating can be reduced.

  However, as shown in FIGS. 9A and 9B, the convex portion 64 is formed on the filled via 63 because the plating formation speed is high. Such a convex portion 64 should be avoided when mounting the electronic component on the filled via 63. In order to remove the convex part 64, it is necessary to add a grinding | polishing process newly, and also there exists a possibility of causing the fall of a yield while a manufacturing cost rises. In particular, in the case of a flexible printed wiring board, it is not easy to evenly polish a thin and flexible sheet.

  Further, in the case of the comparative example, since the plating speed is high, there is a possibility that the variation in the amount of dimple dents on the filled via becomes large.

  The present invention has been made based on such technical recognition, and solves the above-described problems as described in the following embodiments.

  Hereinafter, two embodiments according to the present invention will be described with reference to the drawings. In the drawings, components having the same functions are denoted by the same reference numerals, and detailed description of the components having the same reference numerals is not repeated.

(First embodiment)
1A to 1E are views for explaining a method of manufacturing a flexible printed wiring board having a filled via structure according to the first embodiment. In each figure, (a) is a process sectional view, (b ) Shows a plan view of the vicinity of a region where a filled via is formed.

(1) First, a double-sided copper clad laminate 4 having copper foils 2 and 3 (each 5 μm thick, for example) on the front and back surfaces of a flexible insulating base material 1 (for example 25 μm thick) is prepared. Then, a photosensitive dry film type resist film is laminated on the surface of the double-sided copper-clad laminate 4. Next, the resist film is irradiated with a predetermined exposure pattern. As can be seen from FIG. 1A (b), the exposure pattern irradiated here has a star shape having protrusions directed inward. The number of protrusions is twelve, and these protrusions are connected. Thereafter, development is performed, and a resist layer having a star-shaped opening is formed on the copper foil 2.

(2) Next, the copper foil 2 is etched using a resist film having a star-shaped opening as a mask. Thereafter, the resist film is peeled off. As a result, a star-shaped metal mask 5 for shielding the laser is formed on the copper foil 2 as shown in FIGS. The metal mask 5 has a star shape having twelve inwardly connected projections 5a, similar to the opening of the resist film described above.

(3) Next, a laser beam in an irradiation range larger than that of the metal mask 5 is irradiated onto the metal mask 5 to perform conformal laser processing. Thereby, as shown to FIG. 1B (a) and (b), the bottomed via hole 6 which the copper foil 3 exposed to the bottom face is formed in the predetermined position of the double-sided copper clad laminated board 4. FIG. The shape of the cross section of the bottomed via hole 6 is the same as that of the metal mask 5. In addition, as a laser which can be used at this process, a carbon dioxide gas laser, a UV-YAG laser, etc. are mentioned, However, It is preferable to use a carbon dioxide gas laser from a viewpoint of productivity.

(4) Next, direct laser processing is performed by irradiating the metal mask 5 with a laser beam having a high energy density capable of removing the copper foil 2. For example, as can be seen from FIG. 2 (a), trepanning is used in which the peripheral edge of the metal mask 5 is rotated and irradiated with laser light. In addition, a processing method for irradiating the metal mask 5 with laser light in an irradiation range larger than that of the metal mask 5 may be used.

  As a result, as shown in FIGS. 1C (a) and 1 (b) and FIGS. 2 (a) and 2 (b), the copper foil 2 at the peripheral edge of the bottomed via hole 6 and a part of the insulating base material 1 therebelow are removed. The upper via hole 7b having a right circular shape (for example, φ100 μm) is formed by removing. The lower via hole 7 a corresponding to the lower part of the bottomed via hole 6 and the upper via hole 7 b communicating with the lower via hole 7 a constitute a step bottomed via hole 7.

  As shown in FIG. 1C (a), the upper via hole 7b includes an upper insulating via hole 7b1 having a side wall made of the insulating base material 1 and an upper metal via hole 7b2 having a side wall made of the copper foil 2. The side wall of the upper insulating via hole 7b1 is formed obliquely by laser processing, but this is not an essential feature of the present invention. However, by forming the side walls obliquely, there is an advantage that the liquid renewability during the conductive treatment is improved and the conductive film is easily formed.

  In the laser processing in this step, a UV-YAG laser or a carbon dioxide gas laser can be used. Further, the upper via hole 7b may be formed by NC drilling instead of using laser processing.

(5) Next, a desmear process is performed in the step bottomed via hole 7 to remove the resin residue. As the desmear process, it is preferable to perform a resin etching of about 1 μm after the plasma process. By this resin etching, it is possible to remove smear on the bottom surface of the step-bottomed via hole 7 without damaging the insulating base material 1 on the side wall of the step-bottomed via hole 7. Thereafter, a conductive process is performed in the step-bottomed via hole 7 to form a conductive film.

(6) Next, using a copper sulfate plating solution containing an additive for via fill plating (for example, Sulcup EVF-R manufactured by Uemura Kogyo Co., Ltd.), copper is filled into the step-bottomed via hole 7 by an electrolytic plating method. To do. Thereby, as shown to FIG. 1D (a) and (b), while filling the copper foil 2 and the filled via | veer 8 which electrically connects the copper foil 3, the surface layer plating 9 is formed on the copper foil 2. FIG. . Also, as shown in FIGS. 1D (a) and 1 (b), a dimple 10 is formed on the filled via 8.

  Although details of the formation process of the filled via 8 will be described later, the thickness of the surface plating 9 is significantly reduced (about 10 μm) than the conventional one due to the shape of the step-bottomed via hole 7, and the dimple 10 formed on the filled via 8 is formed. The variation of the dent amount is smaller than that of the conventional case.

(7) Next, a photofabrication technique is performed on the double-sided copper-clad laminate 4 subjected to the via filling shown in FIG. 1D (a). Thereby, as shown in FIG. 1E (a), the surface layer plating 9 and the copper foil 2 are processed into a predetermined pattern to form a circuit wiring pattern 11.

  Since the thickness of the surface plating 9 is relatively thin, the thickness of the conductor film to be processed (the surface plating 9 and the copper foil 2) is about 15 μm, which is thinner than the conventional one. For this reason, the formation pitch of the circuit wiring pattern 11 can be made smaller than conventional (for example, 80 μm), and a circuit wiring pattern with a narrow pitch can be formed.

  As shown in FIG. 1E, the printed wiring board according to the present embodiment obtained through the above steps includes an insulating base material 1 and copper foils 2 and 3 provided on the front and back surfaces of the insulating base material 1, respectively. , And a double-sided copper-clad laminate 4 having a base material. The printed wiring board according to the present embodiment includes a step-bottomed via hole 7 formed in the double-sided copper-clad laminate 4 and is made of a plated metal filled in the step-bottomed via hole 7. A filled via 8 for electrically connecting the copper foil 3 is provided. The step-bottomed via hole 7 has an opening in the copper foil 2, the copper foil 3 is exposed on the bottom surface, and the lower via hole 7 a having the same cross-sectional shape as the metal mask 5 is communicated with the lower via hole 7 a. The upper via hole 7b has a circular cross section. The center position of the star in the cross section of the lower via hole 7a and the center position of the regular circle in the cross section of the upper via hole 7b are substantially the same.

  According to the printed wiring board according to the present embodiment, since the circumferential length of the cross-sectional shape of the lower via hole 7a is longer than that without the protrusion, the resistance to the thermal stress of the filled via is increased, and the interlayer connection The reliability of the road is improved.

  Next, the details of the process of forming the filled via 8 by performing via fill plating on the stepped via hole 7 using the electrolytic plating method will be described with reference to FIGS.

  FIGS. 3A to 3C show cross-sectional views of the step-bottomed via hole 7 in the via fill plating process in time series.

  FIG. 3A shows a schematic state at the time when the step of filling the conductor 12 into the lower via hole 7a having a star-shaped cross section is completed. As described above, the via fill plating (electrolytic plating) method has a characteristic that the plated metal is likely to be deposited on the angular portion of the via hole. For this reason, the plating speed in the lower via hole 7a is faster than other portions. However, since the plating speed is high, the convex portion 10A is formed as shown in FIG.

  FIG. 3 (2) shows a schematic state at a point in the middle of the process of filling the conductor 12 in the upper via hole 7b having a regular circular cross section. Since the upper via hole 7b has a larger diameter than the lower via hole 7a and there is no angular portion (projection), the plating rate is reduced. Therefore, as plating progresses, the convex portion 10A disappears, and a dimple 10 having a recess is formed instead.

  FIG. 3 (3) shows a schematic state when the via fill plating is completed. As the plating progresses, the amount of dents in the dimple 10 decreases and finally becomes a predetermined value or less.

FIG. 4 is a graph showing the relationship between the plating time and the plating thickness in the via in the case of the comparative example (see FIG. 9) and the case of the present embodiment. The via plating thickness is the length from the bottom surface of the step-bottomed via hole 7 to the plated metal surface. Via the plating thickness d ₁ in FIG. 4 shows the plating thickness in the via when the lower via hole 7a is filled, as shown in FIG. 3 (1). Via the plating thickness d ₂ shows the plating thickness in the via when the via fill plating process is completed as shown in FIG. 3 (3). Actually, since the plating speed varies within the sheet surface, the via fill plating process is terminated when the in-via plating thickness reaches d ₂ at a place where the plating speed is slow (a place where plating is thin).

As shown in FIG. 4, in the present embodiment, via fill plating proceeds at the same plating rate as in the comparative example until the lower via hole 7a is filled. Then, the plating thickness in the via is reached d _1, the plating rate filling into the upper via hole 7b begins to decrease. Due to the decrease in the plating speed, the variation in the plating thickness in the via, that is, the difference between the plating thickness in the via in the thick plating portion and the plating thickness in the via in the thin plating portion becomes small. At time t ₂ the via fill plating process is completed, variations in plating thickness in the via is delta ₁ as shown in FIG.

On the other hand, in the case of the comparative example, the plating speed remains constant from the beginning to the end. For this reason, the dispersion of the plating thickness in the via increases in proportion to the plating time, and at time t ₁ (<t ₂ ) when the via fill plating process is finished, Δ ₂ larger than Δ ₁ as shown in FIG. Become. In the thick portion of plating, by plating thickness within the via exceeds a predetermined thickness d _3, the convex portion is formed on the filled vias (see FIG. 9).

  As can be seen from the above, according to the present embodiment, the time required for filling the lower via hole 7a is shortened, so that the overall time required for via fill plating is also shortened. Thereby, the thickness of the surface layer plating 9 can be reduced as compared with the prior art.

  Furthermore, according to the present embodiment, since the plating speed when filling the conductor in the upper via hole 7b is lower than that in the lower via hole 7a, the variation in the plating thickness in the via is reduced, and the dimple on the filled via is reduced. The variation in the sheet surface of the dent amount of 10 can be reduced.

  In the description of the above embodiment, the number of protrusions on the star-shaped cross section of the lower via hole 7a is twelve. However, the number is not limited to this, and the number of protrusions is preferably 8 to 32. If the number of protrusions is less than 8, the characteristics of via fill plating that the plating tends to deposit on the angular portions cannot be fully utilized, and the effect of reducing the thickness of the surface plating cannot be sufficiently obtained. On the other hand, when the number of protrusions is more than 32, the groove between the protrusions becomes narrow, so that there is a problem that the chemical solution renewability is lowered during the conductive treatment and it is difficult to form the conductive film. Arise.

(Second Embodiment)
Next, the manufacturing method of a multilayer flexible printed wiring board provided with the filled via structure which concerns on the 2nd Embodiment of this invention is demonstrated.

  5A and 5B show process cross-sectional views of a multilayer flexible printed wiring board having a filled via structure according to the second embodiment.

(1) First, a double-sided copper clad laminate 34 having copper foils 32 and 33 (each 5 μm thick, for example) on the front and back surfaces of a flexible insulating base material 31 (for example 25 μm thick) is prepared.

(2) Next, as can be seen from FIG. 5A (1), through holes 35 are formed at predetermined positions of the double-sided copper-clad laminate 34 using an NC drill.

(3) Next, as can be seen from FIG. 5A (1), after the desmear treatment and the conductive treatment are performed in the through-hole 35, electrolytic plating is performed on the entire surface of the double-sided copper-clad laminate 34, and the inner layer plating film 36 is obtained. Form.

(4) Next, as can be seen from FIG. 5A (1), the photo-fabrication technique is used to process the conductive layer made of the copper foils 32, 33 and the inner layer plating film 36 into a predetermined pattern, and the inner layer circuit wiring pattern. 37 is formed.

(5) Next, as can be seen from FIG. 5A (1), the adhesive is filled in the through holes 35 to form the adhesive layer 38. Thereafter, the single-sided copper-clad laminate 41 having the insulating film 39 and the copper foil 40 on the surface thereof is laminated and bonded to both surfaces of the substrate on which the inner layer circuit wiring pattern 37 is formed via the adhesive layer 38.

(6) Next, as can be seen from FIG. 5A (1), in the same manner as the formation of the metal mask 5 described above, the inwardly protruding portions are formed on the copper foil 40 of the single-sided copper-clad laminate 41 in a predetermined manner. A star-shaped metal mask 42 having a number (for example, 12) is formed.

(7) Next, as can be seen from FIG. 5A (2), the conformal laser processing is performed in the same manner as the above-described bottomed via hole 6 is formed, and the insulating film 39 and the adhesive layer 38 are removed, A bottomed via hole with a star-shaped cross section is formed.

(8) Next, as can be seen from FIG. 5A (2), direct laser processing is performed in the same manner as the formation of the step-bottomed via hole 7 described above, and the copper foil 40 on the peripheral edge of the metal mask 42 and its A portion of the underlying insulating film 39 is removed. This forms a step-bottomed via hole 43 composed of a star-shaped lower via hole 43a having the same cross-sectional shape as that of the metal mask 42 and an upper via hole 43b communicating with the upper via hole 43b having a regular circular shape (φ150 μm). Is done. The side wall of the lower via hole 43 a is composed of an adhesive layer 38 and an insulating film 39. The upper via hole 43b includes an upper insulating via hole 43b1 whose side wall is the insulating film 39 and an upper metal via hole 43b2 whose side wall is the copper foil 40.

(9) Next, as shown in FIG. 5B (3), after the desmear process and the conductive process are performed in the step-bottomed via hole 43, the plating metal is put in the step-bottomed via hole 43 by using a via fill plating technique. Fill. As a result, a filled via 44 that electrically connects the copper foil 40 and the inner plating film 36 and a surface plating 45 on the copper foil 40 are formed. As described above, the time required for via fill plating is shortened by the shape of the step bottomed via hole 43, and the thickness of the surface plating 45 can be reduced. Further, variation in the dimple (not shown) formed on the filled via 44 in the sheet surface can be reduced.

(10) Next, as shown in FIG. 5B (4), the processed conductor film (surface plating 45 and copper foil 40) is processed into a predetermined pattern by using a photofabrication technique, and the outer layer circuit wiring pattern 46 is processed. Form. The thickness of the conductor film to be processed is about 20 μm because the thickness of the surface layer plating 45 is 15 μm and the thickness of the copper foil 40 is 5 μm. Thus, since the thickness of the conductor film to be processed is reduced, the outer layer circuit wiring pattern 46 can be made narrower (for example, 100 μm) than the conventional one.

  The printed wiring board manufacturing method and the printed wiring board according to the present invention have been described above. In the above description of the embodiment, the flexible printed wiring board is taken as an example, but the present invention can also be applied to a printed wiring board other than the flexible printed wiring board.

  In the description of the above embodiment, the metal constituting the circuit wiring pattern and the plating metal filled in the via hole are copper that is advantageous in terms of cost. However, the present invention is not limited to this, for example, aluminum. Other metals such as silver and silver may be used.

  Moreover, the shape of the cross-section of the lower via hole is not limited to the star shape of the embodiment as long as a protruding portion is formed inward so that plating is easily deposited. For example, as shown in FIG. 6A, the protrusions do not have to be connected. Further, the shape of the protrusion may be a shape as shown in FIGS. 6B and 6C.

  The shape of the cross section of the upper via hole is not limited to a circle and may be, for example, an ellipse as long as it has a larger diameter than the shape of the cross section of the lower via hole and does not have a protrusion.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the above-described embodiments. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

1, 31, 51 Insulation base material 2, 3, 32, 33, 40, 52, 53 Copper foils 4, 34, 54 Double-sided copper clad laminates 5, 42, 55 Metal masks 5a, 5b Protrusions 6, 56, 62 Bottomed via holes 7, 43 Step bottomed via holes 7a, 43a Lower via holes 7b, 43b Upper via holes 7b1, 43b1 Upper insulated via holes 7b2, 43b2 Upper metal via holes 8, 44, 57, 63 Filled vias 9, 45, 58 Surface plating 10, 59 Dimple 10A, 64 Projection 11, 60 Circuit wiring pattern 12 Conductor 35 Through hole 36 Inner layer plating film 37 Inner layer circuit wiring pattern 38 Adhesive layer 39 Insulating film 41 Single-sided copper clad laminate 46 Outer layer circuit wiring pattern 61 Sheet

Claims (10)

Preparing a substrate to be processed having an insulating layer and first and second metal layers respectively provided on the front and back surfaces of the insulating layer;
Forming a first-shaped metal mask having an inward protruding portion on the first metal layer, and performing conformal laser processing using the metal mask, the second metal layer is exposed on the bottom surface. And forming a bottomed via hole having a cross section of the first shape,
By removing a part of the first metal layer and the insulating layer below the first metal layer at the peripheral edge of the metal mask, an upper via hole having a second shape whose cross section does not have a protrusion is formed,
A lower via hole corresponding to a lower portion of the bottomed via hole, with the second metal layer exposed on a bottom surface and having a transverse section of the first shape, and the upper via hole communicating with the lower via hole; In the step-bottomed via hole composed of: filling a plating metal by an electrolytic plating technique to form a filled via that electrically connects the first metal layer and the second metal layer;
A printed wiring board manufacturing method characterized by the above.   The method of manufacturing a printed wiring board according to claim 1, wherein the upper via hole is formed by trepanning processing in which a peripheral portion of the metal mask is rotated and irradiated with laser light.   The method of manufacturing a printed wiring board according to claim 1, wherein the upper via hole is formed by irradiating the metal mask with laser light having an irradiation range larger than that of the metal mask.   The method for manufacturing a printed wiring board according to claim 1, wherein the upper via hole is formed by NC drilling.   5. The method of manufacturing a printed wiring board according to claim 1, wherein the number of the protrusions of the first shape is 8 to 32, and the protrusions are connected. 6.   The method of manufacturing a printed wiring board according to claim 1, wherein the second shape is a regular circle or an ellipse.   In the step of filling the plated metal in the step bottomed via hole, a surface layer plating made of the plating metal formed on the first metal layer, and a processed conductor film made of the first metal layer, 7. The printed wiring board manufacturing method according to claim 1, wherein a circuit wiring pattern is formed by processing into a predetermined pattern using a photofabrication technique. An insulating layer;
First and second metal layers respectively provided on the front and back surfaces of the insulating layer;
The second metal layer is exposed on the bottom surface, and the lower via hole is in communication with the lower via hole, which is a first shape having a projecting portion facing inward, and is larger than the diameter of the lower via hole. A step-bottomed via hole having a diameter and an upper via hole having a second cross-sectional shape having no protrusion and having an opening in the first metal layer;
A filled via made of a plated metal filled in the step-bottomed via hole, electrically connecting the first metal layer and the second metal layer;
A printed wiring board comprising:   The method of manufacturing a printed wiring board according to claim 8, wherein the number of the protrusions of the first shape is 8 to 32, and the protrusions are connected.   The method for manufacturing a printed wiring board according to claim 8, wherein the second shape is a regular circle or an ellipse.

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