JP5506172B2 - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

Info

Publication number
JP5506172B2
JP5506172B2 JP2008237942A JP2008237942A JP5506172B2 JP 5506172 B2 JP5506172 B2 JP 5506172B2 JP 2008237942 A JP2008237942 A JP 2008237942A JP 2008237942 A JP2008237942 A JP 2008237942A JP 5506172 B2 JP5506172 B2 JP 5506172B2
Authority
JP
Japan
Prior art keywords
single crystal
film
layer
substrate
crystal semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008237942A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009111354A (ja
JP2009111354A5 (https=
Inventor
舜平 山崎
純一 肥塚
哲弥 掛端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008237942A priority Critical patent/JP5506172B2/ja
Publication of JP2009111354A publication Critical patent/JP2009111354A/ja
Publication of JP2009111354A5 publication Critical patent/JP2009111354A5/ja
Application granted granted Critical
Publication of JP5506172B2 publication Critical patent/JP5506172B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2008237942A 2007-10-10 2008-09-17 半導体基板の作製方法 Expired - Fee Related JP5506172B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008237942A JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007264719 2007-10-10
JP2007264719 2007-10-10
JP2008237942A JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009111354A JP2009111354A (ja) 2009-05-21
JP2009111354A5 JP2009111354A5 (https=) 2011-10-27
JP5506172B2 true JP5506172B2 (ja) 2014-05-28

Family

ID=40533362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008237942A Expired - Fee Related JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Country Status (3)

Country Link
US (1) US7851332B2 (https=)
JP (1) JP5506172B2 (https=)
KR (1) KR101537925B1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021033989A1 (ko) * 2019-08-22 2021-02-25 (주)더숨 디스플레이 제조용 기판 및 이의 제조 방법

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI437696B (zh) * 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
TWI493609B (zh) * 2007-10-23 2015-07-21 半導體能源研究所股份有限公司 半導體基板、顯示面板及顯示裝置的製造方法
US8432021B2 (en) * 2009-05-26 2013-04-30 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US8735191B2 (en) * 2012-01-04 2014-05-27 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding using pedestals
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
JP5680987B2 (ja) * 2011-02-18 2015-03-04 株式会社アドバンテスト 半導体装置、試験装置、および製造方法
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
US9041147B2 (en) * 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus
JP6245791B2 (ja) * 2012-03-27 2017-12-13 日亜化学工業株式会社 縦型窒化物半導体素子およびその製造方法
US9209142B1 (en) 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
KR102407529B1 (ko) * 2015-10-30 2022-06-10 엘지디스플레이 주식회사 플렉서블 표시 장치와 그의 제조 방법
JP6597865B2 (ja) * 2018-10-16 2019-10-30 大日本印刷株式会社 テンプレート基板の製造方法、および、ナノインプリント用テンプレートの製造方法
TWI888525B (zh) * 2020-04-08 2025-07-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法
CN113985219B (zh) * 2021-09-24 2024-05-31 浙江华云电力工程设计咨询有限公司 一种开关柜局部放电和温度联合监测系统及监测方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP4103968B2 (ja) 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6388652B1 (en) 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3525061B2 (ja) * 1998-09-25 2004-05-10 株式会社東芝 半導体発光素子の製造方法
JP4450126B2 (ja) * 2000-01-21 2010-04-14 日新電機株式会社 シリコン系結晶薄膜の形成方法
JP4126912B2 (ja) * 2001-06-22 2008-07-30 セイコーエプソン株式会社 電気光学装置及びその製造方法並びに電子機器
JP4182323B2 (ja) 2002-02-27 2008-11-19 ソニー株式会社 複合基板、基板製造方法
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
TWI351548B (en) * 2003-01-15 2011-11-01 Semiconductor Energy Lab Manufacturing method of liquid crystal display dev
JP2004246028A (ja) * 2003-02-13 2004-09-02 Seiko Epson Corp デバイスの製造方法及びこれを用いて製造されたデバイス、複合基板の製造方法、電気光学装置、並びに電子機器
US7105448B2 (en) * 2003-02-28 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Method for peeling off semiconductor element and method for manufacturing semiconductor device
JP4082242B2 (ja) * 2003-03-06 2008-04-30 ソニー株式会社 素子転写方法
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
JP4624131B2 (ja) * 2005-02-22 2011-02-02 三洋電機株式会社 窒化物系半導体素子の製造方法
JP5084169B2 (ja) * 2005-04-28 2012-11-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7510950B2 (en) * 2005-06-30 2009-03-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20080042095A (ko) * 2005-07-27 2008-05-14 실리콘 제너시스 코포레이션 제어된 클리빙 처리를 이용하여 플레이트 상에 다수의 타일영역을 제작하는 방법 및 구조
US8164257B2 (en) * 2006-01-25 2012-04-24 Samsung Mobile Display Co., Ltd. Organic light emitting display and method of fabricating the same
US7713836B2 (en) * 2006-09-29 2010-05-11 Semiconductor Energy Laboratory Co., Ltd. Method for forming conductive layer and substrate having the same, and method for manufacturing semiconductor device
US8119204B2 (en) * 2007-04-27 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Film formation method and method for manufacturing light-emitting device
KR100882932B1 (ko) * 2007-06-11 2009-02-10 삼성전자주식회사 반도체 기판 및 그 제조 방법, 반도체 소자의 제조 방법 및이미지 센서의 제조 방법
US20100015782A1 (en) * 2008-07-18 2010-01-21 Chen-Hua Yu Wafer Dicing Methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021033989A1 (ko) * 2019-08-22 2021-02-25 (주)더숨 디스플레이 제조용 기판 및 이의 제조 방법

Also Published As

Publication number Publication date
KR101537925B1 (ko) 2015-07-20
US20090096054A1 (en) 2009-04-16
KR20090037352A (ko) 2009-04-15
US7851332B2 (en) 2010-12-14
JP2009111354A (ja) 2009-05-21

Similar Documents

Publication Publication Date Title
JP5506172B2 (ja) 半導体基板の作製方法
US8435871B2 (en) Method for manufacturing semiconductor device, and semiconductor device and electronic device
US8211780B2 (en) Method for manufacturing SOI substrate
JP5250228B2 (ja) 半導体装置の作製方法
TWI437696B (zh) 半導體裝置及其製造方法
CN101393859B (zh) 设置有半导体膜的衬底及其制造方法
US7638408B2 (en) Manufacturing method of substrate provided with semiconductor films
JP5619474B2 (ja) Ｓｏｉ基板の作製方法
US8985173B2 (en) Manufacturing method and manufacturing apparatus of semiconductor substrate
US7816232B2 (en) Method for manufacturing semiconductor substrate and semiconductor substrate manufacturing apparatus
US7816234B2 (en) Method for manufacturing semiconductor device
KR20090037312A (ko) 반도체 장치의 제작 방법
KR101691387B1 (ko) Ｓｏｉ 기판의 제작 방법 및 반도체 장치의 제작 방법
KR20110025110A (ko) 반도체 장치의 제작 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110908

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110908

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130905

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130905

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131224

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140108

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140311

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140318

R150 Certificate of patent or registration of utility model

Ref document number: 5506172

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees