JP5500793B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5500793B2 JP5500793B2 JP2008167487A JP2008167487A JP5500793B2 JP 5500793 B2 JP5500793 B2 JP 5500793B2 JP 2008167487 A JP2008167487 A JP 2008167487A JP 2008167487 A JP2008167487 A JP 2008167487A JP 5500793 B2 JP5500793 B2 JP 5500793B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- crystal semiconductor
- semiconductor layer
- transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
- H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
- H10D86/0225—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using crystallisation-promoting species, e.g. using a Ni catalyst
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Thin Film Transistor (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008167487A JP5500793B2 (ja) | 2007-06-29 | 2008-06-26 | 半導体装置の製造方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007173281 | 2007-06-29 | ||
| JP2007173281 | 2007-06-29 | ||
| JP2008167487A JP5500793B2 (ja) | 2007-06-29 | 2008-06-26 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009033139A JP2009033139A (ja) | 2009-02-12 |
| JP2009033139A5 JP2009033139A5 (enExample) | 2011-07-07 |
| JP5500793B2 true JP5500793B2 (ja) | 2014-05-21 |
Family
ID=40159297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008167487A Expired - Fee Related JP5500793B2 (ja) | 2007-06-29 | 2008-06-26 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7807520B2 (enExample) |
| JP (1) | JP5500793B2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100224880A1 (en) * | 2009-03-05 | 2010-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US9346998B2 (en) | 2009-04-23 | 2016-05-24 | The University Of Chicago | Materials and methods for the preparation of nanocomposites |
| KR101426723B1 (ko) | 2009-10-16 | 2014-08-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시 장치 |
| KR101501420B1 (ko) * | 2009-12-04 | 2015-03-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시 장치 |
| US8759917B2 (en) * | 2010-01-04 | 2014-06-24 | Samsung Electronics Co., Ltd. | Thin-film transistor having etch stop multi-layer and method of manufacturing the same |
| TWI424392B (zh) * | 2010-01-29 | 2014-01-21 | Prime View Int Co Ltd | 主動元件陣列基板及使用其之平面顯示器 |
| WO2011099389A1 (en) * | 2010-02-12 | 2011-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of the same |
| US9093538B2 (en) * | 2011-04-08 | 2015-07-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US9012905B2 (en) * | 2011-04-08 | 2015-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including transistor comprising oxide semiconductor and method for manufacturing the same |
| WO2012158847A2 (en) | 2011-05-16 | 2012-11-22 | The University Of Chicago | Materials and methods for the preparation of nanocomposites |
| JP5912394B2 (ja) * | 2011-10-13 | 2016-04-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| TWI457890B (zh) * | 2012-08-17 | 2014-10-21 | 聚積科技股份有限公司 | Display structure and display |
| JP6824115B2 (ja) * | 2017-06-19 | 2021-02-03 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN110571333B (zh) * | 2019-08-13 | 2023-06-30 | 北京元芯碳基集成电路研究院 | 一种无掺杂晶体管器件制作方法 |
| US11067269B1 (en) * | 2020-01-31 | 2021-07-20 | Dell Products, Lp | System and method for backlight integration with electrical contact foil in piezoelectric haptic keyboard |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0618926A (ja) | 1992-07-02 | 1994-01-28 | Sharp Corp | 液晶表示用大型基板およびその製造方法 |
| JPH0832038A (ja) * | 1994-07-15 | 1996-02-02 | Komatsu Electron Metals Co Ltd | 貼り合わせsoi基板の製造方法および貼り合わせsoi基板 |
| JPH0927452A (ja) * | 1995-07-12 | 1997-01-28 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US5710057A (en) * | 1996-07-12 | 1998-01-20 | Kenney; Donald M. | SOI fabrication method |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
| JP3997682B2 (ja) * | 2000-03-13 | 2007-10-24 | セイコーエプソン株式会社 | 電気光学装置の製造方法及び電気光学装置 |
| US6602758B2 (en) * | 2001-06-15 | 2003-08-05 | Agere Systems, Inc. | Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing |
| JP3696131B2 (ja) * | 2001-07-10 | 2005-09-14 | 株式会社東芝 | アクティブマトリクス基板及びその製造方法 |
| JP2003282885A (ja) * | 2002-03-26 | 2003-10-03 | Sharp Corp | 半導体装置およびその製造方法 |
| US7119365B2 (en) | 2002-03-26 | 2006-10-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate |
| JP4103447B2 (ja) * | 2002-04-30 | 2008-06-18 | 株式会社Ihi | 大面積単結晶シリコン基板の製造方法 |
| JP3918708B2 (ja) * | 2002-10-08 | 2007-05-23 | セイコーエプソン株式会社 | 回路基板及びその製造方法、転写チップ、転写元基板、電気光学装置、電子機器 |
| JP4151420B2 (ja) * | 2003-01-23 | 2008-09-17 | セイコーエプソン株式会社 | デバイスの製造方法 |
| US6949451B2 (en) * | 2003-03-10 | 2005-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | SOI chip with recess-resistant buried insulator and method of manufacturing the same |
| JP3946683B2 (ja) * | 2003-09-25 | 2007-07-18 | 株式会社東芝 | アクティブマトリクス基板の製造方法 |
| US7229901B2 (en) * | 2004-12-16 | 2007-06-12 | Wisconsin Alumni Research Foundation | Fabrication of strained heterojunction structures |
| US7691730B2 (en) * | 2005-11-22 | 2010-04-06 | Corning Incorporated | Large area semiconductor on glass insulator |
-
2008
- 2008-06-19 US US12/142,454 patent/US7807520B2/en not_active Expired - Fee Related
- 2008-06-26 JP JP2008167487A patent/JP5500793B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7807520B2 (en) | 2010-10-05 |
| JP2009033139A (ja) | 2009-02-12 |
| US20090001387A1 (en) | 2009-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5500793B2 (ja) | 半導体装置の製造方法 | |
| US20240213276A1 (en) | Semiconductor device | |
| US12276891B2 (en) | Liquid crystal display device and electronic device | |
| US8431451B2 (en) | Display device and method for manufacturing the same | |
| JP6522189B2 (ja) | 半導体装置 | |
| JP5520437B2 (ja) | 表示装置 | |
| JP2009008890A (ja) | 表示装置及び電子機器 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110523 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110523 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130509 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130604 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130724 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140304 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140311 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5500793 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |