JP5484053B2 - 銅配線のバリア界面調整のための方法および装置 - Google Patents

銅配線のバリア界面調整のための方法および装置 Download PDF

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JP5484053B2
JP5484053B2 JP2009526620A JP2009526620A JP5484053B2 JP 5484053 B2 JP5484053 B2 JP 5484053B2 JP 2009526620 A JP2009526620 A JP 2009526620A JP 2009526620 A JP2009526620 A JP 2009526620A JP 5484053 B2 JP5484053 B2 JP 5484053B2
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layer
copper
integrated system
barrier layer
metal
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JP2010503204A (ja
JP2010503204A5 (enExample
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ボイド・ジョン
ドルディ・イエッディ
ユーン・ヒュングスック・アレキサンダー
レデカー・フリッツ・シー．
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Lam Research Corp
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Lam Research Corp
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    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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US11/639,050 US8916232B2 (en) 2006-08-30 2006-12-13 Method for barrier interface preparation of copper interconnect
US11/639,050 2006-12-13
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