JP5480168B2 - 電流劣化を保護する読取り基準手法 - Google Patents

電流劣化を保護する読取り基準手法 Download PDF

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Publication number
JP5480168B2
JP5480168B2 JP2010550709A JP2010550709A JP5480168B2 JP 5480168 B2 JP5480168 B2 JP 5480168B2 JP 2010550709 A JP2010550709 A JP 2010550709A JP 2010550709 A JP2010550709 A JP 2010550709A JP 5480168 B2 JP5480168 B2 JP 5480168B2
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JP
Japan
Prior art keywords
current
cell
cells
bit
reference cell
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Expired - Fee Related
Application number
JP2010550709A
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English (en)
Japanese (ja)
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JP2011514615A (ja
JP2011514615A5 (enExample
Inventor
ム、フーチェン
エイ． カバッシ、マルコ
ジェイ． スイズデク、ロナルド
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
JP2010550709A 2008-03-14 2009-01-26 電流劣化を保護する読取り基準手法 Expired - Fee Related JP5480168B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/048,683 US7742340B2 (en) 2008-03-14 2008-03-14 Read reference technique with current degradation protection
US12/048,683 2008-03-14
PCT/US2009/031945 WO2009114213A1 (en) 2008-03-14 2009-01-26 Read reference technique with current degradation protection

Publications (3)

Publication Number Publication Date
JP2011514615A JP2011514615A (ja) 2011-05-06
JP2011514615A5 JP2011514615A5 (enExample) 2012-03-15
JP5480168B2 true JP5480168B2 (ja) 2014-04-23

Family

ID=41062885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010550709A Expired - Fee Related JP5480168B2 (ja) 2008-03-14 2009-01-26 電流劣化を保護する読取り基準手法

Country Status (4)

Country Link
US (1) US7742340B2 (enExample)
EP (1) EP2266117A4 (enExample)
JP (1) JP5480168B2 (enExample)
WO (1) WO2009114213A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014068961A1 (ja) * 2012-10-30 2014-05-08 パナソニック株式会社 不揮発性半導体記憶装置
US9595340B2 (en) * 2015-01-20 2017-03-14 Taiwan Semiconductor Manufacturing Company Limited Nonvolatile memory device and method of setting a reference current in a nonvolatile memory device
US11082383B2 (en) 2018-03-13 2021-08-03 ROVl GUIDES, INC. Systems and methods for displaying a notification at an area on a display screen that is within a line of sight of a subset of audience members to whom the notification pertains
US11114176B1 (en) * 2020-03-06 2021-09-07 Qualcomm Incorporated Systems and methods to provide write termination for one time programmable memory cells

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69326329T2 (de) * 1993-06-28 2000-04-13 Stmicroelectronics S.R.L., Agrate Brianza Speicherzellen-Stromleseverfahren in Mikrosteuergerät
US6097632A (en) * 1997-04-18 2000-08-01 Micron Technology, Inc. Source regulation circuit for an erase operation of flash memory
JP2000268584A (ja) * 1999-03-15 2000-09-29 Nec Corp 不揮発性半導体記憶装置およびその製造方法
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
JP4212760B2 (ja) * 2000-06-02 2009-01-21 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
FR2820539B1 (fr) * 2001-02-02 2003-05-30 St Microelectronics Sa Procede et dispositif de rafraichissement de cellules de reference
EP1251523B1 (en) * 2001-04-19 2007-08-15 STMicroelectronics S.r.l. Method and circuit for timing dynamic reading of a memory cell with control of the integration time
US6813189B2 (en) * 2002-07-16 2004-11-02 Fujitsu Limited System for using a dynamic reference in a double-bit cell memory
JP2004062922A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp 不揮発性半導体記憶装置
US7180782B2 (en) * 2005-06-10 2007-02-20 Macronix International Co., Ltd. Read source line compensation in a non-volatile memory

Also Published As

Publication number Publication date
EP2266117A1 (en) 2010-12-29
JP2011514615A (ja) 2011-05-06
US20090231925A1 (en) 2009-09-17
WO2009114213A1 (en) 2009-09-17
EP2266117A4 (en) 2011-07-06
US7742340B2 (en) 2010-06-22

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