JP5466096B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5466096B2
JP5466096B2 JP2010140941A JP2010140941A JP5466096B2 JP 5466096 B2 JP5466096 B2 JP 5466096B2 JP 2010140941 A JP2010140941 A JP 2010140941A JP 2010140941 A JP2010140941 A JP 2010140941A JP 5466096 B2 JP5466096 B2 JP 5466096B2
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Japan
Prior art keywords
wiring layer
layer
insulating layer
forming
opening
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JP2010140941A
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Japanese (ja)
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JP2012004506A5 (enExample
JP2012004506A (ja
Inventor
孝治 山野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2010140941A priority Critical patent/JP5466096B2/ja
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Publication of JP2012004506A5 publication Critical patent/JP2012004506A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010140941A 2010-06-21 2010-06-21 半導体装置及びその製造方法 Active JP5466096B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010140941A JP5466096B2 (ja) 2010-06-21 2010-06-21 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010140941A JP5466096B2 (ja) 2010-06-21 2010-06-21 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2012004506A JP2012004506A (ja) 2012-01-05
JP2012004506A5 JP2012004506A5 (enExample) 2013-05-16
JP5466096B2 true JP5466096B2 (ja) 2014-04-09

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Family Applications (1)

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JP2010140941A Active JP5466096B2 (ja) 2010-06-21 2010-06-21 半導体装置及びその製造方法

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JP (1) JP5466096B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5846953B2 (ja) * 2012-02-15 2016-01-20 アルプス電気株式会社 入力装置及びその製造方法
US9082764B2 (en) * 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
JP2014187334A (ja) * 2013-03-25 2014-10-02 Disco Abrasive Syst Ltd ウエハレベルパッケージ構造およびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003101230A (ja) * 2001-09-21 2003-04-04 Fujitsu Ltd 多層プリント配線板の製造方法
JP2004055628A (ja) * 2002-07-17 2004-02-19 Dainippon Printing Co Ltd ウエハレベルの半導体装置及びその作製方法
JP4995551B2 (ja) * 2006-12-01 2012-08-08 ローム株式会社 半導体装置及び半導体装置の製造方法
JP4121542B1 (ja) * 2007-06-18 2008-07-23 新光電気工業株式会社 電子装置の製造方法
JP4953132B2 (ja) * 2007-09-13 2012-06-13 日本電気株式会社 半導体装置
JP2010021194A (ja) * 2008-07-08 2010-01-28 Toshiba Corp 積層型半導体装置、及び積層型半導体装置の製造方法
JP4787296B2 (ja) * 2008-07-18 2011-10-05 Ｔｄｋ株式会社 半導体内蔵モジュール及びその製造方法

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Publication number Publication date
JP2012004506A (ja) 2012-01-05

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