JP5465897B2 - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法 Download PDF

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Publication number
JP5465897B2
JP5465897B2 JP2009051668A JP2009051668A JP5465897B2 JP 5465897 B2 JP5465897 B2 JP 5465897B2 JP 2009051668 A JP2009051668 A JP 2009051668A JP 2009051668 A JP2009051668 A JP 2009051668A JP 5465897 B2 JP5465897 B2 JP 5465897B2
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JP
Japan
Prior art keywords
wafer
wiring
layer
film
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2009051668A
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English (en)
Japanese (ja)
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JP2010206058A5 (https=
JP2010206058A (ja
Inventor
誠 永野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009051668A priority Critical patent/JP5465897B2/ja
Priority to US12/716,928 priority patent/US8236681B2/en
Publication of JP2010206058A publication Critical patent/JP2010206058A/ja
Publication of JP2010206058A5 publication Critical patent/JP2010206058A5/ja
Application granted granted Critical
Publication of JP5465897B2 publication Critical patent/JP5465897B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2009051668A 2009-03-05 2009-03-05 半導体集積回路装置の製造方法 Expired - Fee Related JP5465897B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009051668A JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法
US12/716,928 US8236681B2 (en) 2009-03-05 2010-03-03 Manufacturing method of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009051668A JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010206058A JP2010206058A (ja) 2010-09-16
JP2010206058A5 JP2010206058A5 (https=) 2012-03-29
JP5465897B2 true JP5465897B2 (ja) 2014-04-09

Family

ID=42678638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009051668A Expired - Fee Related JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法

Country Status (2)

Country Link
US (1) US8236681B2 (https=)
JP (1) JP5465897B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2960700B1 (fr) * 2010-06-01 2012-05-18 Commissariat Energie Atomique Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias
US9887160B2 (en) * 2015-09-24 2018-02-06 International Business Machines Corporation Multiple pre-clean processes for interconnect fabrication
KR102616489B1 (ko) 2016-10-11 2023-12-20 삼성전자주식회사 반도체 장치 제조 방법
CN109148356A (zh) * 2017-06-15 2019-01-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US12087692B2 (en) * 2017-09-28 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Hardened interlayer dielectric layer
CN112233977A (zh) * 2020-10-15 2021-01-15 广州粤芯半导体技术有限公司 一种改善晶格损伤的方法
US11990430B2 (en) 2021-01-28 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structures of integrated circuit devices and method forming the same
CN114400234B (zh) * 2021-12-17 2025-02-25 武汉新芯集成电路股份有限公司 背照式影像传感器芯片及其制作方法
TWI879358B (zh) * 2023-12-29 2025-04-01 慧隆科技股份有限公司 先進半導體裝置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4207285B2 (ja) * 1999-02-10 2009-01-14 ソニー株式会社 半導体装置の製造方法
JP5165817B2 (ja) * 2000-03-31 2013-03-21 ラム リサーチ コーポレーション 静電チャック及びその製造方法
JP2002134489A (ja) * 2000-10-25 2002-05-10 Tokyo Electron Ltd 基板除電方法、気相堆積装置、半導体装置の製造方法
JP4493863B2 (ja) * 2001-01-25 2010-06-30 東京エレクトロン株式会社 プラズマ処理装置およびそのクリーニング方法および静電チャックの除電方法
JP2004014868A (ja) * 2002-06-07 2004-01-15 Tokyo Electron Ltd 静電チャック及び処理装置
JP2004247675A (ja) * 2003-02-17 2004-09-02 Renesas Technology Corp 半導体装置の製造方法
JP2005116801A (ja) * 2003-10-08 2005-04-28 Toshiba Corp 半導体装置の製造方法
US7094705B2 (en) * 2004-01-20 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-step plasma treatment method to improve CU interconnect electrical performance
JP2006165189A (ja) * 2004-12-06 2006-06-22 Nec Electronics Corp 半導体装置の製造方法
JP2007115839A (ja) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及びプラズマ処理装置
JP2007258636A (ja) * 2006-03-27 2007-10-04 Matsushita Electric Ind Co Ltd ドライエッチング方法およびその装置
JP5233097B2 (ja) * 2006-08-15 2013-07-10 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
US7700479B2 (en) * 2006-11-06 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cleaning processes in the formation of integrated circuit interconnect structures
US8035277B2 (en) * 2007-08-14 2011-10-11 Avago Technologies Wireless Ip (Singapore) Pte.Ltd. Method for forming a multi-layer electrode underlying a piezoelectric layer and related structure

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Publication number Publication date
JP2010206058A (ja) 2010-09-16
US20100227470A1 (en) 2010-09-09
US8236681B2 (en) 2012-08-07

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