JP5420409B2 - 銅とバリア層との間の接着性を向上させるための自己組織化原子層 - Google Patents

銅とバリア層との間の接着性を向上させるための自己組織化原子層 Download PDF

Info

Publication number
JP5420409B2
JP5420409B2 JP2009526618A JP2009526618A JP5420409B2 JP 5420409 B2 JP5420409 B2 JP 5420409B2 JP 2009526618 A JP2009526618 A JP 2009526618A JP 2009526618 A JP2009526618 A JP 2009526618A JP 5420409 B2 JP5420409 B2 JP 5420409B2
Authority
JP
Japan
Prior art keywords
copper
layer
barrier layer
integrated system
metal barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009526618A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010503203A (ja
JP2010503203A5 (enExample
Inventor
ナラ・プラベーン
ティエ・ウィリアム
ボイド・ジョン
アルナジリ・ティルチラーパリ
ユーン・ヒュングスック・アレキサンダー
レデカー・フリッツ・シー.
ドルディ・イエッディ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of JP2010503203A publication Critical patent/JP2010503203A/ja
Publication of JP2010503203A5 publication Critical patent/JP2010503203A5/ja
Application granted granted Critical
Publication of JP5420409B2 publication Critical patent/JP5420409B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2009526618A 2006-08-30 2007-08-15 銅とバリア層との間の接着性を向上させるための自己組織化原子層 Expired - Fee Related JP5420409B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition
US11/514,038 2006-08-30
US11/639,012 US20090304914A1 (en) 2006-08-30 2006-12-13 Self assembled monolayer for improving adhesion between copper and barrier layer
US11/639,012 2006-12-13
PCT/US2007/018212 WO2008027205A2 (en) 2006-08-30 2007-08-15 Self assembled monolayer for improving adhesion between copper and barrier layer

Publications (3)

Publication Number Publication Date
JP2010503203A JP2010503203A (ja) 2010-01-28
JP2010503203A5 JP2010503203A5 (enExample) 2012-04-26
JP5420409B2 true JP5420409B2 (ja) 2014-02-19

Family

ID=39136454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009526618A Expired - Fee Related JP5420409B2 (ja) 2006-08-30 2007-08-15 銅とバリア層との間の接着性を向上させるための自己組織化原子層

Country Status (7)

Country Link
US (1) US20090304914A1 (enExample)
JP (1) JP5420409B2 (enExample)
KR (1) KR101423349B1 (enExample)
MY (1) MY162187A (enExample)
SG (1) SG174105A1 (enExample)
TW (2) TWI453822B (enExample)
WO (1) WO2008027205A2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916232B2 (en) * 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect
JP4755573B2 (ja) * 2006-11-30 2011-08-24 東京応化工業株式会社 処理装置および処理方法、ならびに表面処理治具
KR100841170B1 (ko) * 2007-04-26 2008-06-24 삼성전자주식회사 저저항 금속 배선 형성방법, 금속 배선 구조 및 이를이용하는 표시장치
JP4971078B2 (ja) * 2007-08-30 2012-07-11 東京応化工業株式会社 表面処理装置
KR101096031B1 (ko) 2009-03-31 2011-12-19 한양대학교 산학협력단 자기조립단분자막 형성방법과 이를 이용한 반도체 소자의 구리배선 및 그의 형성방법
US8415252B2 (en) * 2010-01-07 2013-04-09 International Business Machines Corporation Selective copper encapsulation layer deposition
US9252049B2 (en) * 2013-03-06 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming interconnect structure that avoids via recess
US8962473B2 (en) 2013-03-15 2015-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming hybrid diffusion barrier layer and semiconductor device thereof
KR102264160B1 (ko) 2014-12-03 2021-06-11 삼성전자주식회사 비아 구조체 및 배선 구조체를 갖는 반도체 소자 제조 방법
KR101816028B1 (ko) * 2015-01-23 2018-01-08 코닝정밀소재 주식회사 금속 접합기판
US9799593B1 (en) * 2016-04-01 2017-10-24 Intel Corporation Semiconductor package substrate having an interfacial layer
US10358715B2 (en) * 2016-06-03 2019-07-23 Applied Materials, Inc. Integrated cluster tool for selective area deposition
KR101819825B1 (ko) * 2016-06-13 2018-01-18 아주대학교산학협력단 플렉시블 전극 제조방법
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US9875958B1 (en) 2016-11-09 2018-01-23 International Business Machines Corporation Trace/via hybrid structure and method of manufacture
US10163695B1 (en) * 2017-06-27 2018-12-25 Lam Research Corporation Self-forming barrier process
US10678135B2 (en) 2017-12-20 2020-06-09 International Business Machines Corporation Surface treatment of titanium containing hardmasks
JP2019192892A (ja) 2018-04-18 2019-10-31 東京エレクトロン株式会社 処理システムおよび処理方法
US10914008B2 (en) * 2018-09-27 2021-02-09 Imec Vzw Method and solution for forming interconnects
KR102792797B1 (ko) 2018-11-19 2025-04-07 램 리써치 코포레이션 텅스텐을 위한 몰리브덴 템플릿들
US11076492B2 (en) * 2018-12-17 2021-07-27 Averatek Corporation Three dimensional circuit formation
JP7581213B2 (ja) 2019-01-28 2024-11-12 ラム リサーチ コーポレーション 金属膜の蒸着
WO2021046058A1 (en) 2019-09-03 2021-03-11 Lam Research Corporation Molybdenum deposition
JP2022551965A (ja) 2019-10-15 2022-12-14 ラム リサーチ コーポレーション モリブデン充填
US11929327B2 (en) 2020-01-29 2024-03-12 Taiwan Semiconductor Manufacturing Co., Inc. Liner-free conductive structures with anchor points
DE102020119831B4 (de) 2020-01-29 2024-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren und Struktur
KR20230104071A (ko) * 2020-11-19 2023-07-07 램 리써치 코포레이션 저 저항률 (low resistivity) 콘택트들 및 상호 접속부들
WO2024243143A1 (en) * 2023-05-23 2024-11-28 Lam Research Corporation Inhibited atomic layer deposition in trench features

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949671A (en) * 1985-10-24 1990-08-21 Texas Instruments Incorporated Processing apparatus and method
JP3911643B2 (ja) * 1995-07-05 2007-05-09 富士通株式会社 埋め込み導電層の形成方法
US6042623A (en) * 1998-01-12 2000-03-28 Tokyo Electron Limited Two-wafer loadlock wafer processing apparatus and loading and unloading method therefor
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
JP3974284B2 (ja) * 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
US6734559B1 (en) * 1999-09-17 2004-05-11 Advanced Micro Devices, Inc. Self-aligned semiconductor interconnect barrier and manufacturing method therefor
US6423636B1 (en) * 1999-11-19 2002-07-23 Applied Materials, Inc. Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer
AU2001255656A1 (en) * 2000-04-25 2001-11-07 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
US20040040504A1 (en) * 2002-08-01 2004-03-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing apparatus
US20050274621A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
US7309658B2 (en) * 2004-11-22 2007-12-18 Intermolecular, Inc. Molecular self-assembly in substrate processing
KR100613388B1 (ko) * 2004-12-23 2006-08-17 동부일렉트로닉스 주식회사 다마신법을 이용한 구리 배선층을 갖는 반도체 소자 및 그형성 방법
KR100718804B1 (ko) * 2005-11-15 2007-05-16 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US8916232B2 (en) * 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect

Also Published As

Publication number Publication date
KR101423349B1 (ko) 2014-07-24
TWI453822B (zh) 2014-09-21
WO2008027205A2 (en) 2008-03-06
MY162187A (en) 2017-05-31
TWI462178B (zh) 2014-11-21
JP2010503203A (ja) 2010-01-28
TW200834726A (en) 2008-08-16
KR20090045302A (ko) 2009-05-07
SG174105A1 (en) 2011-09-29
US20090304914A1 (en) 2009-12-10
WO2008027205A3 (en) 2008-04-24
TW201246376A (en) 2012-11-16

Similar Documents

Publication Publication Date Title
JP5420409B2 (ja) 銅とバリア層との間の接着性を向上させるための自己組織化原子層
JP5484053B2 (ja) 銅配線のバリア界面調整のための方法および装置
CN101548030A (zh) 用于增强铜和阻挡层之间粘结的自组装单层
US8039966B2 (en) Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects
JP5489717B2 (ja) 金属堆積のために基板表面を調整する方法および統合システム
CN101558482B (zh) 一种用于在衬底上产生盖层的方法和一种器件
JP2010503203A5 (enExample)
KR101506352B1 (ko) 금속 증착을 위해 기판 표면을 가공하는 프로세스 및 통합 시스템
US7867897B2 (en) Low leakage metal-containing cap process using oxidation
KR100403671B1 (ko) 확산 장벽층 및 이를 포함한 반도체 디바이스
US10256185B2 (en) Nitridization for semiconductor structures
CN100481384C (zh) 导体-电介质结构及其制造方法
KR101487564B1 (ko) 구리 상호접속부의 배리어 계면 제작 방법 및 장치
JP2012074608A (ja) 配線形成方法
KR100538094B1 (ko) 반도체 장치의 배선 형성 방법, 반도체 장치의 금속층형성 방법 및 장치
US6784093B1 (en) Copper surface passivation during semiconductor manufacturing
JP2006024667A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100806

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120309

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130603

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130625

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130924

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131022

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131120

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees