JP5415580B2 - Multilayer printed wiring board - Google Patents

Description

  The present invention relates to a multilayer printed wiring board for mounting electronic components such as capacitors and ICs on a surface layer, and more specifically, a multilayer that does not cause dropping of electronic components due to a drop, deterioration of electrical connectivity, and reliability. The present invention relates to a printed wiring board.

  In recent portable electronic devices such as mobile phones and digital cameras, the mounting parts are reduced in size in response to the demand for higher functionality and higher density, and the wiring density (wiring width line / Corresponding to increasing the density of mounted components, such as reducing the wiring space) and reducing the solder pads.

Specifically, components mounted on such a substrate include IC chips, capacitors, passive components such as resistors and inductors, liquid crystal devices, display devices for performing digital display, operation systems such as keypads and switches, etc. There is an external terminal such as a device or USB or earphone.
Conductive pads corresponding to these mounting components are mixedly disposed on the mounting substrate, and the mounting components are mounted on these conductive pads via solder.

  As one of the multilayer circuit boards on which such electronic components are mounted, a via hole opening is formed by laser irradiation on an insulating hard substrate having a conductor circuit on one side or both sides, and a metal is formed in the opening. By creating a via hole by filling a paste or plating to produce an interlayer connected circuit board, preparing two or more layers of this circuit board, and laminating these circuit boards sequentially or collectively. There is a type manufactured (refer to Japanese Patent Laid-Open No. 10-13028).

In such a multilayer circuit board, via holes or via hole lands on one adjacent circuit board are connected to conductor circuits or lands on the other circuit board, so that the two-layer circuit boards are electrically connected to each other. Connected to.
In other areas that do not contribute to the electrical connection of the circuit boards, the circuit boards are bonded to each other by an adhesive layer made of a thermosetting resin, a prepreg, or the like, so that multilayering is achieved.

  Then, a solder resist layer for protecting the conductor circuit is formed on the surface layer of the multilayer circuit board or the general printed wiring board as described above, and an opening is formed in a part of the solder resist layer and exposed from the opening. In general, a corrosion-resistant layer such as gold or nickel-gold is formed on the surface of the conductor circuit, and a solder body such as a solder bump is formed on the surface of the conductor circuit on which such a corrosion-resistant layer is formed. Electronic components such as capacitors and ICs are mounted via these solder bodies.

  By the way, in the multilayer circuit board that realizes high-density mounting of electronic components used in portable electronic devices such as mobile phones and digital cameras as described above, higher reliability has recently been demanded. It is.

  That is, even if a substrate or a product (showing a state where a substrate on which all electronic components including a liquid crystal device are mounted is housed in a housing) is dropped from a certain height a predetermined number of times, the substrate There is a demand for further improvement in the reliability of the drop test so that the function of the electronic device and the function of the electronic device are not deteriorated and the electronic component is not detached from the substrate.

Further, there is a demand for further reducing the thickness of the substrate itself used in the portable electronic device. However, the thickness of the insulating layer of each layer constituting the mounting substrate is 100 μm or less, and the mounting substrate itself even if it is multilayered. As a whole, the thickness is required to be thinner than before. For this reason, the rigidity of the mounting substrate itself tends to be lowered.
In addition, since the rigidity of the substrate itself is reduced, the resistance to warpage and the like is likely to be reduced, and as a result, the flatness of the substrate is likely to be impaired, and a problem occurs in a subsequent process (for example, a component mounting process). It becomes easy.

  Further, since the insulating layer is thin, the mounting substrate itself is also soft and easily warped, so that it is easily affected by the stress generated by an external impact or the like. For example, although it has been studied to increase the rigidity by increasing the thickness of the insulating substrate, which is the center when stacking, to 600 μm or more, it may not fit in a case such as a portable electronic device. There is a dilemma that the technique of increasing the thickness of the film cannot be used.

  Therefore, the conventional multilayer circuit board for mounting as described above cannot increase the rigidity by increasing the thickness of the insulating substrate that is the center of the stack, thus improving the function and start-up of the board over the drop test in the reliability test. It was difficult to let In particular, it has been difficult to improve the reliability and the drop resistance against the drop test in the mounting substrate in which the mounting density of components and the like is increased as described above. In other words, since sufficient reliability cannot be obtained in the reliability test, the electrical connectivity and reliability cannot be further improved.

  Therefore, the present invention proposes a multilayer printed wiring board capable of improving reliability with respect to a reliability test, ensuring more electrical connectivity and functionality, and particularly improving reliability with respect to a drop test. .

  As a result of intensive research for realizing the above object, the present inventors pay attention to the shape and laminated form of via holes that electrically connect conductor circuits in a multilayer circuit board. A first via group formed in one insulating layer of the two insulating layers located at the other side and the other insulating layer disposed inwardly from the insulating layer, and two insulations located on the outermost side Each of the vias stacked in the opposing positional relationship, divided into the other insulating layer of the layers and the second via group formed in the other insulating layer disposed inward from the insulating layer When the via holes belonging to the group are formed in a shape that tapers the surface of the insulating substrate on which they are provided or the surface of the conductor circuit provided on the insulating substrate, the insulating substrate constituting the mounting substrate is Even if it is thin, Implementation decrease in rigidity of the substrate, and finding that there is not caused warping of occurrence, based on such findings, the present invention has been completed for the following contents and the summary and construction.

That is, the present invention
(1) In a multilayer printed wiring board in which insulating layers and conductor layers are alternately laminated, and the conductor layers are electrically connected via via holes provided in the insulating layer,
A first via group consisting of via holes provided in one of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer;
A second via group consisting of via holes provided in the other insulating layer of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer. And
Said first respectively via group and second via groups, has a tapered shape that each via hole is reduced in diameter toward the inside in the thickness direction of the insulating layer, substantially identical straight to each other in the thickness direction of the insulating layer Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating layer,
The first via group and the second via group are shifted in a direction substantially perpendicular to the thickness direction of the insulating layer, and are stacked so as to partially overlap each other in the thickness direction of the insulating layer. It is the multilayer printed wiring board characterized by the above-mentioned.

The present invention also provides:
(2) At least one layer of another insulating substrate having a conductor circuit is laminated on both surfaces of one insulating substrate having a conductor circuit, and the conductor circuit provided on the one insulating substrate and the conductor provided on the other insulating substrate. In a multilayer printed wiring board in which a circuit is electrically connected through a via hole provided in each insulating substrate,
A first via group comprising a via hole provided in one of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate;
A second via group comprising via holes provided in the other of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate; And
Each of the first via groups and second via groups has a tapered shape in which each via hole is reduced in diameter toward the inside in the thickness direction of the insulating substrate, substantially the same straight one another in the thickness direction of the insulating substrate Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating substrate,
The first via group and the second via group are shifted in a direction substantially orthogonal to the thickness direction of the insulating substrate and stacked in a positional relationship that partially overlaps with each other in the thickness direction of the insulating substrate. It is the multilayer printed wiring board characterized by the above-mentioned.

The present invention also provides:
(3) At least one outer insulating substrate having a conductor circuit is laminated on both surfaces of an inner insulating substrate having a conductor circuit, and the conductor circuit provided on the inner insulating substrate and the conductor circuit provided on the outer insulating substrate. In a multilayer printed wiring board that is electrically connected through via holes provided in each insulating substrate,
A first via group comprising a via hole provided in one of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate;
A second via group comprising via holes provided in the other of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate; And
Each of the first via groups and second via groups has a tapered shape in which each via hole is reduced in diameter toward the inside in the thickness direction of the insulating substrate, substantially the same straight one another in the thickness direction of the insulating substrate Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating substrate,
The first via group and the second via group are shifted in a direction substantially orthogonal to the thickness direction of the insulating substrate and stacked in a positional relationship that partially overlaps with each other in the thickness direction of the insulating substrate. It is the multilayer printed wiring board characterized by the above-mentioned.

Further, in the present invention,
(4) The thickness of the insulating layer or the insulating substrate is preferably 100 μm or less, and can be 50 μm or less.

Further, in the present invention, the first via group and the second via group are shifted in a direction substantially orthogonal to the thickness direction of the insulating substrate, and one in the thickness direction of the insulating substrate. The multi-layer stacked via structure is formed by stacking in a positional relationship such that they overlap each other and face each other .

Moreover, each via-hole forming the first via group and the second via groups each are stacked so that positions are aligned on substantially the same straight line with one another.

A via hole constituting one of the first via group and the second via group is located at two opposing vertices of the virtual square lattice on the insulating substrate, and the other via group Can be configured so as to be located at the other two vertices of the virtual square lattice on the insulating substrate facing each other.

A via hole constituting one of the first via group and the second via group is located at each vertex of a virtual square lattice or a triangular lattice on the insulating substrate, and the other via group. Can be configured to be located at the center of a virtual square lattice or a triangular lattice on the insulating substrate.

In addition, the via holes constituting one of the first via group and the second via group are concentrated in a predetermined region of the insulating substrate, and the via holes constituting the other via group are: The insulating substrate may be disposed in a peripheral region surrounding the predetermined region.

Each via hole has a taper of 60 to 90 degrees at an inner angle with respect to the surface of the insulating layer or insulating substrate on which the via hole is formed or to the surface of the conductor circuit provided on the surface. It can be formed in such a tapered shape.
Each via hole is formed by filling plating in an opening formed in an insulating layer or an insulating substrate .

  Furthermore, the via holes constituting the first via group and the second via group can form a multistage stacked via structure.

According to the present invention, a first via groups provided in the insulating layer or insulating substrate is laminated to the insulating layer or insulating substrate formed of a laminated center and one surface of the insulating layer or an insulating substrate becomes laminated center The multi-layer stacked via structure in which the insulating layer stacked on the other surface side or the second via group provided on the insulating substrate is arranged opposite to each other is configured, and the via holes belonging to each via group are directed in the thickness direction. The tapered insulating layer is formed so as to taper with respect to the surface of the insulating layer or the insulating substrate or the surface of the conductor circuit provided on the surface of the insulating layer or insulating substrate. or even thickness of the insulating substrate is a following thin layer 100 [mu] m, the external stress generated by the external force (refer to like impact force generated when dropped), the insulating layer or insulating substrate It is possible to suppress the warp.

  As a result, since external stress can be suppressed, it is possible to obtain an effect that it is possible to suppress the occurrence of cracks and disconnection of the conductor circuit and reduce the reliability and drop resistance of the mounting substrate.

That is, when the insulating layer or the insulating substrate warps outside due to external stress, the multistage stack via fits into the insulating layer or the insulating substrate so that the insulating resin and the conductor layer forming the multistage stack via Is difficult to peel off. As a result, it is possible to reduce a decrease in reliability and drop resistance of the mounting substrate.

Further, when the insulating layer or the insulating substrate warps inward due to external stress, the multistage stacked via serves as a pile, and the warping of the insulating layer or the insulating substrate can be suppressed. For this reason, external stress transmitted to the insulating layer or the insulating substrate can be reduced, and as a result, a reduction in reliability and drop resistance of the mounting substrate can be reduced.
Further, in order to multistage stacked via is formed in the insulating layer or insulating substrate, even for the warpage of the insulating layer or insulating substrate due to internal stress, it will play a role of pile, the insulating layer or insulating substrate Can be made difficult to warp. Therefore, since the flatness of the substrate is not impaired, even if a reliability test such as a heat cycle condition is performed, cracks or the like occur early in the conductor circuit (including via holes), the insulating layer, or the insulating substrate. And the reliability of the mounting board is not lowered.

  In particular, when the insulating layer or the insulating substrate has a thickness of 100 μm or less and a conductor circuit is provided on such an insulating layer or insulating substrate, and the mounting substrate is formed by multilayering them, the warping of the mounting substrate can be suppressed. It is useful in.

  Furthermore, the insulating layer or the insulating substrate has a thickness of 50 μm or less, and is useful when a conductive circuit is provided in such an insulating layer and the mounting substrate is formed by multilayering them. It is estimated that the reliability and drop resistance of the mounting substrate can be ensured.

The first with vias and the second via groups are shifted in a direction substantially perpendicular to the thickness direction of the mutually insulating layer or an insulating substrate, from one another insulating layer or the thickness direction of the insulating substrate forming the multistage stacked vias By being formed at a position that overlaps with a part of the insulating layer or the insulating substrate , an effect can be exerted against warping in both the outer direction and the inner direction of the insulating layer or the insulating substrate . That is, when the insulating layer or the insulating substrate warps due to external stress, the resistance to external stress does not decrease due to the presence of the multistage stacked via against the warping in the outer direction and the inner direction. As a result, it is possible to reduce a decrease in reliability and drop resistance of the mounting substrate.

The first with vias and the second via groups are shifted in a direction substantially perpendicular to the thickness direction of the mutually insulating layer or an insulating substrate, from one another insulating layer or the thickness direction of the insulating substrate forming the multistage stacked vias in by being formed at a position opposed overlap part, in such regions the rigidity of the insulating layer or insulating substrate itself can be enhanced. Therefore, the warpage of the mounting board itself can be reduced, and the flatness of the mounting board is maintained in the post-process (for example, solder resist forming process, solder layer forming process, mounting process of electronic components, etc.) There will be no disadvantages such as dropping parts. As a result, it is possible to reduce the significant decrease in electrical connectivity and reliability of the mounting board.

FIG. 1 is a schematic view for explaining a tapered shape of a via hole in the multilayer printed wiring board of the present invention.
FIG. 2A is a schematic diagram showing one reference form of a multistage stacked via in the multilayer printed wiring board of the present invention, and FIG. 2B is an SEM photograph showing a cross section of the substrate having the multistage stacked via.
3A is a schematic diagram showing another reference example of a multistage stacked via, FIG. 3B is an SEM photograph showing a cross section of the substrate, FIG. 3C is a schematic diagram showing still another reference example of the multistage stacked via, and FIG. 3D. These are the SEM photographs which show the cross section of the board | substrate.
FIG. 4 is a schematic view showing a basic form of a multistage stacked via in the multilayer printed wiring board of the present invention.
5A to 5C are schematic views showing examples of planar arrangement patterns of via holes constituting a multistage stacked via.
FIG. 6 is a schematic diagram showing another example (triangular lattice arrangement) of planar arrangement patterns of via holes constituting a multistage stacked via.
FIG. 7 is a schematic view showing still another example (linear arrangement) of a planar arrangement pattern of via holes constituting a multistage stacked via.
8A to 8B are schematic views showing still another example (concentrated arrangement, distributed arrangement) of planar arrangement patterns of via holes constituting a multistage stacked via.
9A to 9E are diagrams showing a part of a process for manufacturing a multilayer printed wiring board according to Reference Example 1 of the present invention.
10A to 10E are diagrams illustrating a part of a process for manufacturing a multilayer printed wiring board according to Reference Example 1 of the present invention.
FIG. 11 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board according to Reference Example 1 of the present invention.
12A to 12B are diagrams showing a part of a process for manufacturing a multilayer printed wiring board according to Reference Example 1 of the present invention.

Multilayer printed wiring board according to an embodiment of the present invention, via holes, the two of the outermost insulating layer or an insulating substrate for electrically connecting the conductor layers to each other which are laminated with an insulating layer or an insulating substrate one of the insulating layer or the first via group consisting of a via hole provided in the insulating layer or an insulating substrate at least one layer of an insulating substrate and which is laminated on the inside, the two of the outermost insulating layer of the Alternatively, the second insulating layer or the insulating substrate of the insulating substrate and at least one insulating layer stacked on the inner side of the insulating substrate or a second via group formed in the insulating substrate and a via hole provided in the insulating substrate , via holes constituting the via group and second via groups is shaped to diameter toward the thickness direction of the insulating layer or an insulating substrate, One, the thickness of the insulating layer or insulating substrate is a multilayer printed wiring board, characterized in that at 100μm or less.

That is, in a multilayer printed wiring board as a laminated body in which conductor layers and insulating layers or insulating substrates are alternately stacked, one insulating layer or insulating substrate of two outermost insulating layers or insulating substrates and from the via holes formed in the insulating layer or an insulating substrate at least one layer which is laminated on the inner side (the first via group) therefrom, the other of the insulating layers of the two insulating layers or insulating substrate to the outermost Alternatively, the insulating substrate and at least one insulating layer stacked on the inner side thereof or a via hole (second via group) provided in the insulating substrate are in a direction substantially orthogonal to the thickness direction of the insulating layer or the insulating substrate. while being shifted, is formed at a position opposed overlap part constitutes a multistage stacked via in the thickness direction of the mutually insulating layer or an insulating substrate Via holes constituting the multistage stacked via is formed in a shape such as a tapered with respect to the surface of the conductor circuit provided on a surface or a surface of the insulating layer or insulating substrate, and the insulating layers or insulating substrate The multilayer printed wiring board is characterized by having a thickness of 100 μm or less.

  Examples of the insulating layer or the insulating substrate used in the present invention include a glass cloth epoxy resin base material, a phenol resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid non-woven fabric-epoxy resin base. Examples thereof include a hard laminated substrate selected from a material, an aramid nonwoven fabric-polyimide resin substrate, and the like. The thickness of the substrate made of such an insulating resin is desirably 100 μm or less. Further, the thickness of the substrate made of an insulating resin may be 50 μm or less.

A circuit board in which a conductor circuit is formed on one or both sides of such an insulating layer or an insulating substrate is used as the center of lamination, and the insulating layer or insulating substrate and the conductor layer are alternately laminated on the surface of the circuit substrate to achieve multilayering. A printed wiring board (mounting board) is obtained. Moreover, by making the thickness of all the insulating layers or insulating substrates in such a mounting substrate 100 μm or less, the thickness of the multilayer mounting substrate itself can be reduced.

In the present invention, both the conductor circuit provided in the insulating layer or the insulating substrate and the via holes (multi-stage stacked vias) respectively constituting the first and second via groups may be formed using a plating process. desirable. The reason for this is that the connection portions between the via holes that constitute the first via group or the second via group and the conductor circuits that are in contact with the upper and lower surfaces of the via holes, respectively, are formed from the same plating treatment plating film. When formed, peeling does not easily occur, and even when external stress is applied from the side surface, no deviation occurs, so that cracks and the like are hardly generated.

  The plating film used for forming the via hole is formed by electrolytic plating or electroless plating, and the metal used may be a single metal such as copper, nickel, iron, cobalt, etc., and these metals are mainly used. An alloy may be used.

  As shown in FIG. 1, the multistage stacked via in the present invention has a shape that decreases in diameter as it goes in the thickness direction of the insulating layer in which the via is formed, or the surface of the insulating substrate or the conductor circuit provided on the surface. It is formed into a shape that is tapered with respect to the surface, or a shape that has a taper that becomes wider from the inside to the outside of the laminated insulating substrate.

  For example, typically, the upper surface is preferably formed in a substantially truncated cone shape having a larger area than the bottom surface, and the internal angle of the taper in the cross-sectional shape (almost trapezoidal shape) in the thickness direction of the insulating substrate is in the range of 60 to 90 degrees. It is desirable to be within.

  The reason is that when the taper angle is 90 degrees or more, the anchor effect in the multistage stacked via may be offset. In other words, the multi-stage stack via when the substrate subjected to external stress warps outward may be difficult to fit to the insulating layer or the insulating substrate, causing peeling of the insulating resin and the conductor layer. As a result, the reliability and drop resistance of the insulating substrate may be reduced. On the other hand, if the angle is less than 60 degrees, the warpage suppression in the multistage stacked via may be lowered. That is, the role as a pile when the substrate subjected to external stress warps inward is reduced, that is, the warpage cannot be suppressed. For this reason, the reliability and drop resistance of the insulating substrate may be reduced.

  The via diameter on the bottom surface side (hereinafter referred to as “via bottom diameter”) in the multistage stacked via may be at least 10 μm in diameter. The reason is that via formation is performed by plating, and the formation of the plating film requires a via bottom diameter of at least 10 μm. Thereby, an electrical connection can be made between the upper conductor layer (upper conductor circuit and via) and the lower conductor circuit.

In the multistage stacked via according to the present invention, in each of the first via group and the second via group, the bottom surface of the outer via hole (upper via hole) and the inner via hole (lower via hole) The bottom surface is formed so as to overlap at the same position . That is, as shown in FIGS. 2A to 2B and FIG. 4 , in the plurality of via holes that respectively constitute the first via group or the second via group, the via holes are formed so as to be on substantially the same straight line .

In addition, if the bottom surface of the upper via hole and the bottom surface of the lower via hole overlap even in a part of them, the function of providing a tapered shape that makes it difficult to reduce reliability and drop resistance can be achieved. Therefore, in the reference example of the present invention, in the plurality of via holes that respectively constitute the first via group or the second via group, the via holes are shifted to positions that are substantially orthogonal to the thickness direction of the insulating layer. In addition, the via holes can be stacked at positions where the bottom surfaces of the via holes overlap at least partially in the thickness direction of the insulating substrate.

For example, in the reference example of the present invention, as shown in FIGS. 3A to 3B, the plurality of via holes respectively constituting the first via group or the second via group are shifted from each other by about ½ of the via hole diameter. Can be laminated. Also, as shown in FIGS. 3C to 3D, a plurality of via holes that respectively constitute the first via group or the second via group can be stacked at positions shifted from each other by substantially the via hole diameter.
Such a function by providing a tapered shape can sufficiently exhibit the effect even when used as a normal printed wiring board.

The first via group and second via groups constituting the multistage stacked via in the present invention is formed by laminating provided with at least two or more layers of the insulating substrate, via holes provided in their insulating substrate The That is, the first via group or the second via group may be configured by stacking three, four, or more via holes.

Each stacked via, that is, the first via group and the second via group may have the same number of layers (for example, first via group: three layers, second via group: three layers). However, the number of stacked layers may be different (for example, first via group: two layers, second via group: three layers). The first via group and the second via group constituting the multistage stacked via in the present invention are shifted in a direction substantially perpendicular to the thickness direction of the insulating layer or the insulating substrate, and the thickness of the insulating layer or the insulating substrate. By being formed in a positional relationship that partially overlaps in the direction and faces each other, it is possible to achieve an effect that the electrical connectivity and reliability of the mounting substrate are not significantly reduced.

  The multistage stacked via in the present invention may be a conductor layer having electrical connection, but may also be a conductor layer without electrical connection, a so-called dummy conductor layer. When a multistage stacked via is formed from a dummy conductor layer, a conductor layer other than a dummy (a conductor layer existing around the dummy conductor layer or a conductor layer having an electrical connection such as an opposing multistage stack via) ) And the drop resistance are not lowered, and the warpage of the mounting board can be reduced, so that the flatness of the mounting board can be ensured.

In addition, the first via group and the second via group constituting the multistage stacked via in the reference example of the present invention are within the region where the conductor circuit of each insulating substrate is formed, as shown in FIGS. It is desirable that they are arranged at substantially the same position (on the same straight line), or arranged in a state where they are shifted relative to each other (distributed state) as shown in FIGS. As shown in FIG. 4, the first via group and the second via group constituting the multistage stacked via in the embodiment of the present invention are arranged in a state in which the positional relationship is shifted from each other (distributed state). .
For example, the resistance to warping due to external stress can be improved by uniformly distributing the first via group and the second via group over the entire area of the insulating substrate.

In addition, the first via group and / or the second via group are arranged centrally in the central part of the insulating substrate, which is most susceptible to the influence of warping due to external stress, thereby improving the resistance to warping due to external stress. Can be made.
Also, the first via group and / or the second via group can be arranged in a peripheral part mainly surrounding the central part of the insulating substrate without being arranged in the central part of the insulating substrate. With such an arrangement, the resistance against warping of the substrate can be improved, the flatness of the mounting substrate can be ensured, and the resistance against external stress can be provided.

Further, mainly in the central portion of the insulating substrate , the first via group and the second via group are linearly opposed to each other as in the reference example, and the first via is disposed in the peripheral portion as in the embodiment. The group and the second via group can be shifted in a direction substantially perpendicular to the thickness direction of the insulating layer or the insulating substrate, and can be arranged in a state where they partially overlap each other in the thickness direction of the insulating layer or the insulating substrate. .

  As the planar arrangement pattern of the multistage stack via, various patterns such as a square lattice (see FIGS. 5A to 5C), a triangular lattice (see FIG. 6), a straight line (see FIG. 7), and the like are available. Pattern.

Wherein when the square lattice arrangement, for example, or by placing a first via group and the second via groups with regularity in the virtual square matrix shape as shown in FIG. 5A, FIG. 5B A first via group is arranged in a virtual matrix shape as shown, and a second via group facing the middle portion of the matrix is arranged, or a staggered shape as shown in FIG. For example, the first via group and the second via group may be arranged with regularity in a virtual matrix shape.

Further, in the case of the triangular lattice arrangement, for example, the first via group is arranged in a virtual triangle shape as shown in FIG. For example, a via group may be arranged.
Further, in the case of the straight line arrangement, for example, at least two first via groups are arranged in a virtual straight line as shown in FIG. For example, two via groups may be arranged.

  In addition, a multistage stacked via can be configured by a pattern in which two or more of these patterns are combined.

Further, as another arrangement pattern of the multistage stacked via in the present invention, for example, the second via group can be arranged to face the region where the first via group is not formed. For example, the first via group is arranged in a matrix in a plan view, and the second via group is shifted from the first via group in a direction substantially perpendicular to the thickness direction of the insulating layer or the insulating substrate . Arrange in a matrix form in a region where the via group is not formed, or arrange the first via group mainly in the center of the substrate and move the second via group from the first via group in the thickness direction of the insulating layer or the insulating substrate. Examples include a pattern that is shifted in a substantially orthogonal direction and arranged on the periphery of the substrate (see FIG. 8A).

  In FIGS. 5 to 8, the first via group is indicated by a circle and the second via group is indicated by an x mark. However, the arrangement may be opposite to such an arrangement. The size of the via diameter may be the same for the first via group and the second via group, or may be different diameters.

Hereinafter, an example of a method for producing a multilayer printed wiring board according to the present invention will be specifically described.
(1) In manufacturing a multilayer printed wiring board according to the present invention, a circuit board as a basic unit constituting the multilayer printed wiring board should be a starting material that has a copper foil attached to one or both sides of an insulating base material. Can do.
This insulating base material is selected from, for example, glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material, aramid non-woven fabric-epoxy resin base material, aramid non-woven fabric-polyimide resin base material In particular, a glass cloth epoxy resin substrate is most preferable.

  The thickness of the insulating substrate is preferably 100 μm or less, and more preferably in the range of 30 to 70 μm. The reason for this is that when the thickness exceeds 100 μm, there is a concern that the thickness of the substrate itself becomes large when it is multi-layered and cannot fit in the housing.

To form a via hole forming opening on the circuit board using a laser, a direct laser method in which a copper foil and an insulating base material are simultaneously drilled by laser irradiation, and a copper foil portion corresponding to a via hole of the copper foil is etched. There is a conformal method in which the insulating base material is perforated by laser irradiation after removal by the above method, either of which may be used in the present invention.
As for the thickness of the copper foil affixed on the said insulating base material, 5-20 micrometers is desirable.
The reason is that when the thickness of the copper foil is less than 5 μm, the end face of the copper foil corresponding to the via hole position is formed when the via hole forming opening is formed in the insulating base material using laser processing as will be described later. This is because it is difficult to form a conductor circuit having a predetermined shape because the portion may be deformed. Further, it is difficult to form a conductor circuit pattern having a fine line width by etching. On the other hand, when the thickness of the copper foil exceeds 20 μm, it is difficult to form a conductor circuit pattern having a fine line width by etching.

  The thickness of this copper foil may be adjusted by half etching. In this case, the thickness of the copper foil is larger than the above numerical value and is adjusted so that the thickness of the copper foil after etching falls within the above range.

  Moreover, when using a double-sided copper clad laminated board as a circuit board, although copper foil thickness is in the said range, the thickness may differ on both surfaces. Thereby, the strength can be ensured and the subsequent process can be prevented from being hindered.

As the insulating substrate and copper foil, in particular, a single-sided or double-sided copper-clad laminate obtained by laminating a copper foil with a prepreg in which epoxy resin is crushed in a glass cloth and copper foil is laminated and heated. It is preferable to use a plate.
The reason is that the position of the wiring pattern or via hole is not shifted during the manufacturing process after the copper foil is etched, and the positional accuracy is excellent.

(2) Next, an opening for forming a via hole is provided in the insulating base material by laser processing.
When a single-sided copper-clad laminate is used to form a circuit board, carbon dioxide laser irradiation is performed on the surface of the insulating base opposite to the side on which the copper foil is pasted, penetrating the insulating base and copper An opening reaching the foil (or conductor circuit pattern) is formed.
When using a double-sided copper-clad laminate to form a circuit board, irradiate carbon dioxide laser on one surface of the insulating base material to which the copper foil is pasted to penetrate both the copper foil and the insulating base material. Forming an opening that reaches the copper foil (or conductor circuit pattern) affixed to the other surface of the insulating base material, or the surface of one copper foil affixed to the insulating base material is smaller than the via hole diameter. After a hole having a slightly smaller diameter is formed by etching, carbon dioxide laser irradiation is performed using the hole as an irradiation mark, and the copper foil (or conductor) is attached to the other surface of the insulating substrate through the insulating substrate. An opening reaching the circuit pattern) is formed.

  Such laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus, and the processing conditions are such that the side wall of the opening for forming the via hole forms a taper of 60 to 90 degrees with respect to the surface of the insulating substrate. Decided.

For example, the taper angle of the opening sidewall can be adjusted by setting the pulse energy within the range of 0.5 to 100 mJ, the pulse width of 1 to 100 μs, the pulse interval of 0.5 ms or more, and the number of shots of 2 to 10. it can.
The diameter of the opening for forming a via hole that can be formed under the processing conditions is preferably 50 to 250 μm. This is because within that range, the taper can be surely formed and the density of the wiring can be increased.

(3) A desmear process for removing the resin residue remaining on the side wall and the bottom wall of the opening formed in the step (2) is performed.
This desmear treatment is performed by wet treatment such as chemical treatment of an acid or an oxidizing agent (for example, chromic acid or permanganic acid), or dry treatment such as oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, or excimer laser treatment. .
Which method to select from these desmear treatment methods is selected in consideration of the amount of smear that is expected to remain depending on the type, thickness, via hole opening diameter, laser irradiation conditions, etc. of the insulating substrate. .

(4) Next, the copper foil surface of the desmear-treated substrate is subjected to an electrolytic copper plating process using the copper foil as a plating lead, and the opening is completely filled with the electrolytic copper plating (filled via). ).
In some cases, after the electrolytic copper plating treatment, the electrolytic copper plating raised above the via hole opening of the substrate may be removed and flattened by belt sander polishing, buff polishing, etching, or the like.

  Moreover, after performing an electroless plating process, you may perform an electrolytic copper plating process. In this case, the electroless plating film may use a metal such as copper, nickel, or silver.

(5) Next, an etching resist layer is formed on the electrolytic copper plating film formed on the substrate in (4). The etching resist layer may be either a method of applying a resist solution or a method of applying a film-like one in advance. A mask on which a circuit is drawn in advance is placed on the resist layer, and an etching resist layer is formed by exposure and development, and the metal layer in the portion where the etching resist is not formed is etched to form a conductor circuit and a land. An included conductor circuit pattern is formed.

The etchant is preferably at least one aqueous solution selected from sulfuric acid-hydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
As a pretreatment to form a conductor circuit by etching the copper foil and the electrolytic copper plating film, the thickness is adjusted in advance by etching the entire surface of the electrolytic copper plating film in order to facilitate the formation of a fine pattern. Also good.
The land as a part of the conductor circuit preferably has an inner diameter that is substantially the same as the via hole diameter, or an outer diameter larger than the via hole diameter and a land diameter in the range of 75 to 350 μm. The reason is that by setting the land diameter within the above range, even if the via position is shifted, it can serve as a multistage stacked via.

  An insulating resin layer and a copper foil are laminated on one or both sides of the circuit board produced according to the steps (1) to (5) as a lamination center. As a result, a substrate in which only one or two insulating resin layers are formed is obtained.

  And by the same process as said (2)-(5), a via hole and a conductor circuit are formed in the laminated | stacked insulating resin layer, Furthermore, an insulating resin layer and copper foil are laminated | stacked, and said (2 ) To (5) are repeated to obtain a multilayered printed wiring board.

Above-described method is a lamination of the insulating resin layer, but the sequential multilayer insulating resin layer by performing a laminate is made, as required, the lamination of insulating resin layer, the circuit board of the insulating resin layer is 1 unit May be laminated into two or more layers, and may be heat-pressed together to form a multilayer printed wiring board.

In the multilayer printed wiring board formed by such a process, the via hole formed in each laminated circuit board or each insulating resin layer is the surface of the circuit board or the surface of the insulating resin layer on which the via hole is formed. On the other hand, a taper of 60 to 90 degrees is given at the inner angle. The via hole formed in at least two insulating resin layers including the circuit board serving as the lamination center constitutes the first via group and faces the insulating resin layer constituting the first via group. Via holes formed in at least two other insulating resin layers arranged and stacked constitute a second via group. The first via group and the second via group constitute a multi-stage stacked via, and each via group has a taper of 60 to 90 degrees at an inner angle with respect to the surface of the insulating resin layer in which the via hole is formed. Yes.

(6) Next, a solder resist layer is formed on the surface of the outermost circuit board. In this case, the solder resist composition is applied to the entire outer surface of the circuit board, the coating film is dried, and then a photomask film in which the opening of the solder pad is drawn is placed on the coating film to expose and develop. By processing, a solder pad opening exposing the conductive pad portion located immediately above the via hole of the conductor circuit is formed. In this case, an opening may be formed by attaching a solder resist layer using a dry film and exposing / developing or laser.
A corrosion-resistant layer such as nickel-gold is formed on the solder pad exposed from the portion where the photomask is not formed. At this time, the thickness of the nickel layer is desirably 1 to 7 μm, and the thickness of the gold layer is desirably 0.01 to 0.1 μm. In addition to these metals, nickel-palladium-gold, gold (single layer), silver (single layer), or the like may be formed.

  After forming the corrosion-resistant layer, the mask layer is peeled off. As a result, a printed wiring board in which a solder pad with a corrosion-resistant layer and a solder pad without a corrosion-resistant layer are mixed is obtained.

(7) A solder body is supplied to the solder pad portion exposed immediately above the via hole from the opening of the solder resist obtained in the step (6), and a solder bump is formed by melting and solidifying the solder body, or A conductive ball or a conductive pin is bonded to the pad portion using a conductive adhesive or a solder layer to form a multilayer circuit board.

As a method of supplying the solder body and the solder layer, a solder transfer method or a printing method can be used.
Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to the opening portion, thereby forming a solder pattern to form a solder carrier film. After the flux is applied to the solder resist opening portion of the substrate, the solder pattern is laminated so as to contact the pads, and this is heated and transferred.

  On the other hand, the printing method is a method in which a printing mask (metal mask) having an opening at a position corresponding to a pad is placed on a substrate, a solder paste is printed, and heat treatment is performed. As solder for forming such solder bumps, Sn / Ag solder, Sn / In solder, Sn / Zn solder, Sn / Bi solder, etc. can be used, and their melting points are connected between the circuit boards to be laminated. It is desirable that the melting point of the conductive bump is lower.

( Reference Example 1)
(1) First, a circuit board as one unit constituting the multilayer printed wiring board is manufactured. This circuit board is a board to be the lamination center among a plurality of insulating layers to be laminated, and a prepreg and a copper foil are laminated and heat-pressed by burying epoxy resin in a glass cloth. Is used as a starting material (see FIG. 9A).
The insulating substrate 12 had a thickness of 60 μm, and the copper foil 14 had a thickness of 12 μm. You may adjust the thickness of copper foil to 12 micrometers by etching process using the copper foil of this laminated board thicker than 12 micrometers.

(2) Carbon dioxide laser irradiation is performed on the double-sided circuit board 10 having the copper foil 14 to form a via hole forming opening 16 that penetrates the copper foil 14 and the insulating base material 12 and reaches the copper foil on the opposite surface. After that, the desmear treatment was performed in the opening formed by laser processing by chemical treatment with permanganic acid (see FIG. 9B).

In this reference example, the via hole forming opening 16 was formed by using a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Hitachi Via Co., Ltd., with a thickness of 12 μm thick copper foil attached. A 60 μm glass cloth epoxy resin base material was directly irradiated with a laser beam on a copper foil under the following processing conditions to form an opening 16 of 75 μmφ at a speed of 100 holes / second.
The opening 16 formed under such conditions was substantially frustoconical with the inner wall of the opening having a taper angle (inner angle) of 65 degrees with respect to the surface of the insulating substrate 12.

(Laser processing conditions)
Pulse energy: 0.5-100mJ
Pulse width: 1 to 100 μs
Pulse interval: 0.5 ms or more Number of shots: 2
Oscillation frequency: 2000 to 3000 Hz

(3) The surface of the copper foil 14 on the side provided with the via hole forming opening 16 after the desmear treatment is subjected to an electrolytic copper plating treatment using the copper foil as a plating lead under the following conditions, and an electrolytic copper plating film Was formed (see FIG. 9C).

[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 10.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 65 minutes Temperature 22 ± 2 ° C

  Additive A promotes the formation of an electrolytic copper plating film in the opening for forming the via hole, and conversely adheres to the copper foil portion mainly by additive B, thereby suppressing the formation of the electrolytic copper plating film. Further, when the inside of the opening for forming the via hole is completely filled with electrolytic copper plating and becomes almost the same level as the copper foil 14, the additive B is attached, so that the electrolytic copper plating film is formed in the same manner as the copper foil portion. Formation is suppressed.

Thereby, a via hole 20 in which the opening 16 is filled with electrolytic copper plating is formed, and the surface of the via hole 20 and the copper foil surface are formed at substantially the same level.
Moreover, you may adjust thickness by etching the conductor layer which consists of copper foil 14 and an electrolytic copper plating film. If necessary, the thickness of the conductor layer may be adjusted by a physical method of sander belt polishing and buff polishing.

(4) A resist made of a photosensitive dry film is formed to a thickness of 15 to 20 μm on the conductor layer made of the copper foil 14 and the electrolytic copper plating film on both surfaces of the substrate obtained by the step (3). did. A mask on which a conductor circuit including via hole lands was drawn was placed on the resist, and exposure / development processing was performed to form an etching resist layer 22 (see FIG. 9D). Then, the copper foil 14 and the electrolytic copper plating film exposed from the etching resist non-forming portion were subjected to an etching process using an etching solution composed of hydrogen peroxide / sulfuric acid to be dissolved and removed.

(5) Thereafter, the etching resist layer 22 is peeled off using an alkali solution, and a conductor circuit pattern 24 including via hole lands is formed. As a result, a via hole 20 that electrically connects the conductor circuit on the front surface and the back surface of the substrate is formed, and a circuit board is obtained in which the via hole 20 and the copper foil portion that forms the conductor circuit 24 are planarized. (See FIG. 9E).

(6) A prepreg having a thickness of 60 μm and a thickness of 12 μm, which is obtained by crushing an epoxy resin into a glass cloth with respect to the front and back surfaces of the circuit board obtained through the steps (1) to (5). A 60 μm-thick resin is formed on the circuit board by superimposing these copper foils on each other and heating and pressing them under pressing conditions of temperature: 80 to 250 ° C. and pressure: 1.0 to 5.0 kgf / cm 2. An insulating layer 26 and a conductor layer 28 having a thickness of 12 μm were stacked (see FIG. 10A).

(7) Next, in substantially the same manner as in the step (2), carbon dioxide laser irradiation is performed on both surfaces of the substrate under the following processing conditions to penetrate the resin insulating layer 26 and the conductor layer 28. A via hole forming opening 30 of 65 μmφ reaching the lower conductor circuit 24 was formed at a speed of 100 holes / second, and then the inside of the opening formed by laser processing was desmeared by chemical treatment of permanganic acid (see FIG. 10B). ).
The opening 30 formed under such conditions was substantially frustoconical with the inner wall of the opening having a taper angle (inner angle) of 65 degrees with respect to the surface of the resin insulating layer 26.

(Laser processing conditions)
Pulse energy: 0.5-100mJ
Pulse width: 1 to 100 μs
Pulse interval: 0.5 ms or more Number of shots: 2
Oscillation frequency: 2000 to 3000 Hz

(8) In substantially the same manner as in the step (3), the conductor layer 28 on the via hole forming opening side after the desmear treatment is subjected to an electrolytic copper plating treatment under the following conditions to obtain an electrolytic copper plating film 32 was formed (see FIG. 10C).

[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 10.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 65 minutes Temperature 22 ± 2 ° C

Thereby, a via hole 34 in which the opening 30 is filled with the electrolytic copper plating film 32 is formed, and the surface of the via hole 34 and the copper foil surface are formed at substantially the same level.

(9) A resist made of a photosensitive dry film was formed to a thickness of 15 to 20 μm on the electrolytic copper plating obtained in (8) in substantially the same manner as in the step (4). Etching is performed by placing a mask on which a conductor circuit, via hole 34 lands, etc. are drawn on this resist, imaging the second positioning mark with a camera, aligning the substrate, and performing exposure and development processing. A resist layer 36 was formed (see FIG. 10D).
Thereafter, the resist non-formed part was subjected to an etching process using an etching solution composed of hydrogen peroxide / sulfuric acid to remove the copper plating film and the copper foil corresponding to the non-formed part.

(10) Next, the etching resist layer 36 is peeled off with an alkaline solution to form a conductor circuit 38 including the via hole 34 and its land. As a result, a circuit board in which the via holes 34 connecting the front and back of the board and the copper foil portions forming the conductor circuit 38 are flattened is obtained (see FIG. 10E).

  Further, by repeating the steps (6) to (10), one more resin insulating layer 40 is formed, and electrolytic copper plating is filled in the opening provided in the resin insulating layer 40 to form a via hole 42. And a conductor circuit pattern 44 including a via hole land is formed. Thus, a multilayer printed wiring board in which two insulating layers and conductor circuits are formed on both surfaces of the double-sided circuit board 10 can be obtained (see FIG. 11).

  That is, a multilayer printed wiring board having 5 insulating layers and 6 conductor circuits is formed, and via holes formed in the double-sided circuit board and the two insulating layers stacked above the double-sided circuit board A via-hole formed in the two insulating layers stacked below the double-sided circuit board is also formed on the surface of the insulating layer, forming the first frustoconical via group having a taper of 65 degrees with respect to the surface. A second frustoconical via group having a taper of 65 degrees was formed, and the via groups were arranged so as to face each other and to be substantially collinear.

(11) A solder resist layer 46 was formed on the surfaces of the two insulating layers located on the outermost sides of the substrate obtained in (10).
First, a film-formed solder resist having a thickness of 20 to 30 μm was attached to the surface of the insulating layer on which the conductor circuit 38 was formed. Next, after performing a drying treatment at 70 ° C. for 20 minutes and 100 ° C. for 30 minutes, a soda lime glass base slope having a thickness of 5 mm in which a circular pattern (mask pattern) of the solder resist opening is drawn by the chromium layer, The side on which the chromium layer was formed was brought into close contact with the solder resist layer 46 and exposed to 1000 mJ / cm 2 of ultraviolet light, and DMTG development processing was performed.
Furthermore, heat treatment was performed under conditions of 120 ° C. for 1 hour and 150 ° C. for 3 hours to form a 20 μm thick solder resist layer 46 having an opening 48 (opening diameter 200 μm) corresponding to the pad portion (see FIG. 12A).

  Before the solder resist layer 46 is formed on the surface of the insulating layer located on the outermost side of the multilayer printed wiring board, a roughened layer can be provided as necessary.

(12) Next, the substrate on which the solder resist layer 46 is formed is applied to an electroless nickel plating solution having a pH of 5 and made of nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, and sodium citrate 10 g / 1. A nickel plating layer having a thickness of 5 μm was formed on the surface of the conductor circuit 38 exposed from the opening 48 by dipping for 5 minutes.
Further, the substrate was placed in an electroless gold plating solution composed of potassium gold cyanide 2 g / 1, ammonium chloride 75 g / 1, sodium citrate 50 g / 1, and sodium hypophosphite 10 g / 1 at 93 ° C. for 23 seconds. Immersion was performed to form a 0.03 μm-thick gold plating layer on the nickel plating layer, and a conductor pad 50 covered with a metal layer composed of a nickel plating layer and a gold plating layer was formed.

(13) Then, a metal mask was placed on the solder resist layer 46, a solder paste made of Sn / Pb solder or Sn / Ag / Cu having a melting point T2 of about 183 ° C. was printed, and the metal mask was removed. Thereafter, by reflowing at 183 ° C., a multilayer printed wiring board having a solder layer 52 formed on the conductor pad 50 exposed from the opening 48 was formed (see FIG. 12B).
Next, electronic parts such as capacitors and resistors are mainly mounted in the area where the solder layer 52 is not formed, and external terminals such as keypads are mainly mounted in the area where the solder layer 52 is formed. Thus, a multilayer printed wiring board was manufactured.

( Reference Example 2)
As shown in FIG. 3A, the via holes constituting the first via group and the second via group formed in the insulating layers laminated on the front and back surfaces of the double-sided circuit board, respectively, A multilayer printed wiring board was manufactured in substantially the same manner as in Reference Example 1 except that it was formed at a position shifted by a distance of about ½.

( Reference Example 3)
Each via hole constituting the first via group formed in the double-sided circuit board and the insulating layer laminated thereon and the second via group formed in the insulating layer laminated below the double-sided circuit board As shown in FIG. 3C , a multilayer printed wiring board was manufactured in substantially the same manner as in Reference Example 1 except that the multilayer printed wiring boards were formed at positions shifted from each other by substantially the via hole diameter.

( Reference Example 4)
Multi-layer printed wiring in which two insulating layers are laminated above the double-sided circuit board and one insulating layer is laminated below the double-sided circuit board, and the number of insulating layers is 4 and the number of conductor circuits is 5. A multilayer printed wiring board was produced in substantially the same manner as in Reference Example 1 except that the board was formed.

( Reference Example 5)
Multi-layer printed wiring in which two insulating layers are laminated above the double-sided circuit board and one insulating layer is laminated below the double-sided circuit board, and the number of insulating layers is 4 and the number of conductor circuits is 5. A multilayer printed wiring board was produced in substantially the same manner as in Reference Example 2 except that the board was formed.

(Reference Example 6 )
Multi-layer print in which two insulating layers are laminated above the double-sided circuit board and one insulating layer is laminated below the double-sided circuit board, and the number of insulating layers is 4 and the number of conductor circuits is 5. A multilayer printed wiring board was produced in substantially the same manner as in Reference Example 3 except that a wiring board was formed.

(Example 1 )
As shown in FIG. 4, the second via group formed in the insulating layer stacked below the double-sided circuit board is formed in the double-sided circuit board and the first via group formed in the insulating layer stacked above the double-sided circuit board. On the other hand, a multilayer printed wiring board was manufactured in substantially the same manner as in Reference Example 1 except that the layers were laminated with a positional relationship shifted in the horizontal direction by about the via hole diameter.

(Example 2 )
Multi-layer print in which two insulating layers are laminated above the double-sided circuit board and one insulating layer is laminated below the double-sided circuit board, and the number of insulating layers is 4 and the number of conductor circuits is 5. A multilayer printed wiring board was produced in substantially the same manner as in Example 1 except that the wiring board was formed.

(Example 3 )
As shown in FIG. 5B, the via hole forming the first via group is located at each vertex of a virtual square lattice (lattice interval: 10 mm) on the insulating substrate, and the via hole forming the other via group is formed. A multilayer printed wiring board was manufactured in substantially the same manner as in Reference Example 4 except that the layers were stacked so as to be positioned at the center of the virtual square lattice.

(Example 4 )
As shown in FIG. 6, the via hole forming the first via group is located at each vertex of the virtual triangular lattice (lattice interval: 20 mm) on the insulating substrate, and the via hole forming the second via group is formed. A multilayer printed wiring board was manufactured in substantially the same manner as in Reference Example 4 except that the holes were stacked at the center of the virtual triangular lattice.

(Example 5 )
As shown in FIG. 8A, the via holes constituting the first via group are located substantially at the center of the insulating substrate and are intensively arranged in a 40 mm × 40 mm region. Is substantially the same as in Reference Example 4, except that the via hole is disposed outside the central region of the peripheral region (40 mm × 40 mm) surrounding the central portion and inside the 70 mm × 100 mm region). A multilayer printed wiring board was manufactured.

(Comparative Example 1)
The via hole constituting the first via group was formed, but the second via group was not formed. Except for this, a multilayer printed wiring board was produced in substantially the same manner as in Reference Example 1.

(Comparative Example 2)
A via hole constituting the first via group and the second via group was not formed. Except for this, a multilayer printed wiring board was produced in substantially the same manner as in Reference Example 1.
The multilayer printed wiring boards manufactured according to the above Reference Examples 1 to 6, Examples 1 to 5 and Comparative Examples 1 to 2 are subjected to an evaluation test of item A, and each of the manufactured multilayer printed wiring boards is mounted on the housing of an electronic device. After storing in the body, the evaluation test of B item and C item was done. The results of those evaluation tests are shown in Table 1.

A. Substrate load test From the horizontal state in which one end of the substrate was fixed, the other side that was not fixed was lifted by about 3 cm, the substrate was warped, and then repeated to return to the horizontal state 30 times. After that, conduct a continuity test of the specific circuit corresponding to the multi-stage via, measure the amount of change in resistance value to check for open (conductor circuit breakage), calculate the rate of change in resistance, and display the result. It was shown in 1.
Resistance change rate = ((resistance value after substrate load test−resistance value before substrate load test) / resistance value before substrate load test)

B. Reliability Test A continuity test was conducted on the multilayer printed wiring boards obtained in Reference Examples 1-6, Examples 1-5, and Comparative Examples 1-2, and 10 good products were taken out at random. Then, under heat cycle conditions (-55 ° C / 3 minutes to 130 ° C / 3 minutes as one cycle, the number of cycles was 1000 times, 2000 times, and 3000 times, and allowed to stand for 2 hours each 1000 times. Later, a continuity test is performed to confirm the presence or absence of disconnection of the conductor circuit. The amount of change in connection resistance is 10% ((connection resistance value after heat cycle−initial connection resistance value) / initial connection resistance value. Table 1 shows the numbers considered as defective.

C. Drop test With the mounted liquid crystal display portion facing downward, the casing containing the substrate was naturally dropped from a height of 1 m. The number of drops was 50 times, 100 times, and 150 times, and the conduction of the conductor circuit was confirmed.
It should be noted that ◯ (Good) when the change amount of the connection resistance value is within 5%, Δ (Average) when the change amount of the connection resistance value is within 10%, and × (Poor) when the change amount of the connection resistance value exceeds 10%. Indicated.

( Additional reference example)
Based on the result of the evaluation item A, the taper angles of via holes constituting the first via group and the second via group (pointing to the inner angle with respect to the surface of the conductor circuit) are 55 degrees, 60 degrees, and 70 degrees. The simulation was performed on the assumption that a total of eight different angles were manufactured, such as degrees, 75 degrees, 80 degrees, 85 degrees, 90 degrees, and 95 degrees. For these substrates, items A. and B. evaluated in each example and comparative example. Table 2 shows the results of the resistance change rate by simulating the amount of change in connection resistance, assuming that the same substrate load test was performed 50 times.

As described above, external stress such as impact force when dropped can be suppressed and warping of the insulating layer can be suppressed, thus preventing cracks and disconnection of the conductor circuit, reliability of the mounting board and drop resistance It is possible to provide a multilayer printed wiring board that can alleviate the decrease in the thickness.

Claims (4)

In the multilayer printed wiring board in which the insulating layers and the conductor layers are alternately laminated, and the conductor layers are electrically connected via via holes provided in the insulating layers,
A first via group consisting of via holes provided in one of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer;
A second via group consisting of via holes provided in the other insulating layer of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer. And
Said first respectively via group and second via groups, has a tapered shape that each via hole is reduced in diameter toward the inside in the thickness direction of the insulating layer, substantially identical straight to each other in the thickness direction of the insulating layer Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating layer,
The first via group and the second via group are shifted in a direction substantially perpendicular to the thickness direction of the insulating layer, and are stacked so as to partially overlap each other in the thickness direction of the insulating layer. multilayer printed wiring board, characterized by that. At least one other insulating substrate having a conductor circuit is laminated on both surfaces of one insulating substrate having a conductor circuit, and a conductor circuit provided on the one insulating substrate and a conductor circuit provided on another insulating substrate are provided. In a multilayer printed wiring board that is electrically connected through via holes provided in each insulating substrate,
A first via group comprising a via hole provided in one of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate;
A second via group comprising via holes provided in the other of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate; And
Each of the first via groups and second via groups has a tapered shape in which each via hole is reduced in diameter toward the inside in the thickness direction of the insulating substrate, substantially the same straight one another in the thickness direction of the insulating substrate Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating substrate,
The first via group and the second via group are shifted in a direction substantially orthogonal to the thickness direction of the insulating substrate and stacked in a positional relationship that partially overlaps with each other in the thickness direction of the insulating substrate. multilayer printed wiring board, characterized by that. At least one layer of an outer insulating substrate having a conductor circuit is laminated on both surfaces of an inner insulating substrate having a conductor circuit, and the conductor circuit provided on the inner insulating substrate and the conductor circuit provided on the outer insulating substrate are: In multilayer printed wiring boards that are electrically connected through via holes provided in each insulating substrate,
A first via group comprising a via hole provided in one of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate;
A second via group comprising via holes provided in the other of the two outermost insulating substrates and at least one insulating substrate stacked inward from the insulating substrate; And
Each of the first via groups and second via groups has a tapered shape in which each via hole is reduced in diameter toward the inside in the thickness direction of the insulating substrate, substantially the same straight one another in the thickness direction of the insulating substrate Consists of stacked vias stacked and aligned on the line ,
Each via hole is filled with plating in an opening formed in the insulating substrate,
The first via group and the second via group are shifted in a direction substantially orthogonal to the thickness direction of the insulating substrate and stacked in a positional relationship that partially overlaps with each other in the thickness direction of the insulating substrate. multilayer printed wiring board, characterized by that.   4. The multilayer printed wiring board according to claim 1, wherein a thickness of the insulating layer or the insulating substrate is 100 μm or less. 5.

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