CN103891425B - The manufacture method of multi-layer wire substrate, probe card and multi-layer wire substrate - Google Patents
The manufacture method of multi-layer wire substrate, probe card and multi-layer wire substrate Download PDFInfo
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- CN103891425B CN103891425B CN201280051467.8A CN201280051467A CN103891425B CN 103891425 B CN103891425 B CN 103891425B CN 201280051467 A CN201280051467 A CN 201280051467A CN 103891425 B CN103891425 B CN 103891425B
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- layer
- interarea
- wire substrate
- insulator layer
- via conductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention provides the less multi-layer wire substrate of wiring spacing on a kind of mounting surface.Multi-layer wire substrate（1）Including base main body（12）And many wirings（14）.Base main body（12）With first and second interarea（12a、12b）.Many wirings（14）It is arranged on base main body（12）It is interior, and from the first interarea（12a）Towards the second interarea（12b）Side.Base main body（12）With the multiple insulator layers being stacked（13）.Wiring（14）Comprising being respectively arranged at multiple insulator layers（13）Via conductor（15）.In many wirings（14）At least one wiring in, be arranged on composition base main body（12）The first interarea（12a）Insulator layer be the first insulator layer（13a）On via conductor（15a）Diameter less than being arranged on multiple insulator layers（13）Except the first insulator layer（13a）The via conductor at least one of which in insulator layer in addition（15）Diameter.
Description
Technical field
The present invention relates to multi-layer wire substrate, possess the probe card of the multi-layer wire substrate and the system of multi-layer wire substrate
Make method.
Background technology
In the past, it is widely used on interarea and is equipped with the multi-layer wire substrate of IC etc..It is configured with multi-layer wire substrate
The many wirings that the back side is extended to since mounting surface.Many wirings are made up of the multiple via conductors for electrically connecting respectively.
For example between the wiring that the wiring on mounting surface is smaller than the back side is recorded in patent document 1 and patent document 2
Away from multi-layer wire substrate.
Prior art literature
Patent document
Patent document 1：Japanese Patent Laid-Open 2008-300482 publications
Patent document 2：Japanese Patent Laid-Open 2008-164577 publications
The content of the invention
The technical problems to be solved by the invention
In recent years, the miniaturization of the electronic component such as IC on multi-layer wire substrate is just continued to develop.Thus, wish
The wiring spacing hoped on mounting surface further reduces.
The present invention provides the less multi-layer wire substrate of wiring spacing on a kind of mounting surface.
Solve the technical scheme that technical problem is used
First multi-layer wire substrate involved in the present invention includes that base main body and Duo Gen are connected up.Base main body has first
And second interarea.Many wirings are arranged in base main body, and from the first interarea towards the second interarea side.Base main body has quilt
Multiple insulator layers of stacking.Wiring includes the via conductor being respectively arranged on multiple insulator layers.In many wirings extremely
In a few wiring, the via conductor on insulator layer i.e. first insulator layer of the first interarea for constituting base main body is arranged on
Diameter be less than and be arranged on mistake at least one of which in the insulator layer in addition to the first insulator layer of multiple insulator layers
The diameter of hole conductor.
The a certain particular aspects of the first multi-layer wire substrate involved in the present invention are, at many at least one of wiring
In wiring, the diameter of the via conductor being arranged on the first insulator layer be less than be arranged on multiple insulator layers except the first insulation
The diameter of the via conductor in any layer in insulator layer beyond body layer.
Another particular aspects of the first multi-layer wire substrate involved in the present invention are that the thickness of the first insulator layer is small
At least one layer of thickness in the insulator layer in addition to the first insulator layer of multiple insulator layers.
The yet another particular aspect of the first multi-layer wire substrate involved in the present invention is that the thickness of the first insulator layer is small
The thickness of each insulator layer in multiple insulator layers in addition to the first insulator layer.
Another particular aspects of the first multi-layer wire substrate involved in the present invention are to be provided with position on the first interarea
Recess between adjacent wire.
The still other particular aspects of the first multi-layer wire substrate involved in the present invention are that recess is arranged so that this
Adjacent wire is exposed to wall respectively.
Second multi-layer wire substrate involved in the present invention includes that base main body and Duo Gen are connected up.Base main body has first
And second interarea.Many wirings are arranged in base main body, and from the first interarea towards the second interarea side.Set on the first interarea
There is the recess between adjacent wire.
The a certain particular aspects of the second multi-layer wire substrate involved in the present invention are that recess is arranged so that this is adjacent
Wiring is exposed to wall respectively.
The respective a certain particular aspects of first and second multi-layer wire substrate involved in the present invention are that recess is set to
So that the recess surrounds the exposed division of the first interarea of wiring.
Another particular aspects of the second multi-layer wire substrate involved in the present invention are that base main body has what is be stacked
Multiple insulator layers.Wiring includes the via conductor being respectively arranged on multiple insulator layers.
The yet another particular aspect of the second multi-layer wire substrate involved in the present invention is to be arranged on the first interarea of composition
Via conductor has following part on insulator layer, and the part has from the surface with the first interarea opposite side of insulator layer
Start to the thicker shape in the first interarea side.
The respective a certain particular aspects of first and second multi-layer wire substrate involved in the present invention are that recess is set to
Reach the surface with the first interarea opposite side of the insulator layer for constituting the first interarea.
The respective another particular aspects of first and second multi-layer wire substrate involved in the present invention are, adjacent wire it
Between distance broadened to the second interarea side since the first interarea side.
The respective yet another particular aspect of first and second multi-layer wire substrate involved in the present invention is that multiple vias are led
At least one of body is with the conical by its shape narrowed initially towards the first interarea side from the second interarea side.
The respective another particular aspects of first and second multi-layer wire substrate involved in the present invention are respectively to be routed through
Multiple via conductors are directly electrically connected to constitute.
The respective another particular aspects of first and second multi-layer wire substrate involved in the present invention are that via conductor sets
It is set to the thickness direction for causing the central shaft of via conductor along insulator layer.
The respective still other particular aspects of first and second multi-layer wire substrate involved in the present invention are, many cloth
At least one in line includes following part, and in the portion, the wall of adjacent in a thickness direction via conductor is extremely
A few part is continuous.
The respective still other particular aspects of first and second multi-layer wire substrate involved in the present invention are, many cloth
At least one in line includes following part, and in the portion, via conductor adjacent in a thickness direction is used as overall tool
There is the conical by its shape attenuated initially towards the first interarea side from the second interarea side.
Probe card involved in the present invention is for the involved in the present invention first or second multi-layer wire substrate.
The manufacture method of multi-layer wire substrate involved in the present invention is on manufacturing involved in the present invention first or the
The manufacture method of two multi-layer wire substrates.In the manufacture method of multi-layer wire substrate involved in the present invention, prepare multiple using
In the ceramic green sheet for constituting insulator layer.Through hole is formed on multiple ceramic green sheets.Filled for constituting in through hole
The conductive paste of hole conductor.Multiple ceramic green sheets filled with conductive paste in through hole are laminated, are thus manufactured
The layered product of semi-finished product.Burnt till to obtain multi-layer wire substrate by the layered product to semi-finished product.By to ceramic green sheet
Laser is irradiated to form through hole.
The a certain particular aspects of the manufacture method of multi-layer wire substrate involved in the present invention are, for a ceramic green
Piece, forms multiple through holes, to cause that adjacent through hole is attached an interarea side.In one ceramic green of outermost layer stackup
Piece, to cause that an interarea is constituted the interarea of the layered product of semi-finished product.
Invention effect
In accordance with the invention it is possible to provide the less multi-layer wire substrate of wiring spacing on a kind of mounting surface.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 1.
Fig. 2 is the diagrammatic cross-sectional view of the probe card in implementation method 1.
Fig. 3（a）It is the diagrammatic cross-sectional view of the first thicker insulator layer.Fig. 3（b）It is the letter of the first relatively thin insulator layer
Want sectional view.
Fig. 4 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 2.
Fig. 5 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 3.
Fig. 6 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 4.
Fig. 7 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 5.
Fig. 8 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 6.
Fig. 9 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 7.
Figure 10 is the schematic top of a part for the multi-layer wire substrate involved by implementation method 7.
Figure 11（a）It is the diagrammatic cross-sectional view of the first insulator layer of multi-layer wire substrate involved by comparative example.Figure 11（b）
It is the diagrammatic cross-sectional view of the first insulator layer of multi-layer wire substrate involved by implementation method 7.
Figure 12 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 8.
Figure 13 is the diagrammatic cross-sectional view for illustrating the manufacturing process of the multi-layer wire substrate involved by implementation method 7.
Figure 14 is the diagrammatic cross-sectional view for illustrating the manufacturing process of the multi-layer wire substrate involved by implementation method 7.
Figure 15 is the diagrammatic cross-sectional view for illustrating the manufacturing process of the multi-layer wire substrate involved by implementation method 8.
Figure 16 is the diagrammatic cross-sectional view for illustrating the manufacturing process of the multi-layer wire substrate involved by implementation method 8.
Figure 17 is the diagrammatic cross-sectional view of the first insulator layer involved by variation 1.
Figure 18 is the diagrammatic cross-sectional view of the first insulator layer involved by variation 2.
Figure 19 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 9.
Figure 20 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 10.
Figure 21 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 11.
Figure 22 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 12.
Figure 23 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 13.
Figure 24 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by the variation of implementation method 2.
Specific embodiment
Below, an example for implementing the preferred embodiment of the present invention is illustrated.However, following implementation methods are only
Only it is to illustrate.The invention is not restricted to following any embodiments.
Additionally, in each accompanying drawing of the institute such as implementation method reference, being come with reference to substantially with identical work(with identical label
The component of energy.Additionally, the accompanying drawing of the institute such as implementation method reference is the figure of schematic description, the size of the object drawn in accompanying drawing
Ratio etc. may be with the difference such as dimensional ratios of the object in reality.Dimensional ratios of the mutual object of accompanying drawing etc. also have can
Can be different.Dimensional ratios of specific object etc. should refer to the following description to be judged.
(implementation method 1)
（The structure of multi-layer wire substrate 1）
Fig. 1 is the diagrammatic cross-sectional view of the multi-layer wire substrate 1 involved by implementation method 1.Multi-layer wire substrate 1 includes installing
Face 1a and back side 1b.Multi-layer wire substrate 1 can install the electronic components 10 such as IC chip to use for example on mounting surface 1a.This
Outward, as shown in Fig. 2 multi-layer wire substrate 1 is for example provided with probe unit 11 on mounting surface 1a, so as to be also used as probe
Card 2.
Multi-layer wire substrate 1 has base main body 12.Base main body 12 has first and second interarea 12a, 12b.Substrate
First interarea 12a of main body 12 constitutes mounting surface 1a.Second interarea 12b of base main body 12 constitutes back side 1b.
Base main body 12 has insulating properties.Base main body 12 has the multiple insulator layers 13 being stacked.Insulator layer 13
As long as constituent material insulator, be not particularly limited.Insulator layer 13 can be by such as ceramics with insulating properties
Material, resin etc. are constituted.Below, the situation that insulator layer 13 is made up of ceramic material is illustrated herein.
As the specific example of the ceramic material for preferably using, can include, for example, low-temperature sintered ceramics（LTCC：
Low Temperature Co-fired Ceramic）Material, high temperature sintering ceramics（HTCC：High Temperature Co-
fired Ceramic）Material etc..Here, so-called low-temperature sintered ceramics material is can be carried out at the temperature below 1050 DEG C
Sintering, and can the ceramic material that burns till simultaneously such as Au, Ag or Cu less with resistivity.
As the specific example of low-temperature sintered ceramics material, can include, for example, borosilicate glass is mixed into oxygen
Change aluminium or zirconium oxide, magnesia, forsterite etc. ceramic powders in and formed glass complex class LTCC materials, use ZnO-
MgO-Al2O3-SiO2The sintered glass ceramics class LTCC materials of the sintered glass ceramics of class and use BaO-Al2O3-SiO2Class ceramics
Powder or Al2O3-Cao-SiO2-MgO-B2O3Non-glass class LTCC materials of class ceramic powders etc. etc..
As the specific example of high temperature sintering ceramic material, can include, for example to aluminum oxide, aluminium nitride, mullite,
And add the sintering aid such as glass in other ceramics, and can more than 1100 DEG C at a high temperature of the ceramic material that is sintered
Deng.
In addition, the stacking number and thickness of insulator layer 13 can be carried out according to circuit structure of multi-layer wire substrate 1 etc.
Suitably set.The stacking number of insulator layer 13 can for example be set to 5 layers~30 layers or so.One layer of thickness in insulator layer 13
Such as 5 μm~50 μm or so can be set to.In addition, when using base main body 12 as probe card 2, the stacking of insulator layer 13
Numerical example can such as be set to 20 layers~100 layers or so.One layer of thickness can be set to such as 5 μm~200 μm left sides in insulator layer 13
It is right.
In present embodiment, insulator layer i.e. first insulator layer of the first interarea 12a is constituted in multiple insulator layers 13
Thickness of the thickness of 13a less than at least one of the insulator layer 13b in multiple insulator layers in addition to the first insulator layer 13a
Degree.Specifically, in the present embodiment, the first insulator layer 13a is than multiple insulator layer 13b any one be all thin.
It is preferred that the thickness of insulator layer 13a be the thickness of most thick insulator layer in multiple insulator layer 13b 3/4 with
Under, more preferably below 1/2.Specifically, the thickness of insulator layer 13a is preferably less than 75 μm, more preferably less than 50 μm.
But, if the thickness of insulator layer 13a is too small, more difficult formation insulator layer 13a.Therefore, the thickness of insulator layer 13a is preferred
It is more than 5 μm, more preferably more than 10 μm.
In addition, the thickness of multiple insulator layers 13 can be all identical, it is also possible to different.That is, in multiple insulator layers 13
The different various insulator layers of thickness can be included.
Many wirings 14 are provided with the inside of base main body 12.Many wirings 14 are set to be extended to from the first interarea 12a
Second interarea 12b.The distance between adjacent wire 14 is from the first interarea 12a sides（X1 sides）Start to the second interarea 12b sides（x2
Side）Broaden.Therefore, the distance between adjacent wire 14 is more than on the first interarea 12a between adjacent wire 14 on the second interarea 12b
Distance.
Wiring 14 includes the via conductor 15 for being respectively arranged at multiple insulator layers 13.Specifically, many connect up 14
A part is made up of the via conductor 15 on each layer for being arranged on multiple insulator layers 13, and a remaining part is by being arranged on multiple
Via conductor 15 on each layer of insulator layer 13 and it is arranged on the interface of adjacent insulator layer 13 on thickness direction x
Electrode 16 is constituted.
As long as in addition, constituting the material conductive material of via conductor 15 and electrode 16, there is no particular limitation.Respectively
Individual via conductor 15 and electrode 16 can be by for example with least one as main component in Ag, Cu, Ni, Pt, Pd, W, Mo and Au
Metal constitute.As with the various metals as main component in Ag, Cu, Ni, Pt, Pd, W, Mo and Au, can include for example
Ag-Pt alloys, Ag-Pd alloys etc..Wherein, because the resistivity of Ag, Ag-Pt alloy, Ag-Pd alloys and Cu is smaller therefore excellent
From the material for making wiring 14, the material of the wiring 14 of the multi-layer wire substrate 1 being particularly preferably used as the purpose of high-frequency applications.
In addition, in the case where insulator layer 13 is constituted using high temperature sintering ceramic material, preferably comprise from Mo, Pt, Pd,
At least one metal selected in the group that W and Ni is constituted is used as the material for constituting wiring 14.
Via conductor 15 is arranged so that the central shaft of via conductor 15 along the thickness direction of insulator layer 13.That is, mistake
The central shaft of hole conductor 15 is parallel with the thickness direction of insulator layer 13.
Via conductor 15 has from the second interarea 12b sides（X2 sides）Initially towards the first interarea 12a sides（X1 sides）Narrow
Conical by its shape.
In many at least one of wiring 14, the diameter for being arranged at the via conductor 15a of the first insulator layer 13a is less than
The diameter of the via conductor 15 being arranged at least one of which in multiple insulator layer 13b.More specifically, 14 are connected up at many
In, it is arranged at the surface of the second interarea 12b sides in the first insulator layer 13a of the via conductor 15a of the first insulator layer 13a
On diameter be less than be arranged on via conductor 15 at least one of which of multiple insulator layer 13b insulator layer 13b's
Diameter on the surface of the second interarea 12b sides.Specifically, in many at least one wirings of wiring 14, it is arranged at first
The diameter on the surface of the second interarea 12b sides of the first insulator layer 13a of the via conductor 15a of insulator layer 13a is less than
It is arranged at the straight on the surface of the second interarea 12b sides of insulator layer 13b of the via conductor 15 of any insulator layer 13b
Footpath.More specifically, many wiring 14 all wirings in, be arranged at the first insulator layer 13a via conductor 15a
Diameter on the surface of the second interarea 12b sides of the first insulator layer 13a is led less than the via for being arranged at any insulator layer 13b
The diameter on the surface of the second interarea 12b sides of insulator layer 13b of body 15.
In addition, the diameter of via conductor 15a can be set to such as 20 μm~100 μm or so.In addition to via conductor 15a
The diameter of via conductor 15 can be set to such as 40 μm~200 μm or so.The diameter of via conductor 15a is preferably except via is led
Less than 1/2 times of the diameter of the via conductor 15 outside body 15a, more preferably less than 1/5 times.
（The manufacture method of multi-layer wire substrate 1）
Below, an example to the manufacture method of multi-layer wire substrate 1 is illustrated.First, prepare multiple for structure
Into the ceramic green sheet of insulator layer 13.In the present embodiment, at least insulator layer 13a is different from the thickness of insulator layer 13b.
Accordingly, it would be desirable to prepare the ceramic green sheet for constituting insulator layer 13a and the ceramic green for constituting insulator layer 13b respectively
Piece.Ceramic green sheet for constituting insulator layer 13a is thinner than for constituting the ceramic green sheet of insulator layer 13b.
Ceramic green sheet for example, by the coating ceramic slurry on film carrier, and can be such that its drying is obtained to make.Ceramic slurry
The coating of material can be carried out for example, by print processes such as doctor blade methods.
Then, the through hole for forming via conductor is formed on ceramic green sheet（Via）.Through hole can be by example
Such as irradiate laser to be formed, it is also possible to formed using stamping machine.Wherein, laser is preferably used to form through hole.This be by
In using laser through hole can be formed with positional precision and form accuracy higher.Even if in addition, through hole relative to
Also can utilize laser to form through hole in the case of the thickness direction run-off the straight of ceramic green sheet, it is particularly suited for insertion
Hole along the thickness direction of ceramic green sheet situation.
In addition, using the through hole of laser formation in the conical by its shape narrowed towards laser direction of advance.
Then, via conductor is formed in the through hole for be formed at ceramic green sheet.Via conductor can be for example, by passing through
Conductive paste is filled in through hole to be formed.Can be for example, by suction or Vacuum printing to conductive paste is filled in through hole
Come carry out.
Then, multiple ceramic green sheets are suitably laminated so that for constitute the ceramic green sheet of insulator layer 13a into
It is most top layer, thus makes the layered product of semi-finished product.Pressure can be applied to the layered product of semi-finished product.
It is then possible to be burnt till to complete multi-layer wire substrate 1 by the layered product to semi-finished product.
As discussed above, in the present embodiment, constitute the first interarea 12a of base main body 12 first is exhausted
The thickness of edge body layer 13a is less than at least the one of the insulator layer 13b in addition to the first insulator layer 13a of multiple insulator layers 13
The thickness of layer, more specifically, less than the thickness of all of insulator layer 13b.Therefore, it is possible to make the wiring 14 on mounting surface 1a
Spacing it is smaller.On its reason, reference picture 3（a）And Fig. 3（b）It is described in detail.
Such as Fig. 3（a）It is shown, in the case where the first insulator layer 113a is thicker, due to the via conductor on interarea 113a2
The diameter R2 of 115a is larger relative to the diameter R1 of the via conductor 115a on interarea 113a1, it is therefore desirable to increase diameter R2.This
It is due in order to ensure reliably electrically connecting, it is necessary to which diameter R1 is set as the size more than to a certain degree.
On the other hand, such as Fig. 3（b）It is shown, in the case where the first insulator layer 13a is relatively thin, due on interarea 13a2
The diameter R3 of via conductor 15a does not have Fig. 3 relative to the diameter R1 of the via conductor 15a on interarea 13a1（a）Shown that
It is big.I.e., it is possible to be set to R3<R2.Therefore, the distance between centers L3=L2+R3 of via conductor 15a<The center of via conductor 115a
Between apart from L1=L2+R2.It follows that by making the thickness of insulator layer 13a less than at least one layer of thickness of insulator layer 13b
Degree, can make the spacing of wiring 14 on mounting surface 1a smaller.The spacing of the wiring 14 from further reduction mounting surface 1a
From the point of view of viewpoint, preferably make the thickness of insulator layer 13a less than the thickness of any insulator layer 13b.In addition, distance between centers L2 is
The factor determined by the machine drilling machine of perforate or the machining accuracy of laser, is identical value.
Additionally, from from the viewpoint of the spacing of the wiring 14 further reduced on mounting surface 1a, in wiring 14, preferably setting
It is placed in the diameter of the via conductor 15a of the first insulator layer 13a（Specifically, in the second interarea 12b sides of insulator layer 13a
Surface on via conductor 15a diameter R3）Less than the via conductor 15 in addition to via conductor 15a at least one it is straight
Footpath（Specifically, the diameter of the via conductor 15 on the surface of the second interarea 12b sides of insulator layer 13b）, more preferably
Less than the diameter of any via conductor 15 in addition to via conductor 15a.This is because, adjacent mistake can be made in this case
The distance between centers L3 of hole conductor 15a（=L2+R3）It is smaller.
Additionally, in the present embodiment, via conductor 15 has from the second interarea 12b sides initially towards the first interarea 12a
The conical by its shape that side narrows.Thus, while the distance between the wiring 14 on the first interarea 12a is made narrows, is easily made
Wiring the distance between 14 increases on two interarea 12b.
Below, other examples to the preferred embodiment of the present invention are illustrated.In the following description, identical is used
Label comes with reference to the component substantially with above-mentioned first embodiment with identical function, and omits the description.
（Implementation method 2 and implementation method 3）
Fig. 4 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 2.Fig. 5 is involved by implementation method 3
The diagrammatic cross-sectional view of multi-layer wire substrate.
In implementation method 1, the boundary of the insulator layer 13b for being configured at adjacent in a thickness direction is included in wiring 14
Electrode 16 on face.In the multi-layer wire substrate 3 involved by implementation method 2, as shown in figure 4, wiring 14 is by mutually directly entering
Multiple via conductors 15 of row electrical connection are constituted, with the laminates involved by implementation method 1 on this point without Interfacial electrode
Line substrate 1 is different.
In the present embodiment, because wiring 14 is only made up of multiple via conductors 15, it is thus possible to realize excellent height
Frequency characteristic.
But the present invention is not limited to the structure.For example, the multi-layer wire substrate 4 involved by implementation method 3 as shown in Figure 5
Like that, adjacent in a thickness direction via conductor 15 can also be electrically connected via electrode 16.
Additionally, as shown in figure 24, it is also possible to by being integrally provided in positioned at its lower floor positioned at the via conductor 15a of the superiors
Via conductor 15 top.
（Implementation method 4）
Fig. 6 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 4.It is all of exhausted in implementation method 4
Edge body layer 13 has identical thickness, in addition to the insulating barrier for being configured at the superiors, multiple is configured with other insulator layers 13
Via conductor 15, the via conductor 15 across insulator layer 13 at least two-layer and be continuously formed.By possessing this structure,
And using the insulating barrier 13 of same thickness, can make to be arranged at the via diameter of the via conductor 15a of the first insulator layer 13a with
Other via conductors 15 are compared to relatively small.
（Implementation method 5 and implementation method 6）
Fig. 7 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 5.Fig. 8 is involved by implementation method 6
The diagrammatic cross-sectional view of multi-layer wire substrate.
As shown in Figures 7 and 8, in implementation method 5 and the multi-layer wire substrate 5,6 involved by implementation method 6, many wirings
At least one of 14 includes following part, and in the portion, the wall of adjacent in a thickness direction via conductor 15 is extremely
A few part is continuous.Thereby, it is possible to realize more excellent high frequency characteristics.
Also, in multi-layer wire substrate 6, many at least one of wiring 14 includes following part, in the portion
Via conductor 15 adjacent in a thickness direction is in become initially towards the first interarea 12a sides from the second interarea 12b sides as entirety
Narrow conical by its shape.Thus, excellent high frequency characteristics is further realized.
In addition, from from the viewpoint of further realizing excellent high frequency characteristics, preferably all of wiring 14 is in from second
The conical by its shape that interarea 12b sides narrow initially towards the first interarea 12a sides.However, in this case, the second master of wiring 14
Diameter on the 12b of face is possible to become too much.It is therefore preferable that wiring 14 includes multiple following parts, in the portion in thickness
Adjacent via conductor 15 is in what is narrowed initially towards the first interarea 12a sides from the second interarea 12b sides as entirety on degree direction
Conical by its shape.
（Implementation method 7 and implementation method 8）
Fig. 9 is the diagrammatic cross-sectional view of the multi-layer wire substrate 7 involved by implementation method 7.Figure 10 is involved by implementation method 7
Multi-layer wire substrate a part schematic top.Figure 12 is the brief of the multi-layer wire substrate involved by implementation method 8
Sectional view.In addition, implementation method 8 and the equal reference picture 10 of implementation method 7.
Except the first insulator layer 13a and mistake in multi-layer wire substrate 7,8 involved by implementation method 7 and implementation method 8
Outside the structure of hole conductor 15a, with the structure substantially the same with multi-layer wire substrate 1 involved by implementation method 1.Cause
This, only illustrates difference of the multi-layer wire substrate 7,8 from multi-layer wire substrate 1 herein, and embodiment party is then quoted on other guide
The record of formula 1.
In implementation method 7 and implementation method 8, at least provided with a recess on the first interarea 12a for constituting mounting surface 1a
21.Recess 21 is located between the adjacent wire 14 on the first interarea 12a.Specifically, as shown in Figure 10, in the first interarea 12a
On, wiring 14 is configured to rectangular.The spacing relative narrower in the y-direction of wiring 14, the spacing in the z-direction of wiring 14 is relative
It is wider.In the present embodiment, recess 21 is configured between wiring 14 adjacent in y-direction, adjacent in a z-direction without configuring
Wiring 14 between.But, in the present invention, it is also possible to which recess is arranged between all of adjacent wire 14.Additionally, also may be used
So that recess to be placed around the exposed division of the first interarea of wiring, such as clathrate.
In the present embodiment, the plan view shape of recess is circle, but the shape of recess is not particularly limited.Recess
Can be such as rectangle, polygon, ellipse, Long Circle, or the shape along wiring 14.
Recess 21 can be set to not reach opposite with the first interarea 12a of the first insulator layer 13a as shown in Figure 9
The surface of side, it is also possible to be arranged to arrive at the first interarea 12a opposite with the first insulator layer 13a as shown in Figure 12
The surface of side.
In addition, in the present embodiment, also identical with implementation method 1~6, the thickness of preferably the first insulator layer 13a is small
In at least one layer of thickness of multiple insulator layer 13b, the thickness of more preferably less than any insulator layer 13b.However, differing
Surely need to make at least one layer of thickness of the thickness less than multiple insulator layer 13b of the first insulator layer 13a.For example, it is also possible to
Make the thickness of the first insulator layer 13a equal with the thickness of insulator layer 13b.
In the present embodiment, the via conductor 15a for being arranged at the first insulator layer 13a has from mounting surface 1a（First
Interarea 12a）Side（X1 sides）Initially towards back side 1b（Second interarea 12b）Side（X2 sides）=the part for narrowing.Specifically, via
Conductor 15a has from x1 sides initially towards x2 sides, in the shape that narrows afterwards of temporarily broadening.Towards the x2 sides of via conductor 15a
And the part for broadening is exposed to the part of recess 21.
For example, such as Figure 11（a）It is shown, it is provided with insulator layer 213a with narrowing with away from surface 213a1
Shape via conductor 215a in the case of, it is necessary to make the distance between via conductor 215a adjacent on the 213a1 of surface L11
More than the diameter of the via conductor 215a on the 213a1 of surface.This is due to that can occur between adjacent via conductor 215a
Short circuit.Accordingly, it is difficult to will be set apart from L11 smaller.
Unlike this, in the present embodiment, such as Figure 11（b）It is shown, due to being provided between adjacent vias conductor 15a
Recess 21, even if the distance between adjacent vias conductor 15a L12 are shorter, will not also occur between adjacent vias conductor 15a
Short circuit.Therefore, it is possible to be set apart from L12 shorter.For example, can make apart from L12 less than the via conductor on the 13a1 of surface
The diameter of 15a.Thereby, it is possible to make the spacing between the adjacent wire 14 on mounting surface 1a smaller.
As shown in Figure 13 or Figure 15, when multi-layer wire substrate 7,8 are manufactured, first, for constituting the first insulator layer
Multiple via conductor 15a are formed on the ceramic green sheet 22 of 13a.Then, as shown in Figure 14 or Figure 16, recess 21 is formed.Via is led
Body 15a can be after through hole be initially formed, by being formed to conducting paste is filled in through hole.Forming through hole
When, as shown in figure 13, multiple through holes can be formed, to cause that adjacent through hole is not contacted.Additionally, as shown in figure 14, also may be used
To form multiple through holes, to cause that adjacent through hole is connected on the surface of ceramic green sheet 22.Through the above way, can make
The spacing of wiring 14 is more narrow.In addition, in this case, after just conducting paste has been filled, adjacent vias conductor is each other
State in being connected.However, due to being formed with recess 21, finally, in electric insulation between adjacent vias conductor
State.
In addition, the formation of recess 21 can be carried out before layered product is formed, it is also possible to carried out after layered product is formed.
In addition, in the present embodiment, the knot to forming recess in the way of removing a part for adjacent vias conductor
Structure is illustrated, but as shown in Figure 17, Figure 18, it is also possible to adjacent vias conductor 15a is not removed, and in adjacent vias conductor
Recess 21 is set between 15a.Manufacture multi-layer wire substrate when, if the distance between adjacent vias conductor 15a shortens, from
In one through hole of the lateral ceramic green sheet of interarea in the operation of filling conductivity type thickener, in another interarea side of ceramic green sheet
Conductive paste can be produced to ooze out and cause problem as short circuit, therefore, shorten the distance between adjacent vias conductor 15a's
Limitation.However, in the present embodiment, after to conductive paste is filled in through hole, by carrying out in ceramic green
The operation of recess is formed between the adjacent vias conductor of another interarea side of piece, electric insulation is between adjacent vias conductor can be made
State, therefore compared with existing situation, the distance between adjacent vias conductor 15a can be made to shorten, i.e., can shorten wiring
Spacing.
（Implementation method 9~11）
Figure 19 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 9.Figure 20 is involved by implementation method 10
And multi-layer wire substrate diagrammatic cross-sectional view.Figure 21 is the brief section view of the multi-layer wire substrate involved by implementation method 11
Figure.
As shown in figure 19, in implementation method 9, identical with implementation method 2, wiring 14 is by being mutually directly electrically connected
Multiple via conductors 15 are constituted, on this point without Interfacial electrode with the multi-layer wire substrate 7 involved by implementation method 7 not
Together.
In the present embodiment, because wiring 14 is only made up of multiple via conductors 15, it is thus possible to realize excellent height
Frequency characteristic.
As shown in figure 20, in implementation method 10, many at least one of wiring 14 includes following part, in the part
In, at least a portion of the wall of adjacent in a thickness direction via conductor 15 is continuous.It is more excellent thereby, it is possible to realize
Different high frequency characteristics.
Also, in implementation method 11, many at least one of wiring 14 includes following part, in the portion in thickness
Adjacent via conductor 15 is in what is narrowed initially towards the first interarea 12a sides from the second interarea 12b sides as entirety on degree direction
Conical by its shape.It is linearly because the side of via conductor 15 does not bend, therefore further realize excellent high frequency characteristics.
(implementation method 12)
Figure 22 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 12.As shown in figure 22, in embodiment party
It is identical with implementation method 1 in formula 12, the via conductor 15 for constituting many wirings 14 is configured with the inside of base main body 12, but
Different on this point following, i.e., in the middle of base main body 12, the tapered direction of via conductor 15 there occurs reversely.It is logical
Cross and be at least formed as from the first interarea 12a sides the via conductor 15 for constituting the insulator layer 13 of the second interarea 12b（X1 sides）Open
Begin towards the second interarea 12b sides（X2 sides）The conical by its shape for narrowing, can make the distance between wiring 14 on the second interarea 12b
It is wider.
(implementation method 13)
Figure 23 is the diagrammatic cross-sectional view of the multi-layer wire substrate involved by implementation method 13.As shown in figure 23, although in base
The inside of plate main body 12 forms many wirings 14 since the first interarea 12a to the second interarea 12b sides, but can be by many cloth
Line 14 is set to be not extend to the second interarea 12b.In this case, many at least one insulators of wiring 14 are not being formed
Other circuits 17a, 17b can be set on layer 13c.Even if in this case, it is also possible to obtain and the phase such as above-mentioned implementation method
Same effect.
Symbol description
1,3~8 multi-layer wire substrates
1a mounting surfaces
The 1b back sides
2 probe cards
10 electronic components
11 probe units
12 base main bodies
The interareas of 12a first
The interareas of 12b second
13rd, 13a, 13b insulator layer
14 wirings
15 via conductors
16 electrodes
21 recesses
22 ceramic green sheets
Claims (14)
1. a kind of multi-layer wire substrate, the multi-layer wire substrate includes base main body, Yi Jishe with first and second interarea
Put in the base main body, and from first interarea initially towards many of the second interarea side wirings, its feature exists
In,
The base main body has the multiple insulator layers being stacked,
The wiring includes the via conductor for being respectively arranged at multiple insulator layers,
In many at least one wirings of the wiring, the insulation of first interarea for constituting the base main body is arranged on
Body layer be the via conductor on the first insulator layer diameter be less than be arranged on multiple insulator layers except described the
The diameter of the via conductor at least one of which in insulator layer beyond one insulator layer,
Each less than multiple insulator layers in addition to first insulator layer of the thickness of first insulator layer
The insulator layer beyond the thickness of insulator layer, and first insulator layer has equal thickness,
On first interarea, the recess between the adjacent wiring is provided with,
Multiple via conductors are routed through described in each to be directly electrically connected and constitute.
2. multi-layer wire substrate as claimed in claim 1, it is characterised in that
In at least one wiring of many wirings, the via conductor being arranged on first insulator layer it is straight
Footpath is less than the mistake being arranged in multiple insulator layers in any layer of the insulator layer in addition to first insulator layer
The diameter of hole conductor.
3. multi-layer wire substrate as claimed in claim 1, it is characterised in that
The recess is arranged so that the adjacent wire is exposed to wall respectively.
4. multi-layer wire substrate as claimed in claim 1, it is characterised in that
The recess is placed around the exposed division of first interarea of the wiring.
5. multi-layer wire substrate as claimed in claim 1 or 2, it is characterised in that
Being arranged on via conductor on the insulator layer for constituting first interarea has in the part of following shape, i.e., from institute
State the shape that the surface of the first interarea opposite side of insulator layer broadens initially towards the first interarea side.
6. multi-layer wire substrate as claimed in claim 1, it is characterised in that
The recess is arranged to arrive at the first interarea opposite side with the insulator layer for constituting first interarea
Surface.
7. multi-layer wire substrate as claimed in claim 1 or 2, it is characterised in that
The distance between adjacent described wiring expands since the first interarea side to the second interarea side.
8. multi-layer wire substrate as claimed in claim 1 or 2, it is characterised in that
At least one of multiple via conductors has and narrows initially towards the first interarea side from the second interarea side
Conical by its shape.
9. multi-layer wire substrate as claimed in claim 1 or 2, it is characterised in that
The via conductor is arranged so that the central shaft of the via conductor along the thickness direction of the insulator layer.
10. multi-layer wire substrate as claimed in claim 1 or 2, it is characterised in that
At least one wiring of many wirings includes following part, in the portion, adjacent institute in a thickness direction
At least a portion for stating the wall of via conductor is continuous.
11. multi-layer wire substrates as claimed in claim 1 or 2, it is characterised in that
At least one wiring of many wirings includes following part, in the portion, adjacent institute in a thickness direction
Via conductor is stated as the overall conical by its shape for having and attenuating initially towards the first interarea side from the second interarea side.
A kind of 12. probe cards, it is characterised in that
With the multi-layer wire substrate as described in any one such as claim 1 to 11.
13. a kind of manufacture methods of multi-layer wire substrate, for manufacturing the laminates as described in any one of claim 1 to 11
Line substrate, it is characterised in that including：
Prepare multiple operations for constituting the ceramic green sheet of the insulator layer；
The operation of through hole is formed on multiple ceramic green sheets；
To the operation that the conductive paste for constituting the via conductor is filled in the through hole；
Multiple ceramic green sheets filled with the conductive paste in through hole are laminated, the layered product of semi-finished product is manufactured
Operation；And
Burnt till to obtain the operation of multi-layer wire substrate by the layered product to the semi-finished product,
Laser is irradiated to the ceramic green sheet to form the through hole.
The manufacture method of 14. multi-layer wire substrates as claimed in claim 13, it is characterised in that
For a ceramic green sheet, multiple through holes are formed, to cause that adjacent through hole is carried out an interarea side
Connection,
In one ceramic green sheet of outermost layer stackup, to cause that an interarea is constituted the interarea of the semi-finished product layered product.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011231670 | 2011-10-21 | ||
| JP2011-231670 | 2011-10-21 | ||
| PCT/JP2012/077048 WO2013058351A1 (en) | 2011-10-21 | 2012-10-19 | Multilayer wiring substrate, probe card, and method for manufacturing multilayer wiring substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103891425A CN103891425A (en) | 2014-06-25 |
| CN103891425B true CN103891425B (en) | 2017-06-13 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201280051467.8A Active CN103891425B (en) | 2011-10-21 | 2012-10-19 | The manufacture method of multi-layer wire substrate, probe card and multi-layer wire substrate |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9456494B2 (en) |
| JP (1) | JP5772970B2 (en) |
| CN (1) | CN103891425B (en) |
| WO (1) | WO2013058351A1 (en) |
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| JPWO2015076121A1 (en) * | 2013-11-20 | 2017-03-16 | 株式会社村田製作所 | Multilayer wiring board and probe card having the same |
| JP6380547B2 (en) * | 2014-09-30 | 2018-08-29 | 株式会社村田製作所 | Multilayer board |
| CN108713354B (en) * | 2016-03-03 | 2020-12-11 | 株式会社村田制作所 | Laminated wiring substrate for probe card and probe card provided with same |
| JP6712765B2 (en) * | 2016-05-31 | 2020-06-24 | パナソニックＩｐマネジメント株式会社 | High frequency board |
| JP6777525B2 (en) | 2016-12-21 | 2020-10-28 | 日本碍子株式会社 | Heat resistant element for current detection |
| JP2018163901A (en) * | 2017-03-24 | 2018-10-18 | イビデン株式会社 | Print circuit board |
| US20230182368A1 (en) * | 2020-04-29 | 2023-06-15 | Liquiform Group Llc | Seal pin for container forming and filling |
| CN111741592B (en) * | 2020-06-17 | 2021-09-21 | 珠海越亚半导体股份有限公司 | Multilayer substrate and manufacturing method thereof |
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| JPH04258198A (en) * | 1991-02-13 | 1992-09-14 | Fujitsu Ltd | Multiple-layer printed circuit board for large current processing |
| JP3724468B2 (en) * | 1995-04-28 | 2005-12-07 | 日本ビクター株式会社 | Multilayer printed circuit board |
| TW323432B (en) | 1995-04-28 | 1997-12-21 | Victor Company Of Japan | |
| JP3629348B2 (en) | 1997-04-16 | 2005-03-16 | 新光電気工業株式会社 | Wiring board |
| JPH11284334A (en) | 1998-03-27 | 1999-10-15 | Kyocera Corp | Method for filling through hole with metallic paste in ceramic green sheet |
| JP2000133934A (en) | 1998-10-23 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Device for filling conductor into ceramic board |
| JP2005072328A (en) * | 2003-08-26 | 2005-03-17 | Kyocera Corp | Multilayer wiring board |
| JP2005072508A (en) * | 2003-08-27 | 2005-03-17 | Kyocera Corp | Circuit board |
| JP2005108950A (en) * | 2003-09-29 | 2005-04-21 | Matsushita Electric Ind Co Ltd | Ceramic modular component and its manufacturing method |
| JP2005268692A (en) * | 2004-03-22 | 2005-09-29 | Mitsubishi Electric Corp | Method for manufacturing multilayer substrate |
| JP4272568B2 (en) * | 2004-03-24 | 2009-06-03 | 京セラ株式会社 | Multiple wiring board |
| US20060289202A1 (en) * | 2005-06-24 | 2006-12-28 | Intel Corporation | Stacked microvias and method of manufacturing same |
| US7834273B2 (en) * | 2005-07-07 | 2010-11-16 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP4897961B2 (en) * | 2006-12-08 | 2012-03-14 | 日本特殊陶業株式会社 | Wiring board for electronic component inspection and manufacturing method thereof |
| US7875810B2 (en) | 2006-12-08 | 2011-01-25 | Ngk Spark Plug Co., Ltd. | Electronic component-inspection wiring board and method of manufacturing the same |
| JP5092547B2 (en) | 2007-05-30 | 2012-12-05 | 凸版印刷株式会社 | Method for manufacturing printed wiring board |
| KR101489798B1 (en) * | 2007-10-12 | 2015-02-04 | 신꼬오덴기 고교 가부시키가이샤 | Wiring board |
| JP5289880B2 (en) * | 2007-10-12 | 2013-09-11 | 新光電気工業株式会社 | Wiring board |
| JP2009188362A (en) | 2008-02-08 | 2009-08-20 | Japan Electronic Materials Corp | Ceramic laminated substrate and its manufacturing method |
| JP2010056482A (en) * | 2008-08-29 | 2010-03-11 | Fujitsu Ltd | Printed wiring board and conductive material |
| JP5083906B2 (en) | 2008-10-30 | 2012-11-28 | 京セラＳｌｃテクノロジー株式会社 | Wiring board manufacturing method |
| US8929090B2 (en) * | 2010-01-22 | 2015-01-06 | Nec Corporation | Functional element built-in substrate and wiring substrate |
-
2012
- 2012-10-19 CN CN201280051467.8A patent/CN103891425B/en active Active
- 2012-10-19 WO PCT/JP2012/077048 patent/WO2013058351A1/en active Application Filing
- 2012-10-19 JP JP2013539696A patent/JP5772970B2/en active Active
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2014
- 2014-04-01 US US14/231,780 patent/US9456494B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103891425A (en) | 2014-06-25 |
| JP5772970B2 (en) | 2015-09-02 |
| US9456494B2 (en) | 2016-09-27 |
| JPWO2013058351A1 (en) | 2015-04-02 |
| WO2013058351A1 (en) | 2013-04-25 |
| US20140209356A1 (en) | 2014-07-31 |
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