JP4897961B2 - Wiring board for electronic component inspection and manufacturing method thereof - Google Patents

Wiring board for electronic component inspection and manufacturing method thereof Download PDF

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JP4897961B2
JP4897961B2 JP2007036064A JP2007036064A JP4897961B2 JP 4897961 B2 JP4897961 B2 JP 4897961B2 JP 2007036064 A JP2007036064 A JP 2007036064A JP 2007036064 A JP2007036064 A JP 2007036064A JP 4897961 B2 JP4897961 B2 JP 4897961B2
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laminate
back surface
land
green sheet
wiring
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JP2008164577A (en
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一哉 野津
俊寿 野村
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NGK Spark Plug Co Ltd
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Description

本発明は、電子部品の導通性や動作の可否を検査するための電子部品検査用配線基板およびその製造方法に関する。   The present invention relates to an electronic component inspection wiring board for inspecting the continuity and operation of electronic components and a method for manufacturing the same.

ICチップやLSIなどの被検査電子部品の導通性や動作の可否を検査するため、かかる電子部品を搭載する表面を有し且つ有機絶縁層の間に形成した複数の薄膜配線層と、かかる薄膜配線層の下層にビア導体を貫通させたセラミックからなるベース基板と、からなるプローブカードが提案されている(例えば、特許文献1参照)。   A plurality of thin film wiring layers having a surface on which such electronic components are mounted and formed between organic insulating layers, and such thin films, in order to inspect the continuity and operation of electronic components to be inspected such as IC chips and LSIs There has been proposed a probe card including a base substrate made of ceramic with a via conductor penetrating under a wiring layer (see, for example, Patent Document 1).

特開2006−275714号公報(第1〜6頁、図1〜5)JP 2006-275714 A (pages 1 to 6, FIGS. 1 to 5)

ところで、被検査電子部品を搭載する表面を有し且つかかる電子部品の検査情報を収集する比較的高密度の配線層を複数のセラミック層間に有する第1積層体と、かかる第1積層体の下方に積層され且つ複数のセラミック層をビア導体が貫通する第2積層体とを形成する場合、両者の配線層などの導体の密度が異なっている。このため、第1・第2積層体間の焼成収縮には、それなりの差を生じる場合があった。その結果、第1積層体と第2積層体とに同じ割掛け率を適用し、これらを積層して同時に焼成した場合、得られるセラミック基板の表層に位置するパッド、もしくは表層に露出するビア導体が、所望の位置からズレているため、被検査電子部品の検査情報が正確に収集できなくなる、という問題があった。   By the way, the 1st laminated body which has the surface which mounts the to-be-inspected electronic component, and has a comparatively high-density wiring layer which collects the inspection information of this electronic component between several ceramic layers, Below this 1st laminated body In the case of forming a second laminated body in which via conductors pass through a plurality of ceramic layers, the densities of the conductors such as the wiring layers of the two are different. For this reason, a certain difference may occur in the firing shrinkage between the first and second laminates. As a result, when the same ratio is applied to the first laminated body and the second laminated body, and these are laminated and fired at the same time, the pads located on the surface layer of the resulting ceramic substrate, or the via conductor exposed on the surface layer However, since there is a deviation from a desired position, there is a problem that the inspection information of the electronic component to be inspected cannot be collected accurately.

本発明は、背景技術において説明した問題点を解決し、複数のセラミック層間に次述する第2積層体よりも比較的高密度の配線層を有する第1積層体と、かかる第1積層体の裏面側に積層され且つ複数のセラミック層をビア導体が貫通する第2積層体とからなり、被検査電子部品の検査情報を正確に収集できる電子部品検査用配線基板およびその製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, and includes a first laminate having a wiring layer having a relatively higher density than the second laminate described below between a plurality of ceramic layers, and the first laminate. Provided is a wiring board for inspecting electronic components and a method for manufacturing the same, comprising a second laminated body that is laminated on the back side and through which a via conductor penetrates a plurality of ceramic layers, and that can accurately collect inspection information of electronic components to be inspected. This is the issue.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、第1積層体および第2積層体を同じ材料組成のセラミックにより形成し、且つ第1積層体および第2積層体の各々に形成されたビア導体同士間を接続するランドを大径にすると共に、第1積層体と第2積層体とを製造する際に、両者の割掛け率を相違させる、ことに着想して成されたものである。
即ち、本発明の電子部品検査用配線基板(請求項1)は、複数のセラミック層からなり、表面に形成され複数のパッド、前記セラミック層間に形成された配線層、および上記パッドと配線層と裏面との間を接続する複数のビア導体を有する第1積層体と、上記セラミック層と同じ材料組成で且つ複数のセラミック層からなり、表面と裏面との間を貫通する複数のビア導体を有し、上記第1積層体の裏面側に積層された第2積層体と、を備え、上記第1積層体の導体密度は、第2積層体の導体密度に比べて、高密度であり上記両積層体の焼成収縮率が相違することに対応して、該第1積層体と第2積層体とを製造する際の両積層体の割掛け率を相違させており、上記第1積層体と第2積層体との間には、第1積層体の裏面に露出するビア導体と第2積層体の表面に露出するビア導体とを接続する複数のランド、およびかかるランドの周りに隙間を介して位置するベタ状の配線層が配置されており、上記ランドの直径は、上記2つのビア導体の直径の2〜5倍である、ことを特徴とする。
In order to solve the above-mentioned problem, the present invention provides that the first laminated body and the second laminated body are formed of ceramics having the same material composition, and between via conductors formed in each of the first laminated body and the second laminated body. The idea is to make the land connecting the two large-diameters and to make the percentages of the two different when the first laminated body and the second laminated body are manufactured.
That is, an electronic component inspection wiring board according to the present invention comprises a plurality of ceramic layers, a plurality of pads formed on the surface, a wiring layer formed between the ceramic layers, and the pads and wiring layers. A first laminate having a plurality of via conductors connecting between the back surface and a plurality of via conductors having the same material composition as the ceramic layer and including a plurality of ceramic layers and penetrating between the front surface and the back surface. and, and a second laminate laminated to the back surface side of the first laminate, the conductor density of the first laminate, as compared to the conductor density of the second laminate was high, the Corresponding to the difference in firing shrinkage between the two laminates, the first laminate and the second laminate are produced at different rates. Via conductor exposed on the back surface of the first laminated body between the first laminated body and the second laminated body A plurality of lands that connect via conductors exposed on the surface of the second laminate, and a solid wiring layer located around the lands with a gap between them are arranged, and the diameter of the lands is 2 2 to 5 times the diameter of one via conductor.

これによれば、第1積層体と第2積層体との配線層などの導体の密度が相違し、両積層体の焼成収縮率が相違することに対応して、第1積層体と第2積層体との割掛け率を互いに異ならしめた場合であっても、第1積層体の裏面に露出するビア導体と、第2積層体の表面に露出するビア導体とを、前記ランドを介して確実に接続した状態で、第1・第2積層体が積層されている。従って、第1積層体の表面のパッド上に搭載したICチップやLSIなどの被検査電子部品に通電したり、かかる電子部品の検査情報を正確に収集することが可能となる。
しかも、ベタ状の前記配線層は、電源層または接地層として活用できるため、被検査電子部品への給電や、第1積層体に形成された配線層などの接地に活用することが可能となる
尚、前記ランドの直径が前記ビア導体の直径の2倍未満になると、かかるランドとビア導体との導通が取りにくくなるおそれがあり、一方、ランドの直径がビア導体の直径の5倍を越えると、当該ランドの面積が過大となり、所望数のビア導体を配置することが困難となる。このため、ランドの直径を前記範囲とした。
According to this, the density of conductors such as the wiring layers of the first laminate and the second laminate is different, and the first and second laminates are different from each other in terms of the firing shrinkage rates. Even when the rate of splitting with the multilayer body is different from each other, via conductors exposed on the back surface of the first multilayer body and via conductors exposed on the surface of the second multilayer body are interposed via the lands. The first and second stacked bodies are stacked in a securely connected state. Therefore, it is possible to energize the electronic component to be inspected such as an IC chip or LSI mounted on the pad on the surface of the first laminated body, or to accurately collect inspection information of the electronic component.
Moreover, since the solid wiring layer can be used as a power supply layer or a grounding layer, it can be used for power feeding to the electronic component to be inspected or grounding of the wiring layer formed in the first laminate. .
If the diameter of the land is less than twice the diameter of the via conductor, it may be difficult to establish conduction between the land and the via conductor. On the other hand, the diameter of the land exceeds five times the diameter of the via conductor. Then, the area of the land becomes excessive, and it becomes difficult to arrange a desired number of via conductors. For this reason, the diameter of the land was made into the said range.

また、前記第1・第2積層体を形成するセラミック層の素材は、同じ材料組成のアルミナなどからなる高温焼成セラミック、あるいは、同じ材料組成のガラス−セラミックなどからなる低温焼成セラミックである。
更に、前記配線層やビア導体は、高温焼成セラミックの場合には、WまたはMoで形成され、低温焼成セラミックの場合には、AgまたはCuで形成される。
また、前記ランドの周りで且つ同じ平面に配置されるベタ状の配線層は、接地用あるいは電源用の配線層である
The material of the ceramic layer forming the first and second laminates is a high-temperature fired ceramic made of alumina having the same material composition, or a low-temperature fired ceramic made of glass-ceramic having the same material composition.
Further, the wiring layer and the via conductor are formed of W or Mo in the case of a high-temperature fired ceramic, and are formed of Ag or Cu in the case of a low-temperature fired ceramic.
Moreover, solid shaped wiring layer and are located on the same plane around the land is a wiring layer for grounding or for power.

一方、本発明による電子部品検査用配線基板の製造方法(請求項2)は、上下2組で且つ同じ材料組成のセラミックからなる複数ずつのグリーンシートに対し、上側の組の各グリーンシートには相対的に大きな割掛け率に従った位置に複数のビアホールを形成すると共に、下側の組の各グリーンシートには相対的に小さな割掛け率に従った位置に複数のビアホールを形成する工程と、前記ビアホールごとに金属粉末を含む導電性ペーストを充填してビア導体を形成する工程と、上記上側の組における複数のグリーンシートの表面および裏面の少なくとも一方に上記同様の導電性ペーストからなる配線層を形成する工程と、上記上側の組における最下層のグリーンシートの裏面と、下側の組における最上層のグリーンシートの表面との間において、前者の裏面と後者の表面とに露出するビア導体を、これらの直径よりも2倍以上大きなランドを介して接続し、且つ該ラドの周りに隙間を介してベタ状の配線層が位置するように、上下2組の各グリーンシートを積層することにより、上側の組からなり導体密度が相対的に高い第1積層体と下側の組からなり導体密度が相対的に低い第2積層体とを有するグリーンシート積層体を形成する工程と、上記グリーンシート積層体を焼成する工程と、含む、ことを特徴とする。 On the other hand, the method for manufacturing a wiring board for inspecting electronic components according to the present invention (Claim 2) includes a plurality of green sheets made of ceramics having the same material composition in two upper and lower sets, and each green sheet in the upper set and forming a plurality of via holes in relatively accordance with large numbers multiplying ratio position, forming a plurality of via holes in the position according to a relatively small split multiplying ratio is below the set of the green sheets A process of forming a via conductor by filling a conductive paste containing metal powder for each via hole, and a wiring made of the same conductive paste on at least one of the front and back surfaces of the plurality of green sheets in the upper set Forming a layer, and between the back surface of the lowermost green sheet in the upper set and the surface of the uppermost green sheet in the lower set The via conductor exposed to the former back surface and the latter surface, and connected via a large land more than twice those of the diameter, and a solid-like wiring layer through the gap around the該Ra down soil By stacking the upper and lower two green sheets so as to be positioned, the first laminated body composed of the upper pair and the conductor density is relatively high, and the second laminate composed of the lower pair and the conductor density is relatively low. A step of forming a green sheet laminate having a laminate, and a step of firing the green sheet laminate .

これによれば、追って相対的に導体密度が高くなる上側の組のグリーンシートには大きな割掛け率に従ってビアホールを形成し、下側の組のグリーンシートには小さな割掛け率に従ってビアホールを形成している。これら上下の組を積層したグリーンシート積層体を形成した際に、上側の組のビア導体と下側の組のビア導体とは、比較的大径の前記ランドを介して確実に接続される。このため、かかるグリーンシート積層体を焼成しても、焼成収縮が比較的大きい第1積層体側のビア導体と、焼成収縮が比較的小さい第2積層体側のビア導体とは、上記ランドに接続した状態で焼成される。この結果、従来のように、第1積層体および第2積層体となる各グリーンシートに同じ割り掛け率を適用していた場合に比べ、第1積層体および第2積層体側の何れかのビア導体とランドとが外れるおそれが皆無となる。更に、第1積層体側のビア導体は、その表面に追って形成されるパッドの直下に位置している。従って、第1積層体の表面上に搭載した被検査電子部品に通電したり、かかる電子部品の検査情報を正確に収集できる電子部品検査用配線基板を確実に提供することが可能となる。
According to this, via holes are formed in the upper set of green sheets, whose conductor density will be relatively higher, in accordance with a large allocation rate, and via holes are formed in the lower set of green sheets in accordance with a small allocation rate. ing. When a green sheet laminate is formed by laminating these upper and lower sets, the upper set of via conductors and the lower set of via conductors are securely connected via the land having a relatively large diameter. For this reason, even if the green sheet laminate is fired, the via conductor on the first laminate side with relatively large firing shrinkage and the via conductor on the second laminate side with relatively little firing shrinkage are connected to the land. Baked in the state. As a result, as compared with the conventional case where the same allocation rate is applied to the green sheets that are the first laminated body and the second laminated body, either via on the first laminated body side or the second laminated body side. There is no risk of the conductor and land coming off. Furthermore, the via conductor on the first laminated body side is located immediately below a pad formed on the surface thereof. Therefore, it is possible to reliably provide an electronic component inspection wiring board capable of energizing an electronic component to be inspected mounted on the surface of the first laminated body and accurately collecting inspection information of the electronic component.

尚、前記割掛け率とは、同じ2点間について、焼成前のグリーンシートにおける長さを、焼成後のセラミック層における長さで、除した(割り算:焼成前の長さ/焼成後の長さ)値を指す。通常、割掛け率は、約1.1〜1.2程度である。また、前記大小の割掛け率の差は、約0.001〜0.003の範囲である。かかる範囲とすることで、上・下側の組のグリーンシートを積層し、これらを同時に焼成した後に、表層に形成されたパッド、もしくは内部のビア導体の位置や寸法を、設定値に近付けることが可能となる。   In addition, the said dividing rate is the same between the two points, and the length in the green sheet before firing is divided by the length in the ceramic layer after firing (division: length before firing / length after firing). I) Value. Usually, the multiplication rate is about 1.1 to 1.2. The difference between the large and small percentages is in the range of about 0.001 to 0.003. By setting this range, the upper and lower groups of green sheets are stacked and fired at the same time, and then the positions and dimensions of the pads formed on the surface layer or the internal via conductors are brought closer to the set values. Is possible.

付言すれば、前記割り掛け率の異なる複数のグリーンシートを積層して得られるグリーンシート積層体を焼成する工程と、かかる焼成により得られた複数のセラミック層からなる第1積層体の表層に露出する焼成済みである複数のビア導体の上方に、それぞれパッドを形成する工程と、を有する、電子部品検査用配線基板の製造方法も本発明に含まれ得る。
これによる場合、上記パッドに被検査電子部品の電極を接続した際に、第1・第2積層体側の各ビア導体、およびこれに確実に接続した前記ランドを介して、上記電子部品の検査情報を正確に収集できる電子部品検査用配線基板を、確実に製造することが可能となる。
In other words, the step of firing a green sheet laminate obtained by laminating a plurality of green sheets having different percentages, and the surface layer of the first laminate comprising a plurality of ceramic layers obtained by the firing are exposed. A method of manufacturing a wiring board for inspecting electronic components, which includes a step of forming a pad above each of the plurality of via conductors that have been fired, can be included in the present invention.
In this case, when the electrode of the electronic component to be inspected is connected to the pad, the inspection information of the electronic component is passed through the via conductors on the first and second laminated bodies side and the land securely connected thereto. It is possible to reliably manufacture a wiring board for inspecting electronic components, which can be collected accurately.

以下において、本発明を実施するための最良の形態について説明する。
図1は、本発明における一形態の電子部品検査用配線基板(以下、単に検査用配線基板と称する)1を示す垂直断面図である。
かかる検査用配線基板1は、平面視が矩形(正方形または長方形)を呈し、図1に示すように、複数のセラミック層s1〜s3からなり、表面2および裏面3を有する第1積層体C1と、その裏面3側に積層され、且つ上記と同じ材料組成からなる複数のセラミック層s4〜s6からなり、表面4および裏面5を有する第2積層体C2と、を備えている。上記セラミック層s1〜s6は、同じ材料組成のアルミナなどからなる。
図1に示すように、第1積層体C1は、上記セラミック層s1〜s3間に形成された配線層7,8、表面2に形成された複数のパッド6、および表・裏面2,3間を導通する複数ビア導体vを有している。第2積層体C2は、表面4に形成された配線層。ランド10、および上記セラミック層s4〜s6の厚み方向に沿って貫通する複数のビア導体Vを有している。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a vertical sectional view showing an electronic component inspection wiring board (hereinafter simply referred to as an inspection wiring board) 1 according to an embodiment of the present invention.
The wiring board for inspection 1 has a rectangular shape (square or rectangular) in plan view, and includes a first laminate C1 having a plurality of ceramic layers s1 to s3 and having a front surface 2 and a back surface 3, as shown in FIG. The second laminated body C2 is formed of a plurality of ceramic layers s4 to s6 laminated on the back surface 3 side and made of the same material composition as described above, and has a front surface 4 and a back surface 5. The ceramic layers s1 to s6 are made of alumina having the same material composition.
As shown in FIG. 1, the first laminate C1 includes wiring layers 7 and 8 formed between the ceramic layers s1 to s3, a plurality of pads 6 formed on the front surface 2, and the front and back surfaces 2 and 3 And a plurality of via conductors v that conducts. The second stacked body C2 is a wiring layer formed on the surface 4. The land 10 and a plurality of via conductors V penetrating along the thickness direction of the ceramic layers s4 to s6 are provided.

第1積層体C1において、最上層のセラミック層s1の表面2の中央付近には、複数のパッド6が形成されている。かかる複数のパッド6は、被検査電子部品を搭載する搭載エリアa内に密集して配設され、被検査電子部品の電極と個別に接触して、かかる電子部品の性能を検査するために用いられる。
また、配線層7,8は、WまたはMoからなり且つ所定のパターンを有すると共に、セラミック層s1〜s3を貫通するビア導体vを介して、互いに導通し且つ上記パッド6とも導通可能とされている。最下層セラミック層s3を貫通するビア導体vは、第1積層体Cの裏面3側に露出している。上記各ビア導体vも、WまたはMoからなる。
In the first laminate C1, a plurality of pads 6 are formed near the center of the surface 2 of the uppermost ceramic layer s1. The plurality of pads 6 are densely arranged in the mounting area “a” on which the electronic components to be inspected are mounted, and are used to inspect the performance of the electronic components by individually contacting the electrodes of the electronic components to be inspected. It is done.
The wiring layers 7 and 8 are made of W or Mo and have a predetermined pattern. The wiring layers 7 and 8 are electrically connected to each other through the via conductors v penetrating the ceramic layers s1 to s3 and can be electrically connected to the pad 6. Yes. The via conductor v penetrating the lowermost ceramic layer s3 is exposed on the back surface 3 side of the first stacked body C. Each via conductor v is also made of W or Mo.

第2積層体C2において、最上層のセラミック層s4の表面4には、図2の水平部分断面図で示すように、例えば、接地層または電源層となるベタ状の配線層9と、平面視が円環形を呈する複数の隙間cごとの内側に形成された平面視が円形のランド10とが、同一平面において形成されている。上記配線層9と各ランド10もWまたはMoからなり、隙間cおよびランド10は、配線層9内に平面視で格子状に配設されている。
図1に示すように、前記第1積層体C1の裏面3側に露出するビア導体vは、上記ランド10の上面に接続されている。また、複数のランド10は、第2積層体C2のセラミック層s4〜s6を貫通する複数の長いビア導体Vを介して、第2積層体C2の裏面5に形成された複数の裏面側パッド11と個別に導通されている。
前記第1積層体C1と第2積層体C2とでは、前者のパッド6、配線層7,8、およびビア導体vからなる導体の単位体積当たりの密度が、後者の配線層9、ランド10、ビア導体V、および裏面側パッド11からなる導体の単位体積当たりの密度よりも、高くなっている。
尚、長いビア導体Vと裏面側パッド11も、WまたはMoからなる。また、裏面側パッド11は、パッド6、ランド10、およびビア導体v,Vを介して送信された被検査電子部品の検査情報を、外部の電子機器に出力するものである。
In the second laminated body C2, the surface 4 of the uppermost ceramic layer s4 has, for example, a solid wiring layer 9 serving as a ground layer or a power supply layer and a plan view as shown in the horizontal partial sectional view of FIG. A land 10 having a circular shape in plan view formed on the inner side of each of the plurality of gaps c having an annular shape is formed on the same plane. The wiring layer 9 and each land 10 are also made of W or Mo, and the gaps c and lands 10 are arranged in a lattice shape in the wiring layer 9 in plan view.
As shown in FIG. 1, the via conductor v exposed on the back surface 3 side of the first stacked body C <b> 1 is connected to the upper surface of the land 10. In addition, the plurality of lands 10 includes a plurality of back surface side pads 11 formed on the back surface 5 of the second stacked body C2 through a plurality of long via conductors V penetrating the ceramic layers s4 to s6 of the second stacked body C2. And are individually conducted.
In the first laminated body C1 and the second laminated body C2, the density per unit volume of the former pad 6, the wiring layers 7 and 8, and the conductor composed of the via conductors v is the latter wiring layer 9, land 10, The density per unit volume of the conductor composed of the via conductor V and the back surface side pad 11 is higher.
The long via conductor V and the back surface side pad 11 are also made of W or Mo. The back surface side pad 11 outputs inspection information of the electronic component to be inspected transmitted via the pad 6, the land 10, and the via conductors v and V to an external electronic device.

図3の部分拡大図で示すように、各ランド10の直径d1は、第1積層体C1側の前記ビア導体vの直径d2、および第2積層体C2を貫通する長いビア導体Vの直径d2に対し、それらの2〜5倍とされている。
以上のような検査用配線基板1によれば、第1積層体C1の裏面3側に露出するビア導体vと第2積層体C2の表面4に露出する長いビア導体Vとが、前記ランド10を介して確実に接続されている。このため、表面2側のパット6と裏面5側の裏面側パッド11とを、ランド10およびビア導体v,Vを介して確実に導通可能となる。従って、第1積層体C1の表面2に形成したパッド6上に搭載したICチップなどの被検査電子部品に通電したり、かかる電子部品の検査情報を正確に収集することが可能となる。
As shown in the partially enlarged view of FIG. 3, the diameter d1 of each land 10 is equal to the diameter d2 of the via conductor v on the first stacked body C1 side and the diameter d2 of the long via conductor V penetrating the second stacked body C2. On the other hand, it is 2-5 times those.
According to the inspection wiring substrate 1 as described above, the via conductor v exposed on the back surface 3 side of the first multilayer body C1 and the long via conductor V exposed on the front surface 4 of the second multilayer body C2 are formed by the land 10. It is securely connected via For this reason, the pad 6 on the front surface 2 side and the back surface side pad 11 on the back surface 5 side can be reliably conducted via the land 10 and the via conductors v and V. Therefore, it becomes possible to energize the electronic components to be inspected such as IC chips mounted on the pads 6 formed on the surface 2 of the first laminate C1, and to accurately collect the inspection information of the electronic components.

前記のような検査用配線基板1は、次のようにして製造した。
同種のアルミナ粉末、有機バインダ、溶剤などを同量ずつ配合して、同じ材料組成のセラミックスラリーを作り、ドクターブレード法によって、図4に示すように、6枚のグリーンシートg1〜g6を製作した。
図4において、上側のグリーンシートg1〜g3は、各々厚みが約180〜300μmで、且つ追って前記第1積層体C1のセラミック層s1〜s3となり、下側のグリーンシートg4〜g6は、各々厚みが約180〜516μmで、且つ追って前記第2積層体C2のセラミック層s4〜s6となる。
上側のグリーンシートg1〜g3(組)に対し、それぞれ割掛け率を1.2として、図4に示すように、複数のビアホールhを、打ち抜き加工で所定の位置に形成した。また、下側のグリーンシートg4〜g6(組)に対し、それぞれ割掛け率を1.198として、上記と同様に、複数のビアホールhを所定の位置に形成した(ビアホール形成工程)。
The inspection wiring board 1 as described above was manufactured as follows.
The same kind of alumina powder, organic binder, solvent and the like are blended in the same amount to make a ceramic slurry having the same material composition, and six green sheets g1 to g6 are produced by the doctor blade method as shown in FIG. .
In FIG. 4, the upper green sheets g1 to g3 each have a thickness of about 180 to 300 μm and later become the ceramic layers s1 to s3 of the first laminate C1, and the lower green sheets g4 to g6 each have a thickness. Is about 180 to 516 μm, and later become ceramic layers s4 to s6 of the second laminate C2.
With respect to the upper green sheets g1 to g3 (sets), each of the multiplying rates was 1.2, and a plurality of via holes h were formed at predetermined positions by punching as shown in FIG. In addition, the lower green sheets g4 to g6 (group) were each set at a rate of 1.198, and a plurality of via holes h were formed at predetermined positions in the same manner as described above (via hole forming step).

次に、グリーンシートg1〜g6ごとの各ビアホールh内に、W粉末を含む導電性ペーストをメタルマスクおよびスキージ(何れも図示せず)を用いて充填した。その結果、図5に示すように、グリーンシートg1〜g6ごとの各ビアホールh内に、未焼成のビア導体vが形成された(ビア導体形成工程)。
次いで、グリーンシートg2〜g4の表面、およびグリーンシートg6の裏面5に、上記同様の導電性ペーストをスクリーン印刷によって、図5に示すように、それぞれ所定パターンを有する未焼成の配線層7〜9、ランド10、および裏面側パッド11を形成した(配線層形成工程)。このうち、グリーンシートg4の表面4には、かかる表面4のほぼ全面をベタ状に覆う配線層9が形成されると共に、平面視で格子状に形成された円環形状を呈する複数の隙間cごとの内側に、円形のランド10を配線層9と同一平面において形成した。かかるランド10の直径(d1)は、図5で上方および下方に位置する各ビア導体vの直径(d2)の2〜5倍となるように設定した。
尚、前記配線層9および複数のランド10は、追って第1積層体C1の裏面3となるグリーンシートg3の裏面3側に形成しても良い。この場合、前記割掛け率の差は、例えば、0.003に大きくする。
Next, each of the via holes h for each of the green sheets g1 to g6 was filled with a conductive paste containing W powder using a metal mask and a squeegee (both not shown). As a result, as shown in FIG. 5, an unfired via conductor v was formed in each via hole h for each of the green sheets g1 to g6 (via conductor forming step).
Next, the same conductive paste as described above is applied to the front surface of the green sheets g2 to g4 and the back surface 5 of the green sheet g6 by screen printing, as shown in FIG. 5, and unfired wiring layers 7 to 9 each having a predetermined pattern. Then, the land 10 and the back surface side pad 11 were formed (wiring layer forming step). Among these, on the surface 4 of the green sheet g4, a wiring layer 9 that covers almost the entire surface 4 in a solid shape is formed, and a plurality of gaps c exhibiting an annular shape formed in a lattice shape in plan view. A circular land 10 was formed in the same plane as the wiring layer 9 on the inner side. The diameter (d1) of the land 10 was set to be 2 to 5 times the diameter (d2) of each via conductor v located above and below in FIG.
The wiring layer 9 and the plurality of lands 10 may be formed on the back surface 3 side of the green sheet g3, which will be the back surface 3 of the first stacked body C1 later. In this case, the difference in the multiplication rate is increased to, for example, 0.003.

更に、図5で上側のグリーンシートg1〜g3(組)と下側のグリーンシートg4〜g6(組)とを、前者で最下層のグリーンシートg3の裏面3に露出する複数のビア導体vが、後者で最上層のグリーンシートg4の表面4に位置する複数のランド10の上面に接触するように、グリーンシートg1〜g6を厚み方向に沿って加圧しつつ積層した。
その結果、図6に示すように、グリーンシートg1〜g3からなる第1積層体C1とグリーンシートg4〜g6からなる第2積層体C2とが積層され、且つ両者のビア導体vがランド10に接続されたグリーンシート積層体GSが形成された(積層工程)。かかるグリーンシート積層体GSを、所定の温度帯に加熱して(同時)焼成した(焼成工程)。
Further, in FIG. 5, the upper green sheets g1 to g3 (group) and the lower green sheets g4 to g6 (group) are connected to the former and the plurality of via conductors v exposed on the back surface 3 of the lowermost green sheet g3. In the latter case, the green sheets g1 to g6 were laminated while being pressed along the thickness direction so as to be in contact with the upper surfaces of the plurality of lands 10 located on the surface 4 of the uppermost green sheet g4.
As a result, as shown in FIG. 6, the first laminated body C1 made of green sheets g1 to g3 and the second laminated body C2 made of green sheets g4 to g6 are laminated, and the via conductors v of both are formed on the land 10. The connected green sheet laminated body GS was formed (lamination process). The green sheet laminate GS was heated to a predetermined temperature range (simultaneously) and fired (firing step).

その結果、図7に示すように、表面2および裏面5を有し且つ一体となったセラミック層s1〜s6からなる第1・第2積層体C1,C2、焼成された配線層7〜9、ビア導体v,V、ランド10、および、裏面側パッド11を備えたセラミック積層体SSが得られた。
前記焼成工程において、グリーンシート積層体GSで上層側の組のグリーンシートg1〜g3は、比較的高い密度の配線層7,8を有するため、前記割掛け率:1.2に従って、平面方向および厚み方向に沿って比較的大きく焼成収縮した。一方、下層側の組のグリーンシートg4〜g6は、ベタ状の配線層9、ランド10、および裏面側パッド11を除くと、複数の長いビア導体Vを比較的低密度で有するため、前記割掛け率:1.198に従って、平面方向および厚み方向に沿って比較的小さな焼成収縮に留まった。
As a result, as shown in FIG. 7, the first and second laminated bodies C1 and C2 made of ceramic layers s1 to s6 having the front surface 2 and the back surface 5 and integrated, the fired wiring layers 7 to 9, A ceramic laminate SS including the via conductors v and V, the land 10 and the back surface side pad 11 was obtained.
In the firing step, the green sheets g1 to g3 on the upper layer side of the green sheet laminate GS have the wiring layers 7 and 8 having a relatively high density. Firing shrinkage was relatively large along the thickness direction. On the other hand, since the green sheets g4 to g6 in the lower layer side have a plurality of long via conductors V at a relatively low density except for the solid wiring layer 9, the land 10, and the back surface side pad 11, According to the multiplying factor: 1.198, the firing shrinkage remained relatively small along the plane direction and the thickness direction.

第1積層体C1と第2積層体C2との焼成収縮には差があるため、それぞれに応じて異なる前記割掛け率を適用しても、グリーンシートg4の表面4に形成された各ランド10の直径(d1)を、グリーンシートg3の裏面3に露出する各ビア導体vの直径(d2)の2〜5倍に設定していたため、かかるランド10とビア導体vとの接続を確実に保つことができた。
その結果、図7に示すように、セラミック積層体SSでは、配線層7,8と各ランド10とが、セラミックs1〜s3を貫通する各ビア導体vを介して、導通可能とされ、各ランド10と裏面側パッド11とが、セラミックs4〜s6を貫通する長いビア導体Vを介して、導通可能とされていた。
Since there is a difference in firing shrinkage between the first laminated body C1 and the second laminated body C2, each land 10 formed on the surface 4 of the green sheet g4 is applied even if the above-mentioned different percentages are applied. Is set to 2 to 5 times the diameter (d2) of each via conductor v exposed on the back surface 3 of the green sheet g3, so that the connection between the land 10 and the via conductor v is reliably maintained. I was able to.
As a result, as shown in FIG. 7, in the ceramic laminate SS, the wiring layers 7 and 8 and the lands 10 can be conducted through the via conductors v penetrating the ceramics s1 to s3. 10 and the back surface side pad 11 can be conducted through a long via conductor V penetrating the ceramics s4 to s6.

次に、セラミック積層体SS(セラミック層s1)の表面2の中央部に露出する複数のビア導体vごとの上に、被検査電子部品と接触するパッド(6)を次のようにして形成した。
図8の左側に示すように、セラミック層s1の表面2上に、Ti薄膜層12とCu薄膜層13とを順次スパッタリングによって形成した。次いで、図8の右側に示すように、上記Cu薄膜層13の上に感光性樹脂からなるレジスト層14を形成した後、かかるレジスト層14に対しフォトリソグラフィー技術を施すことによって、ビア導体vごとの上方に円柱形の貫通孔15を形成した。
次に、図9の左側に示すように、各貫通孔15の底面に露出するCu薄膜層13の上に、電解メッキによって、Cuメッキ層16とNiメッキ層17とを、順次形成した。かかる状態で、図9の右側に示すように、上記レジスト層14を現像液によって溶解・除去した。
Next, a pad (6) in contact with the electronic component to be inspected is formed on each of the plurality of via conductors v exposed at the center of the surface 2 of the ceramic laminate SS (ceramic layer s1) as follows. .
As shown on the left side of FIG. 8, a Ti thin film layer 12 and a Cu thin film layer 13 were sequentially formed on the surface 2 of the ceramic layer s1 by sputtering. Next, as shown on the right side of FIG. 8, after forming a resist layer 14 made of a photosensitive resin on the Cu thin film layer 13, a photolithography technique is applied to the resist layer 14, so that each via conductor v is formed. A cylindrical through-hole 15 was formed above the top.
Next, as shown on the left side of FIG. 9, a Cu plating layer 16 and a Ni plating layer 17 were sequentially formed on the Cu thin film layer 13 exposed on the bottom surface of each through hole 15 by electrolytic plating. In this state, as shown on the right side of FIG. 9, the resist layer 14 was dissolved and removed with a developer.

更に、図10の左側に示すように、Cuメッキ層16とNiメッキ層17とに覆われていない部分のTi薄膜層12とCu薄膜層13とを、エッチング液に接触させることによって除去した。その結果、表面2に露出するビア導体vごとの上方に、Ti薄膜層12、Cu薄膜層13、Cuメッキ層16、およびNiメッキ層17の4層が円柱形にして形成された。そして、かかる4層からなる円柱体の全表面に対し、図10の右側に示すように、電解メッキによってAuメッキ層mを被覆した。これにより、複数のパッド6を位置精度良く表面2に形成できた。
その結果、被検査電子部品の電極と接触するための複数のパッド6が表面2の搭載エリアaに形成され、かかるパット6および裏面側パッド11を、前記ランド10を介して確実に導通可能とされた前記図1に示す検査用配線基板1を得ることができた。
Further, as shown on the left side of FIG. 10, the portions of the Ti thin film layer 12 and the Cu thin film layer 13 that are not covered with the Cu plating layer 16 and the Ni plating layer 17 were removed by contacting them with an etching solution. As a result, four layers of the Ti thin film layer 12, the Cu thin film layer 13, the Cu plating layer 16, and the Ni plating layer 17 were formed in a cylindrical shape above each via conductor v exposed on the surface 2. Then, as shown on the right side of FIG. 10, the Au plating layer m was coated on the entire surface of the four-layered cylindrical body by electrolytic plating. As a result, the plurality of pads 6 could be formed on the surface 2 with high positional accuracy.
As a result, a plurality of pads 6 for contacting the electrodes of the electronic component to be inspected are formed in the mounting area a of the front surface 2, and the pads 6 and the back surface side pads 11 can be reliably conducted via the land 10. Thus, the inspection wiring board 1 shown in FIG. 1 was obtained.

以上のような検査用配線基板1の製造方法によれば、前記上側の組のグリーンシートg1〜g3には大きな割掛け率に従ってビアホールhを形成し、前記下側の組のグリーンシートg4〜g6には小さな割掛け率に従った位置にビアホールhを形成し、且つ各ランド10の直径d1を、グリーンシートg3の裏面3に露出する各ビア導体vの直径d2の2〜5倍にしている。このため、2つのビア導体v,Vおよびパッド6の位置精度が向上すると共に、かかる2つのビア導体v,Vは、焼成された前記ランド10を介して確実に接続される。従って、第1積層体C1の表面2上に形成したパッド6上に搭載した被検査電子部品に通電したり、かかる電子部品の検査情報を、ランド10やビア導体v,Vなどを介して、裏面側パッド11から正確に収集できる検査用配線基板1を確実に提供することができた。   According to the manufacturing method of the inspection wiring board 1 as described above, via holes h are formed in the upper set of green sheets g1 to g3 in accordance with a large percentage, and the lower set of green sheets g4 to g6. The via hole h is formed at a position according to a small percentage, and the diameter d1 of each land 10 is 2 to 5 times the diameter d2 of each via conductor v exposed on the back surface 3 of the green sheet g3. . For this reason, the positional accuracy of the two via conductors v and V and the pad 6 is improved, and the two via conductors v and V are reliably connected via the baked land 10. Accordingly, the electronic component to be inspected mounted on the pad 6 formed on the surface 2 of the first laminated body C1 is energized, and the inspection information of the electronic component is transmitted via the land 10 and the via conductors v and V. It was possible to reliably provide the inspection wiring board 1 that can be accurately collected from the back-side pad 11.

図11は、参考形態の検査用配線基板1aを示す垂直断面図である。
かかる検査用配線基板1aは、図11に示すように、前記検査用配線基板1と同様な第1積層体C1および第2積層体C2を一体に積層したものである。
検査用配線基板1aが前記検査用配線基板1と相違する点は、第1積層体C1の裏面3と第2積層体C2の表面4との間に、前記同様に複数のランド10が格子状に配置され、これらの間に信号用である細い線状の配線層9aが同じ平面において配置されていることである。複数のランド10の上下には、第1積層体C1側のビア導体vと第2積層体C2側の長いビア導体Vとが接続されている。各ランド10の直径d1は、上下の各ビア導体v,Vの直径d2の2〜5倍である。
FIG. 11 is a vertical sectional view showing the inspection wiring board 1a of the reference form .
As shown in FIG. 11, the inspection wiring board 1a is formed by integrally laminating a first laminated body C1 and a second laminated body C2 similar to the inspection wiring board 1.
The inspection wiring board 1a is different from the inspection wiring board 1 in that a plurality of lands 10 are formed in a lattice shape between the back surface 3 of the first stacked body C1 and the front surface 4 of the second stacked body C2. The thin linear wiring layers 9a for signals are arranged in the same plane between them. A via conductor v on the first stacked body C1 side and a long via conductor V on the second stacked body C2 side are connected above and below the plurality of lands 10. The diameter d1 of each land 10 is 2 to 5 times the diameter d2 of the upper and lower via conductors v and V.

前記検査用配線基板1aは、前記検査用配線基板1と同様にして製造できるが、前記第2積層体C2の表面4には、信号用の配線層9aとなる線状の導電性ペーストが形成される。この結果、グリーンシートg1〜g3から形成される第1積層体C1とグリーンシートg4〜g6から形成される第2積層体C2との焼成時における焼成収縮の差が、前記検査用配線基板1を製造する場合よりも若干大きくなる。このため、前記上側の組のグリーンシートg1〜g3の割掛け率に対し、下側の組のグリーンシートg4〜g6の割掛け率を、例えば、約0.003程度小さくするか、あるいは、大きくして前記ビアホールhを形成することが望ましい。尚、前記配線層9aの導電性ペーストを、第1積層体C1の裏面3となるグリーンシートg3の裏面3に形成しても良い。
以上のような検査用配線基板1aによっても、前記検査用配線基板1と同様な作用が得られ、且つ同様な効果を奏することが可能である。
The inspection wiring board 1a can be manufactured in the same manner as the inspection wiring board 1. However, a linear conductive paste that forms the signal wiring layer 9a is formed on the surface 4 of the second laminate C2. Is done. As a result, the difference in firing shrinkage during firing between the first laminate C1 formed from the green sheets g1 to g3 and the second laminate C2 formed from the green sheets g4 to g6 It is slightly larger than the case of manufacturing. For this reason, for example, the lowering rate of the green sheets g4 to g6 in the lower group is reduced by about 0.003 or larger than that of the upper side green sheets g1 to g3. It is desirable to form the via hole h. In addition, you may form the electrically conductive paste of the said wiring layer 9a in the back surface 3 of the green sheet g3 used as the back surface 3 of the 1st laminated body C1.
Even with the above-described wiring board for inspection 1a, the same operation as that of the wiring board for inspection 1 can be obtained, and the same effect can be obtained.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記第1積層体と第2積層体とを形成するためのセラミック層およびグリーンシートは、互いに同じ材料組成ないし成分組成のセラミック材料であれば良く、窒化アルミニウムやムライトなどの高温焼成セラミックや、ガラス−セラミック(例えば、アルミナ)などの低高温焼成セラミックとしても良い。
また、前記第1積層体の裏面と第2積層体の表面との間に形成される複数のランドは、平面視で千鳥状に配設した形態としても良い。
更に、上記ランドは、平面視でほぼ正方形や正多角形を呈する形態としても良く、これらの場合には、平面視で最短の距離が前記直径とされる。
The present invention is not limited to the embodiments described above.
For example, the ceramic layer and the green sheet for forming the first laminate and the second laminate may be ceramic materials having the same material composition or component composition, such as high-temperature fired ceramics such as aluminum nitride and mullite, Alternatively, a low-temperature fired ceramic such as glass-ceramic (for example, alumina) may be used.
The plurality of lands formed between the back surface of the first stacked body and the front surface of the second stacked body may be arranged in a staggered manner in a plan view.
Further, the land may have a substantially square or regular polygonal shape in plan view, and in these cases, the shortest distance in plan view is the diameter.

本発明の一形態の電子部品検査用配線基板を示す垂直断面図。1 is a vertical cross-sectional view illustrating an electronic component inspection wiring board according to an embodiment of the present invention. 上記検査用配線基板におけるランド付近を示す水平部分断面図。The horizontal fragmentary sectional view which shows the land vicinity in the said wiring board for an inspection. 上記ランド付近を示す部分拡大断面図。The partial expanded sectional view which shows the said land vicinity. 上記検査用配線基板の一製造工程を示す概略図。Schematic which shows one manufacturing process of the said wiring board for an inspection. 図4に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図5に続く製造工程で得られたグリーンシート積層体を示す概略図。Schematic which shows the green sheet laminated body obtained at the manufacturing process following FIG. 図6に続く製造工程で得られたセラミック積層体を示す概略図。Schematic which shows the ceramic laminated body obtained at the manufacturing process following FIG. 図7に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図8に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図9に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 参考形態の電子部品検査用配線基板を示す垂直断面図。 The vertical sectional view which shows the wiring board for electronic component inspection of a reference form .

符号の説明Explanation of symbols

1………………電子部品検査用配線基板
2,4…………表面
3,5…………裏面
6………………パッド
7〜9…………配線層
10……………ランド
C1……………第1積層体
C2……………第2積層体
s1〜s6……セラミック層
v,V…………ビア導体
d1,d2……直径
g1〜g6……グリーンシート
h………………ビアホール
GS……………グリーンシート積層体
1 ... ............... electronic component test wiring substrates 2 ............ surface 3,5 ............ backside 6 .................. pad 7-9 ... ......... wiring layer 10 ......... …… Land C1 ……………… First laminate C2 ………… Second laminate s1 to s6 …… Ceramic layers v, V ………… Via conductors d1, d2 …… Diameter g1 to g6 …… Green sheet h ……………… via hole GS …………… green sheet laminate

Claims (2)

複数のセラミック層からなり、表面に形成され複数のパッド、前記セラミック層間に形成された配線層、および上記パッドと配線層と裏面との間を接続する複数のビア導体を有する第1積層体と、
上記セラミック層と同じ材料組成で且つ複数のセラミック層からなり、表面と裏面との間を貫通する複数のビア導体を有し、上記第1積層体の裏面側に積層された第2積層体と、を備え、
上記第1積層体の導体密度は、第2積層体の導体密度に比べて、高密度であり
上記両積層体の焼成収縮率が相違することに対応して、該第1積層体と第2積層体とを製造する際の両積層体の割掛け率を相違させており
上記第1積層体と第2積層体との間には、第1積層体の裏面に露出するビア導体と第2積層体の表面に露出するビア導体とを接続する複数のランド、およびかかるランドの周りに隙間を介して位置するベタ状の配線層が配置されており、
上記ランドの直径は、上記2つのビア導体の直径の2〜5倍である、
ことを特徴とする電子部品検査用配線基板。
A first laminate comprising a plurality of ceramic layers, a plurality of pads formed on the surface, a wiring layer formed between the ceramic layers, and a plurality of via conductors connecting between the pads and the wiring layers and the back surface; ,
A second laminated body having the same material composition as the ceramic layer and comprising a plurality of ceramic layers, having a plurality of via conductors penetrating between the front surface and the back surface, and laminated on the back surface side of the first laminated body; With
The conductor density of the first laminate is higher than the conductor density of the second laminate ,
Corresponding to the difference between the firing shrinkage rates of the two laminates, the percentages of the laminates when producing the first laminate and the second laminate are different ,
Between the first laminate and the second laminate, a plurality of lands connecting the via conductor exposed on the back surface of the first laminate and the via conductor exposed on the surface of the second laminate, and the land A solid wiring layer located around the gap is arranged,
The diameter of the land is 2 to 5 times the diameter of the two via conductors.
A wiring board for inspecting electronic components.
上下2組で且つ同じ材料組成のセラミックからなる複数ずつのグリーンシートに対し、上側の組の各グリーンシートには相対的に大きな割掛け率に従った位置に複数のビアホールを形成すると共に、下側の組の各グリーンシートには相対的に小さな割掛け率に従った位置に複数のビアホールを形成する工程と、
上記ビアホールごとに金属粉末を含む導電性ペーストを充填してビア導体を形成する工程と、
上記上側の組における複数のグリーンシートの表面および裏面の少なくとも一方に上記同様の導電性ペーストからなる配線層を形成する工程と、
上記上側の組における最下層のグリーンシートの裏面と、下側の組における最上層のグリーンシートの表面との間において、前者の裏面と後者の表面とに露出するビア導体を、これらの直径よりも2倍以上大きなランドを介して接続し、且つ該ラドの周りに隙間を介してベタ状の配線層が位置するように、上下2組の各グリーンシートを積層することにより、上側の組からなり導体密度が相対的に高い第1積層体と下側の組からなり導体密度が相対的に低い第2積層体とを有するグリーンシート積層体を形成する工程と、
上記グリーンシート積層体を焼成する工程と、含む、
ことを特徴とする電子部品検査用配線基板の製造方法。
For each of the upper and lower sets of green sheets made of ceramics of the same material composition , a plurality of via holes are formed in the upper set of green sheets at positions according to a relatively large percentage. Forming a plurality of via holes at positions according to a relatively small percentage on each green sheet of the side set;
Filling a conductive paste containing metal powder for each via hole to form a via conductor;
Forming a wiring layer made of the same conductive paste on at least one of the front and back surfaces of the plurality of green sheets in the upper set;
Between the back surface of the lowermost green sheet in the upper set and the surface of the uppermost green sheet in the lower set, the via conductor exposed on the former back surface and the latter surface is determined from these diameters. also connects via a large land more than doubled, and through the gap around the該Ra down de to position solidly wiring layers, by laminating the upper and lower two sets of the green sheets, upper Forming a green sheet laminate having a first laminate comprising a set and a relatively high conductor density and a second laminate comprising a lower set and a relatively low conductor density;
Firing the green sheet laminate ,
A method for manufacturing an electronic component inspection wiring board.
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