JP5176995B2 - Manufacturing method of multilayer substrate for semiconductor package - Google Patents

Manufacturing method of multilayer substrate for semiconductor package Download PDF

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JP5176995B2
JP5176995B2 JP2009024076A JP2009024076A JP5176995B2 JP 5176995 B2 JP5176995 B2 JP 5176995B2 JP 2009024076 A JP2009024076 A JP 2009024076A JP 2009024076 A JP2009024076 A JP 2009024076A JP 5176995 B2 JP5176995 B2 JP 5176995B2
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multilayer substrate
semiconductor package
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健央 高田
直人 大野
功 加藤
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Toppan Inc
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Description

本発明は、半導体パッケージ用多層基板及びその製造方法に関し、特に、高信頼性、かつ配線密度を高くすることができる半導体パッケージ用多層基板及びその製造方法に関する。   The present invention relates to a multilayer substrate for a semiconductor package and a method for manufacturing the same, and more particularly to a multilayer substrate for a semiconductor package and a method for manufacturing the same that can increase the reliability and the wiring density.

近年、半導体素子をプリント配線基板に実装するためのインターポーザとして、多層回路基板が広く採用されている。この多層回路基板は表面に所定パターンの導体回路が形成された単位回路基板を複数枚積層して、各単位回路基板の間はスルーホールやビアホールで導通が取られている。   In recent years, multilayer circuit boards have been widely adopted as interposers for mounting semiconductor elements on printed wiring boards. The multilayer circuit board has a plurality of unit circuit boards each having a predetermined pattern of conductor circuits formed on the surface thereof, and the unit circuit boards are electrically connected by through holes or via holes.

その一方で、半導体大規模集積回路(LSI)等の半導体素子ではトランジスタの集積度が高まり、その動作速度はクロック周波数で1GHzに達するもの、入出力端子数では1000を越えるものが出現するに至っている。   On the other hand, in a semiconductor element such as a semiconductor large scale integrated circuit (LSI), the degree of integration of transistors is increased, and the operation speed reaches 1 GHz in the clock frequency, and the number of input / output terminals exceeds 1000. Yes.

このため、多層回路基板にも高密度、高精細の配線形成技術が求められている。半導体素子の小型化、高集積化等に対応するために、配線ピッチ及びビア径はより微細化される傾向にある。すなわち、半導体素子周辺部の信号配線領域におけるバンプ(信号バンプ)の形成ピッチが微細化されることで、信号バンプ間(パッケージ基板側ではビアランド間)に配線を通す必要が生じる。このため、信号配線を微細化すると同時に、ビア径を微細化することが求められている。特に、信号バンプの配列数の増加に伴って、信号バンプ間(パッケージ基板側ではビアランド間)に通す信号数が多くなってきていることから、信号系のビア径はより微細化(小径化)される傾向にある。   For this reason, a high-density, high-definition wiring formation technology is also required for multilayer circuit boards. In order to cope with downsizing and high integration of semiconductor elements, the wiring pitch and via diameter tend to be further miniaturized. That is, since the formation pitch of bumps (signal bumps) in the signal wiring region in the periphery of the semiconductor element is reduced, it is necessary to pass wiring between signal bumps (betland between package substrates). For this reason, it is required to reduce the via diameter at the same time as the signal wiring. In particular, as the number of signal bumps increases, the number of signals passed between signal bumps (betland on the package substrate side) has increased, so the signal system via diameter has become smaller (smaller). Tend to be.

特許文献1では、高周波領域でのノイズ低減のため、ビア周りのインダクタンスの低減が求められるており、スタックドビア(Stacked Via)構造を適用する技術が開示されている(例えば特許文献1参照)。   In Patent Document 1, in order to reduce noise in a high-frequency region, a reduction in inductance around a via is required, and a technique of applying a stacked via structure is disclosed (for example, refer to Patent Document 1).

スタックドビアは、ビアを直線的に複数段積み上げたものであり、配線距離を短縮することが可能であることから、インダクタンスを有効に低減することができる。しかし、スタックドビアは位置をずらして配置したスタガードビア(Staggered Via)に比べて応力が集中しやすいことから、パッケージ基板上に半導体素子を搭載する際に生じる熱応力や半導体素子の動作温度に基づく熱応力等によって、ビアの破断が発生しやすくなる。これは、ビア径の小径化に伴ってより顕著になってきており、高密度、高集積化の課題となっている。   In the stacked via, the vias are stacked in a plurality of stages and the wiring distance can be shortened, so that the inductance can be effectively reduced. However, stress is more concentrated in stacked vias than in staggered vias that are arranged at different positions. Therefore, thermal stress generated when a semiconductor element is mounted on a package substrate or heat based on the operating temperature of the semiconductor element. Via breakage is likely to occur due to stress or the like. This has become more conspicuous as the via diameter becomes smaller, and has become a subject of higher density and higher integration.

スタガードビアは、ビアを階段状に並べたものであり、ビア位置をずらした距離分、余計に配線が必要となることから、インダクタンスの増加が避けられず、配線の引き回しにスペースが必要であり、パーケージの高集積化、高密度化には不向きである。スタックドビア及びスタガードビアのような構造では、インダクタンスの低減及びビア周りの省スペース化と、信頼性の向上とがトレードオフの関係であり、両立する事は困難であった。   Staggered vias are a series of vias that are stepped and require extra wiring for the distance the via position is shifted, so an increase in inductance is unavoidable and space is required for routing the wiring. It is not suitable for high integration and high density packaging. In structures such as stacked vias and staggered vias, there is a trade-off between reducing inductance, saving space around the vias, and improving reliability, and it has been difficult to achieve both.

特開2003−264253号公報JP 2003-264253 A

本発明は、インダクタンスの増加を抑えたうえで、ビアの断線を抑制し信頼性の高い、高密度半導体パッケージ用多層基板及びその製造方法を提供することである。   An object of the present invention is to provide a highly reliable multi-layer substrate for a high-density semiconductor package and a method for manufacturing the same, which suppresses via disconnection and suppresses an increase in inductance.

本発明の請求項に係る発明は、それぞれが第1の面及び第2の面に配線層を有する複数の絶縁層を積層または貼り合わせる半導体パッケージ用多層基板の製造方法において、複数の絶縁層の第i層(i=n、n+1・・・n+k)の絶縁層の第1の面の配線層から第2の面の配線層に至る第iのビアを第i層の絶縁層中に形成し、第i+1層の絶縁層の第1の面の配線層から第2の面の配線層に至る第i+1のビアを第i+1層の絶縁層中に形成し、第iビアと第i+1ビアとの中心距離が、第iビアの半径と第i+1ビアの半径との合計よりも小さくかつ、10μm以上であることを特徴とする半導体パッケージ用多層基板の製造方法としたものである。 The invention according to claim 1 of the present invention, in each of the first surface and a method for manufacturing a multilayer substrate for a semiconductor package combining a plurality of insulating layers laminated or bonded to a second surface on the wiring layer, a plurality of insulating layers An i-th via extending from the wiring layer on the first surface to the wiring layer on the second surface of the i-th insulating layer (i = n, n + 1... N + k) is formed in the i-th insulating layer. Then, an i + 1th via extending from the wiring layer on the first surface of the i + 1th insulating layer to the wiring layer on the second surface is formed in the i + 1th insulating layer, and the ith and i + 1th vias are formed. The center distance of is smaller than the sum of the radius of the i-th via and the radius of the (i + 1) -th via and is 10 μm or more.

本発明の請求項に係る発明は、ビアの中心距離が、上面から見た場合に繰返し二点、正三角形の頂点及び正四角形の頂点を含む正多角形の頂点のいずれかであることを特徴とする請求項に記載の半導体パッケージ用多層基板の製造方法としたものである。 In the invention according to claim 2 of the present invention, when the via center distance is viewed from above, it is any one of a regular polygon vertex including two points repeatedly, a regular triangle vertex and a regular square vertex. The method of manufacturing a multilayer substrate for a semiconductor package according to claim 1 , wherein

本発明の請求項に係る発明は、正多角形の頂点数は、複数のビアの段数に応じて選択することを特徴とする請求項1または2に記載の半導体パッケージ用多層基板の製造方法としたものである。 Invention, the number of vertices regular polygon, a method of manufacturing a semiconductor package multilayer substrate according to claim 1 or 2, characterized in that selected depending on the number of the plurality of vias according to claim 3 of the present invention It is what.

本発明によれば、ビア周りの接続面積を最小限に抑え配線の引き回しを小さくすることにより、配線の高密度化とインダクタンスの低減を実現した上で、ビアに掛かる熱応力を低減し信頼性の高い半導体パッケージ用多層基板を及びその製造方法を提供することができる。   According to the present invention, by minimizing the connection area around the via and reducing the wiring routing, the wiring density is increased and the inductance is reduced, and the thermal stress applied to the via is reduced and the reliability is reduced. It is possible to provide a multilayer substrate for a semiconductor package having a high level and a manufacturing method thereof.

(a)本発明の実施の形態に係るビア部・ランド部の構成を示す概略図であり、(b)は比較用にビア部・ランド部の構成を示す概略図である。(A) It is the schematic which shows the structure of the via part and land part concerning embodiment of this invention, (b) is the schematic which shows the structure of a via part and land part for a comparison. 本発明の実施の形態に係るビア接続部を概念的に示す鳥瞰図である。It is a bird's-eye view which shows notionally a via connection part concerning an embodiment of the invention. 本発明の実施の形態に係るビア部・ランド部の上面透過図であり、(a)はビア位置を二点繰返しとした場合を示す図であり、(b)はビア位置を三点繰返しとした場合を示す図である。It is a top surface transparent view of the via portion and land portion according to the embodiment of the present invention, (a) is a diagram showing a case where the via position is repeated at two points, (b) is a three-point repeated via position. FIG. (a)〜(f)は本発明の実施の形態に係るビア接続部の構造とスタックドビア構造との場合で使用面積を比較したものを示す概略断面図である。(A)-(f) is a schematic sectional drawing which shows what compared the use area in the case of the structure of the via connection part which concerns on embodiment of this invention, and the stacked via structure. (a)〜(e)は本発明の実施の形態に係る半導体パッケージ用多層基板の工程を示す概略断面図である。(A)-(e) is a schematic sectional drawing which shows the process of the multilayer substrate for semiconductor packages which concerns on embodiment of this invention. (a)〜(e)は本発明の実施の形態に係る半導体パッケージ用多層基板の工程を示す概略断面図である。(A)-(e) is a schematic sectional drawing which shows the process of the multilayer substrate for semiconductor packages which concerns on embodiment of this invention. (a)は本発明の実施の形態に係るビア配置を二点繰返しとした場合を示すイメージ図であり、(b)はビア部の信号透過イメージを示す図である。(A) is an image figure which shows the case where the via | veer arrangement | positioning which concerns on embodiment of this invention is made to repeat 2 points | pieces, (b) is a figure which shows the signal permeation | transmission image of a via part. (a)本発明の実施の形態に係るビア配置を三点繰返しとした場合を示すイメージ図であり、(b)はビア部の信号透過イメージを示す図である。(A) It is an image figure which shows the case where the via | veer arrangement | positioning which concerns on embodiment of this invention is made to repeat 3 points | pieces, (b) is a figure which shows the signal permeation | transmission image of a via part. スタックドビア構造の多層配線板を示す概略断面図である。It is a schematic sectional drawing which shows the multilayer wiring board of a stacked via structure.

以下、本発明の実施の形態を、図面を参照しつつ、説明する。なお、本発明の実施の形態は以下の説明に限定されることなく、本発明の趣旨に基づき種々の変形を行っても構わない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment of the present invention is not limited to the following description, and various modifications may be made based on the gist of the present invention.

図1(a)に示すように、本発明の実施の形態に係る接続ビアの構造は、第nビアのボトム部の半径rと第n+1ビアのトップ部の半径rn+1の合計が、第nビアと第n+1ビアとの中心距離dよりも小さくなり、かつ、中心距離dの距離が10μm以上である(r+rn+1>d)。これにより、ビア近郊の配線エリア(ビアとランドとを含む)の面積が小さくなり、パターン縮小に伴う配線ピッチ等の縮小がある場合にも、配線の引き回しが容易になる。中心距離dの距離が10μm未満の場合、レーザ等によるビアの位置精度により、スタックドビア構造と同様な状態になる場合があり、応力の逃げが無くなってしまう。一方、図1(b)に示すように、スタガードビアの構造では、第nビアのボトム部の半径rと第n+1ビアのトップ部の半径rn+1の合計が、第nビアと第n+1ビアとの中心距離dよりも大きくなっている(r+rn+1<d)。 As shown in FIG. 1 (a), the structure of the connection vias according to an embodiment of the present invention, the sum of the radius r n + 1 of radius r n and the top portion of the n + 1 via the bottom portion of the n vias, the n smaller than the center distance d n between the via and the n + 1 via, and a distance center distance d n is 10μm or more (r n + r n + 1 > d n). As a result, the area of the wiring area in the vicinity of the via (including the via and the land) is reduced, and the wiring can be easily routed even when the wiring pitch is reduced due to the pattern reduction. If the distance of the center distance d n is less than 10 [mu] m, the positional accuracy of the via using a laser or the like, may result in similar conditions and stacked via structure, it disappears escapes stress. On the other hand, as shown in FIG. 1 (b), in the structure of Sutagadobia sum of the radius r n + 1 of the top portion of the radius r n and the n + 1 via the bottom portion of the n vias, the n via the first n + 1 via It is larger than the center distance d n between the (r n + r n + 1 <d n).

図2に示すように、本発明の実施の形態に係る接続ビアの構造は、ビア2の周辺にランド1を有し、ビア2の中心位置をわずかにずらしながら積層していくことで、配線層や絶縁層の熱膨張係数の違いによる熱応力の集中を効果的に抑えることができる。本発明の実施の形態に係る接続ビアの構造は、多層積層時の熱応力を有効に緩和することができるため、6層、8層、あるいはそれ以上と、積層数が増加するほど熱応力緩和の効果が大きくなる。一方、例えば、図9に示すように、スタックドビア構造の場合は、スタックドビア部分にて厚み方向に配線層が連続し、応力の逃げが無くビアの破断が発生しやすくなってしまう。   As shown in FIG. 2, the structure of the connection via according to the embodiment of the present invention has a land 1 around the via 2 and is laminated by slightly shifting the center position of the via 2. Concentration of thermal stress due to a difference in thermal expansion coefficient between layers and insulating layers can be effectively suppressed. Since the structure of the connection via according to the embodiment of the present invention can effectively relieve the thermal stress at the time of multilayer lamination, the thermal stress relaxation as the number of lamination increases as 6 layers, 8 layers or more. The effect of increases. On the other hand, for example, as shown in FIG. 9, in the case of the stacked via structure, the wiring layer is continuous in the thickness direction at the stacked via portion, there is no escape of stress, and the via breaks easily.

そこで、図6(e)に示すように、本発明の実施の形態に係る半導体パッケージ用多層基板は、多層積層する場合に繰返し同一点にビア位置を持ってくると、ビア接続に必要となる面積を効果的に低減することができる。   Therefore, as shown in FIG. 6 (e), the multilayer substrate for a semiconductor package according to the embodiment of the present invention is necessary for via connection when a via position is repeatedly provided at the same point in the case of multilayer lamination. The area can be effectively reduced.

本発明の実施の形態に係る半導体パッケージ用多層基板は、図3(a)に示す繰返し二点間または図3(b)に示す繰返し三点間の正三角形の頂点にビア接続を行うことによりビア接続に必要となる面積を効果的に低減することができる。   The multilayer substrate for a semiconductor package according to the embodiment of the present invention performs via connection at the apex of an equilateral triangle between two repeated points shown in FIG. 3 (a) or three repeated points shown in FIG. 3 (b). The area required for via connection can be effectively reduced.

また、本発明の実施の形態に係る半導体パッケージ用多層基板は、上述した正三角形の頂点にビア接続を行うだけでなく、正四角形、正五角形及び正六角形を含む正多角形の頂点にビア接続を行うことによりビア接続に必要となる面積を効果的に低減することができる。   In addition, the multilayer substrate for a semiconductor package according to the embodiment of the present invention not only performs via connection to the vertex of the regular triangle described above but also via connection to the vertex of a regular polygon including a regular square, a regular pentagon, and a regular hexagon. By performing this, the area required for via connection can be effectively reduced.

次に、本発明の実施の形態に係るビア接続の構造とスタガード構造とのビアの使用面積比について検討する。   Next, the via use area ratio between the via connection structure and the staggered structure according to the embodiment of the present invention will be examined.

図4(a)〜(c)は本発明の実施の形態に係るビア2の使用面積比を示し、図4(d)〜(f)はスタガードビア構造のビア2の使用面積比を示している。図4(a)〜(f)は、ビア2半径をr、ビア2とビア2との中心距離dをrとした時の、ビア周りの面積を近似外接円近似3で示したものである(ランド部除く、ビアのトップ部とビアのボトム部とは同一径として計算)。   4A to 4C show the usage area ratio of the via 2 according to the embodiment of the present invention, and FIGS. 4D to 4F show the usage area ratio of the via 2 having the staggered via structure. Yes. 4A to 4F show the area around the via in the approximate circumscribed circle approximation 3 when the radius of the via 2 is r and the center distance d between the via 2 and the via 2 is r. (Excluding the land part, the top part of the via and the bottom part of the via are calculated as the same diameter).

図4(a)に示すように、本発明の実施の形態に係る二点繰返しでは近似外接円直径d=3rとなり、図4(d)に示すスタガード構造では、近似外接円直径d’=4rとなり、本発明の実施の形態に係る二点繰返しの近似外接円直径dがスタガード構造と比較して、r1つ分減少し、面積が低減している。 As shown in FIG. 4A, the approximate circumscribed circle diameter d 2 = 3r is obtained in the two-point repetition according to the embodiment of the present invention, and the approximate circumscribed circle diameter d 2 ′ is obtained in the staggered structure shown in FIG. = 4r, and the approximate circumscribed circle diameter d 2 of the two points repeated according to the embodiment is compared to the staggered structure of the present invention, reduced r1 one minute, the area is reduced.

図4(b)に示すように、本発明の実施の形態に係る三点繰返し(正三角形頂点)では近似外接円直径d=(2+2/√3)rとなり、近似外接円直径dが約3.2rとなり、図4(e)に示すスタガード構造では、近似外接円直径d’=(2+4/√3)rとなり、d’が約4.3rとなり、本発明の実施の形態に係る三点繰返し(正三角形頂点)の近似外接円直径dがスタガードビア構造と比較して、1.1r減少し、面積が低減している。 As shown in FIG. 4B, in the three-point repetition (equilateral triangle vertex) according to the embodiment of the present invention, the approximate circumscribed circle diameter d 3 = (2 + 2 / √3) r, and the approximate circumscribed circle diameter d 3 is In the staggered structure shown in FIG. 4E, the approximate circumscribed circle diameter d 3 ′ = (2 + 4 / √3) r and d 3 ′ is about 4.3r, which is the embodiment of the present invention. compared to approximate circumscribed circle diameter d 3 is Sutagadobia structure of three-point iteration (equilateral triangle vertex) of the decreased 1.1R, the area is reduced.

図4(c)に示すように、四点繰返しでは近似外接円直径d=(2+√2)rとなり、dが約3.4rとなり、図4(f)に示すスタガードビア構造では、近似外接円直径d’=(2+/√2)rとなり、d’が約5.8rとなり、本発明の実施の形態に係る四点繰返しの近似外接円直径dがスタガードビア構造と比較して、2.4r減少し、面積が低減している。以上のように、本発明の実施の形態に係るビア構造を用いることにより、ビア周りの面積を有効に低減することができる。 As shown in FIG. 4C, the approximate circumscribed circle diameter d 4 = (2 + √2) r is obtained in the four-point repetition, and d 4 is about 3.4r. In the staggered via structure shown in FIG. The approximate circumscribed circle diameter d 4 ′ = (2 + / √2) r, d 4 ′ is approximately 5.8 r, and the approximate circumscribed circle diameter d 4 of the four-point repetition according to the embodiment of the present invention is the staggered via structure. In comparison, the area is reduced by 2.4r. As described above, by using the via structure according to the embodiment of the present invention, the area around the via can be effectively reduced.

本発明の実施の形態に係る半導体パッケージ用多層基板は、接続ビアの位置を繰返し二点間または繰返し三点間とすることにより、高信頼性、かつ配線密度を高くすることができる。   The multilayer substrate for a semiconductor package according to the embodiment of the present invention can increase the reliability and the wiring density by repeatedly connecting the vias between two points or between three points.

次に、本発明の実施の形態に係る半導体パッケージ用多層基板の製造工程について説明する。   Next, the manufacturing process of the multilayer substrate for a semiconductor package according to the embodiment of the present invention will be described.

図5(a)〜(e)及び図6(a)〜(e)は、本発明の実施の形態に係る半導体パッケージ用多層基板の工程を示す概略断面図である。図5(a)に示すように、導体層12、絶縁層11、導体層12という構成の両面導体絶縁層10を用いることができる。導体層12の材料としては、導電率、加工性、価格等の観点から銅などの金属を用いることができる。絶縁層11の材料としては、ガラスエポキシ樹脂、プリプレグ、ポリイミド等を用いることができる。   FIGS. 5A to 5E and FIGS. 6A to 6E are schematic cross-sectional views showing steps of the multilayer substrate for a semiconductor package according to the embodiment of the present invention. As shown in FIG. 5A, a double-sided conductor insulating layer 10 having a configuration of a conductor layer 12, an insulating layer 11, and a conductor layer 12 can be used. As a material of the conductor layer 12, a metal such as copper can be used from the viewpoint of conductivity, workability, price, and the like. As a material of the insulating layer 11, glass epoxy resin, prepreg, polyimide, or the like can be used.

次に、図5(b)に示すように、層間接続用のビア孔13を形成した。ビアの形状としては穴止め加工(ブラインドビア加工)を用いた。ビアの形成の方法としては、UVレーザ、COレーザ等のレーザビア法を用いることができる。層間接続用のビア孔13の径としては、加工性、接続信頼性、微細化への対応等の観点から、Φ30μm以上Φ100μm以下が好ましい。その後、必要に応じて、デスミア処理を行うことができる。デスミア処理の方法としては、例えば、過マンガン酸カリウム等の薬液を用いることができる。 Next, as shown in FIG. 5B, via holes 13 for interlayer connection were formed. As the shape of the via, hole stop processing (blind via processing) was used. As a method for forming the via, a laser via method such as a UV laser or a CO 2 laser can be used. The diameter of the via hole 13 for interlayer connection is preferably Φ30 μm or more and Φ100 μm or less from the viewpoints of workability, connection reliability, miniaturization, and the like. Thereafter, desmear processing can be performed as necessary. As a desmear treatment method, for example, a chemical solution such as potassium permanganate can be used.

次に、図5(c)に示すように、フィルドビアめっき法により、接続ビア33を形成した。フィルドビアめっき法としては、例えば、無電解銅めっきと電解銅めっきとを連続して行い、ビア孔13をフィルドする方法等がある。その後、導体厚をコントロールするため、物理的もしくは化学的研磨、あるいはその両方を行うことができる。物理的研磨の例としては、研磨紙、バフ研磨等が挙げられ、化学研磨液の例としては、硫酸過酸化水素系、過硫酸アンモニウム系が挙げられる。   Next, as shown in FIG. 5C, a connection via 33 was formed by a filled via plating method. Examples of the filled via plating method include a method in which electroless copper plating and electrolytic copper plating are continuously performed to fill the via hole 13. Thereafter, physical or chemical polishing, or both, can be performed to control the conductor thickness. Examples of physical polishing include polishing paper, buffing, and the like, and examples of chemical polishing liquids include sulfuric acid hydrogen peroxide and ammonium persulfate.

次に、図5(d)に示すように、フォトリソグラフィ工程を行った。フォトレジスト14としては、例えば東京応化工業(株)製、ポジ型レジスト等を用いることができる。   Next, as shown in FIG. 5D, a photolithography process was performed. As the photoresist 14, for example, a positive resist manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.

次に、図5(e)に示すように、エッチング処理を行い、フォトレジスト14から露出している部分を除去し、ランド15及び配線16を形成し、2層配線板17を得た。エッチング液としては、塩化第二鉄液、塩化第二銅液等の薬液を用いることができる。なお、本発明の実施の形態では、フォトリソグラフィ技術、エッチングを用いたサブトラクティブ方式(サブトラ法)を用いたが、めっき法を主体としたセミアディティブ方式(セミアド法)を用いて、ランド15や配線16等を形成することもできる。   Next, as shown in FIG. 5E, an etching process was performed to remove a portion exposed from the photoresist 14 to form lands 15 and wirings 16 to obtain a two-layer wiring board 17. As the etching solution, a chemical solution such as ferric chloride solution or cupric chloride solution can be used. In the embodiment of the present invention, the photolithography technique and the subtractive method (subtra method) using etching are used, but the land 15 and the semi-additive method (semi-ad method) mainly using a plating method are used. The wiring 16 or the like can also be formed.

次に、図6(a)に示すように、多層化を行った。多層化の方法としては、絶縁層21にプリプレグを用い、導体層22と同時に熱プレスをする方法や、Bステージ(半硬化)状態の、導体・接着層つき絶縁層20を積層する方法などがある。   Next, as shown in FIG. 6A, multilayering was performed. As a multilayering method, there is a method of using a prepreg for the insulating layer 21 and performing heat pressing simultaneously with the conductor layer 22, or a method of laminating the insulating layer 20 with a conductor / adhesive layer in a B stage (semi-cured) state. is there.

次に、図6(b)に示すように、ビア孔23をUVレーザ、COレーザ等のレーザビア法を用いて形成することができる。この時、ビア孔23と一段下の層の接続ビア33の中心距離dをビア孔23の半径と接続ビア33の半径の和よりも小さく、かつ、中心距離dを10μm以上にすることで、本発明の実施の形態に係るビア構造を形成することができる。形成されるビア孔23の径としては、ビア孔13と同様にΦ30μm以上Φ100μm以下が好ましい。一方、中心距離dは例えば、接続ビア33のトップ部がΦ60μm、ビア孔23のボトム部がΦ40μmである場合、50μm未満となる。 Next, as shown in FIG. 6B, the via hole 23 can be formed using a laser via method such as a UV laser or a CO 2 laser. At this time, the center distance d between the via hole 23 and the connection via 33 of the layer one step below is smaller than the sum of the radius of the via hole 23 and the radius of the connection via 33 and the center distance d is 10 μm or more. A via structure according to an embodiment of the present invention can be formed. The diameter of the via hole 23 to be formed is preferably Φ30 μm or more and Φ100 μm or less like the via hole 13. On the other hand, for example, when the top portion of the connection via 33 is Φ60 μm and the bottom portion of the via hole 23 is Φ40 μm, the center distance d is less than 50 μm.

次に、図6(c)に示すように、フィルドビアめっき法を用いて、接続ビア43を形成した。形成方法については、上述したために省略する。   Next, as shown in FIG.6 (c), the connection via | veer 43 was formed using the filled via plating method. The forming method is omitted because it has been described above.

次に、図6(d)に示すように、フォトリソグラフィ工程を行った。フォトレジスト24については、例えば東京応化工業(株)製、ポジ型レジスト等を用いることができる。   Next, as shown in FIG. 6D, a photolithography process was performed. As the photoresist 24, for example, a positive resist manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.

次に、図6(e)に示すように、エッチング処理を行い、フォトレジスト24から露出している部分を除去し、ランド25及び配線26を形成し、4層配線板27を得た。   Next, as shown in FIG. 6E, an etching process was performed to remove a portion exposed from the photoresist 24 to form lands 25 and wirings 26 to obtain a four-layer wiring board 27.

本発明の実施の形態では、4層配線板27の例を示したが、半導体パッケージ多層基板に要求される特性に応じて、6層、8層など各種多層配線板を形成することができる。また、本発明の実施の形態では記載を省略したが、最外層の絶縁保護層としてソルダーレジストの形成や、ランド25等の外部との接触部に表面処理を行っても良い。   In the embodiment of the present invention, the example of the four-layer wiring board 27 is shown, but various multilayer wiring boards such as six layers and eight layers can be formed according to the characteristics required for the semiconductor package multilayer substrate. Although not described in the embodiment of the present invention, a solder resist may be formed as the outermost insulating protective layer, or surface treatment may be performed on a contact portion with the outside such as the land 25.

さらに、本発明の実施の形態に係るビア接続において、使用する正多角形の頂点数を選択する際には半導体パッケージ用多層基板の層数を考慮する。例えば、半導体パッケージ用多層基板の配線層数が5層や9層の場合は、ビアの段数が4や8となるので正四角形の頂点にビア接続を行い、半導体パッケージ用多層基板の配線層数が6層の場合では、ビアの段数が5となるので正五角形の頂点にビア接続を行うことができる。ビア接続において、上述した正多角形の頂点数を選択する際には半導体パッケージ用多層基板の層数を考慮することで、ビア接続の断線及びインダクタンスを低減して、配線の高密度化を図ることができる。   Furthermore, in the via connection according to the embodiment of the present invention, when selecting the number of vertices of a regular polygon to be used, the number of layers of the multilayer substrate for a semiconductor package is considered. For example, when the number of wiring layers of the multilayer substrate for semiconductor package is 5 or 9, the number of vias is 4 or 8, so via connection is made at the apex of the regular square, and the number of wiring layers of the multilayer substrate for semiconductor package. In the case of six layers, since the number of vias is five, via connection can be made to the apex of a regular pentagon. In the via connection, when selecting the number of vertices of the regular polygon described above, the number of layers of the multilayer substrate for the semiconductor package is taken into consideration, thereby reducing the disconnection and inductance of the via connection and increasing the wiring density. be able to.

まず、図5(a)に示すように、両面導体絶縁層10として、日立化成工業社製、両面銅張積層板を使用した。両面導体絶縁層10の絶縁層11は膜厚40μmであり、両面導体絶縁層10の導体層12の材料は銅であり、膜厚12μmである。   First, as shown in FIG. 5A, a double-sided copper-clad laminate made by Hitachi Chemical Co., Ltd. was used as the double-sided conductor insulating layer 10. The insulating layer 11 of the double-sided conductor insulating layer 10 has a thickness of 40 μm, and the material of the conductor layer 12 of the double-sided conductor insulating layer 10 is copper and has a thickness of 12 μm.

次に、図5(b)に示すように、ブラインドビア(ビア孔13)を波長355nmのUVレーザを使用し、片側の銅箔面(導体層12面)からΦ60μmの加工径で行った。この時、ビアのボトム部はΦ40μmであった。   Next, as shown in FIG. 5 (b), a blind via (via hole 13) was performed using a UV laser having a wavelength of 355 nm with a processing diameter of Φ60 μm from one copper foil surface (conductor layer 12 surface). At this time, the bottom portion of the via was Φ40 μm.

次に、図5(c)に示すように、過マンガン酸塩を主成分とする残渣処理及び無電解銅めっきを行うことでビア孔13内クリーニングと導電性銅皮膜を形成した。その後、電解銅めっきによりビア孔13内を銅により全充填して、接続ビア33を形成した。電解銅めっき浴の組成は硫酸銅200g/L、硫酸100g/L、塩酸50g/L、添加剤微少量、浴温25℃であり電流密度2A/dmにおいて40分間電解めっきを行いビアフィルドを行った。めっき工程後には、めっき層と配線層との銅厚があるため規定の膜厚(9μm)まで化学研磨処理を行った。 Next, as shown in FIG.5 (c), the cleaning in the via hole 13 and a conductive copper film were formed by performing the residue processing which has a permanganate as a main component, and electroless copper plating. Thereafter, the via hole 13 was completely filled with copper by electrolytic copper plating to form a connection via 33. The composition of the electrolytic copper plating bath is 200 g / L of copper sulfate, 100 g / L of sulfuric acid, 50 g / L of hydrochloric acid, a small amount of additives, a bath temperature of 25 ° C., and electrolytic plating is performed for 40 minutes at a current density of 2 A / dm 2 to perform via filling. It was. After the plating step, chemical polishing was performed to a prescribed film thickness (9 μm) because of the copper thickness of the plating layer and the wiring layer.

次に、図5(d)に示すように、フォトレジスト14を配線16上に表裏同時塗布し、両面同時に露光・現像し、フォトレジスト14をパターニングした。次に、図5(e)示すように、パターニングされたフォトレジスト14をエッチングマスクとして塩化第二鉄液により配線16をエッチング処理して、ランド15と配線層17を形成した。以上の工程により2層配線板(テープ基材)17が形成された。なお、2層配線板17にはアライメントマークが形成されており以降の配線26形成時での加工基準となる。   Next, as shown in FIG. 5D, the photoresist 14 was simultaneously applied on the wiring 16 on the front and back, and both sides were exposed and developed at the same time, and the photoresist 14 was patterned. Next, as shown in FIG. 5E, the land 16 and the wiring layer 17 were formed by etching the wiring 16 with a ferric chloride solution using the patterned photoresist 14 as an etching mask. A two-layer wiring board (tape substrate) 17 was formed by the above process. An alignment mark is formed on the two-layer wiring board 17 and becomes a processing reference when forming the wiring 26 thereafter.

次に、図6(a)に示すように、銅箔(導体層22)、プリプレグ(絶縁層21)、2層配線板17、プリプレグ銅箔(導体・接着層つき絶縁層20)の順に重ね、一括プレスにより積層を行った。銅箔(導体層22)には、古川電工社製、膜厚12μmの電解銅箔を用い、プリプレグ(絶縁層21)には日立化成工業製、膜厚40μmのプリプレグを用いた。   Next, as shown in FIG. 6A, the copper foil (conductor layer 22), the prepreg (insulating layer 21), the two-layer wiring board 17, and the prepreg copper foil (insulating layer 20 with conductor / adhesive layer) are stacked in this order. Lamination was performed by a batch press. For the copper foil (conductor layer 22), an electrolytic copper foil made by Furukawa Electric Co., Ltd. with a film thickness of 12 μm was used, and for the prepreg (insulating layer 21), a prepreg made by Hitachi Chemical Co., Ltd. with a film thickness of 40 μm was used.

次に、図6(b)に示すように、層間接続用のビア孔23を表裏形成するために、波長355nmのUVレーザを用いてΦ60μmの加工径でビア孔23の加工を行った。ビア孔13同様ボトム部はΦ40μmであった。多段接続部において、下層の接続ビア33とビア孔23の中心距離dは25μmとした。ビア孔13、ビア孔23はトップ部Φ60μm、ボトム部Φ40μm、中心距離dを25μmとしたため、ビア位置はビア半個分ずれていることになる。またビア接続を上から1段目、2段目、3段目とすると、1段目と3段目とのビア位置を繰返し同一点とした(図2参照)。   Next, as shown in FIG. 6B, the via hole 23 was processed with a processing diameter of Φ60 μm using a UV laser with a wavelength of 355 nm in order to form the via hole 23 for interlayer connection on the front and back sides. Like the via hole 13, the bottom portion has a diameter of 40 μm. In the multistage connection portion, the center distance d between the lower connection via 33 and the via hole 23 was set to 25 μm. Since the via hole 13 and the via hole 23 have a top portion Φ60 μm, a bottom portion Φ40 μm, and a center distance d of 25 μm, the via positions are shifted by half of the vias. Further, if the via connection is the first, second, and third stages from the top, the via positions in the first and third stages are repeatedly set to the same point (see FIG. 2).

次に、図6(c)に示すように、2層配線板17を形成する方法と同様に残渣処理、無電解銅めっきによる導電性皮膜の形成を行い、電解銅めっきを行い、接続ビア43を形成した。その後、所望の膜厚を得るために化学研磨処理を行った。次に、図6(d)示すように、2層配線板17を形成する方法と同様にフォトリソグラフィ工程を行った。次に、図6(e)示すように、2層配線板17を形成する方法と同様にエッチング処理を行った。以上の工程を経ることで、図6(e)示すように4層配線板27が完成した。   Next, as shown in FIG. 6 (c), similar to the method of forming the two-layer wiring board 17, a residue treatment, a conductive film is formed by electroless copper plating, electrolytic copper plating is performed, and connection vias 43 are formed. Formed. Thereafter, chemical polishing was performed to obtain a desired film thickness. Next, as shown in FIG. 6D, a photolithography process was performed in the same manner as the method of forming the two-layer wiring board 17. Next, as shown in FIG. 6E, an etching process was performed in the same manner as the method of forming the two-layer wiring board 17. Through the above steps, a four-layer wiring board 27 was completed as shown in FIG.

また、積層工程(図6(a)〜(e))を表裏繰り返すことで6層配線基板を形成した。図7(a)に示すように、ビア接続の位置を上から1段目、2段目、3段目、4段目、5段目とすると、1段目と5段目とのビアは3段目と同一点に形成した。すなわち、1段目、3段目、5段目と2段目、4段目の接続ビアがそれぞれ同一点にあるという構成である。さらに、最外層には絶縁保護層としてソルダーレジスト(図示せず)を形成した。なお、配線幅は30μmとした。   Moreover, the 6-layer wiring board was formed by repeating the lamination process (FIGS. 6A to 6E). As shown in FIG. 7A, if the via connection positions are the first, second, third, fourth, fifth from the top, the vias in the first and fifth stages are It was formed at the same point as the third stage. That is, the first, third, fifth, second, and fourth connection vias are at the same point. Further, a solder resist (not shown) was formed as an insulating protective layer on the outermost layer. The wiring width was 30 μm.

実施例1の接続ビア43の形成位置を変更したこと以外は実施例1と同様に、6層の導体層を有する半導体パッケージ用多層基板を形成した。ビア径はΦ50μm、中心位置dを25μmとし、図8(a)に示すように、ビアの配置を正三角形の頂点繰返しとした。   A multilayer substrate for a semiconductor package having six conductor layers was formed in the same manner as in Example 1 except that the formation position of the connection via 43 in Example 1 was changed. The via diameter was Φ50 μm, the center position d was 25 μm, and the vias were arranged in a regular triangular vertex as shown in FIG.

[比較例1]
実施例1の接続ビア43の形成位置を変更したこと以外は実施例1と同様にして6層の導体層を有する半導体パッケージ用多層基板を形成した。ビア径をΦ50μmとし、5段スタックドビア構造とした。(参考として3段スタックドビア構造の例を図9に示す。
[Comparative Example 1]
A multilayer substrate for a semiconductor package having six conductor layers was formed in the same manner as in Example 1 except that the formation position of the connection via 43 in Example 1 was changed. The via diameter was 50 μm, and a 5-stage stacked via structure was adopted. (For reference, an example of a three-stage stacked via structure is shown in FIG.

上記工法により製造した半導体パッケージ用多層基板の接続信頼性を評価するために、−65℃×30分〜125℃×30分を条件として冷熱衝撃信頼性試験を行った。評価用の半導体パッケージ用多層基板はチェーン回路であり、主な構成を以下に示す。   In order to evaluate the connection reliability of the multilayer substrate for a semiconductor package manufactured by the above method, a thermal shock reliability test was performed under the condition of −65 ° C. × 30 minutes to 125 ° C. × 30 minutes. The multilayer substrate for semiconductor package for evaluation is a chain circuit, and its main configuration is shown below.

実施例1、2及び比較例1により形成した接続信頼性を評価するための半導体パッケージ用多層基板の構成は、配線総数を6層、配線層厚を9μm、絶縁層厚を40μm、ライン幅を30μm、ビア/ランドを50μm/100μm、1層当たりのビア数を1000ビアとした。実施例1のビア接続形態は図7(a)に示す繰返し二点である。図7(b)は繰返し二点の場合のビアの信号透過イメージを示している。実施例2のビア接続形態は図8(a)に示す繰返し三点である。図8(b)は繰返し三点の場合のビアの信号透過イメージを示している。なお、比較例1のビア接続形態はスタックドビア構造とした。以下に、冷熱衝撃信頼性試験結果を表1に示す。   The structure of the multilayer substrate for a semiconductor package for evaluating the connection reliability formed in Examples 1 and 2 and Comparative Example 1 has a total number of wirings of 6 layers, a wiring layer thickness of 9 μm, an insulating layer thickness of 40 μm, and a line width of 30 μm, vias / lands were 50 μm / 100 μm, and the number of vias per layer was 1000 vias. The via connection form of the first embodiment is two points repeatedly shown in FIG. FIG. 7B shows a signal transmission image of a via in the case of repeated two points. The via connection form of the second embodiment is three repetitive points shown in FIG. FIG. 8B shows a signal transmission image of a via in the case of repeated three points. The via connection form of Comparative Example 1 was a stacked via structure. Table 1 shows the results of the thermal shock reliability test.

表1に示す結果から本発明の半導体用パッケージ用多層基板では規定の2000サイクルまで良好な結果を得ることができた。信頼性評価後、半導体用パッケージ用多層基板を故障・破壊解析したところ、ランド/ビアホール底部間にクラックは認められなかった。よって、本発明はビア接続の信頼性を高くすることができた。一方、比較例1のビア接続がフルスタック構造では1200〜1500サイクルで断線し、信頼性評価後、比較例1を故障・破壊解析したところ、ランド銅とビアホール底部との界面にクラックが発生し、信頼性が低いことがわかった。   From the results shown in Table 1, the multilayer substrate for a semiconductor package of the present invention was able to obtain good results up to the specified 2000 cycles. After the reliability evaluation, failure / destructive analysis of the multilayer substrate for semiconductor package revealed no cracks between the bottoms of the lands / via holes. Therefore, the present invention can improve the reliability of via connection. On the other hand, the via connection of Comparative Example 1 was disconnected in 1200 to 1500 cycles in the full stack structure, and after failure evaluation of Comparative Example 1 after reliability evaluation, a crack occurred at the interface between the land copper and the via hole bottom. It was found that the reliability was low.

1:ランド
2:ビア
3:ビア使用面積(外接円近似)
4:ビアの中心線
10:両面導体絶縁層
20:導体・接着層つき絶縁層
11、21:絶縁層
12、22:導体層
13、23:ビア孔
33、43:接続ビア
12、24:フォトレジスト
15、25:ランド
16、26:配線
17:2層配線板
27:4層配線板
1: Land 2: Via 3: Via use area (circumscribed circle approximation)
4: via center line 10: double-sided conductor insulating layer 20: insulating layer 11 with conductor / adhesive layer, 21: insulating layer 12, 22: conductor layer 13, 23: via hole 33, 43: connecting via 12, 24: photo Resist 15, 25: Land 16, 26: Wiring 17: Two-layer wiring board 27: Four-layer wiring board

Claims (3)

それぞれが第1の面及び第2の面に配線層を有する複数の絶縁層を積層または貼り合わせる半導体パッケージ用多層基板の製造方法において、
前記複数の絶縁層の第i層(i=n、n+1・・・n+k)の絶縁層の前記第1の面の配線層から前記第2の面の配線層に至る第iのビアを前記第i層の絶縁層中に形成し、
第i+1層の絶縁層の第1の面の配線層から第2の面の配線層に至る第i+1のビアを前記第i+1層の絶縁層中に形成し、
前記第iビアと前記第i+1ビアとの中心距離が、前記第iビアの半径と前記第i+1ビアの半径との合計よりも小さくかつ、10μm以上であることを特徴とする半導体パッケージ用多層基板の製造方法。
In a method for manufacturing a multilayer substrate for a semiconductor package, in which a plurality of insulating layers each having a wiring layer on a first surface and a second surface are laminated or bonded together,
The i-th via extending from the wiring layer on the first surface to the wiring layer on the second surface of the i-th insulating layer (i = n, n + 1... N + k) of the plurality of insulating layers, formed in an i-layer insulating layer;
Forming an (i + 1) th via from the wiring layer on the first surface of the i + 1th insulating layer to the wiring layer on the second surface in the insulating layer of the (i + 1) th layer;
A multilayer substrate for a semiconductor package, wherein a center distance between the i-th via and the (i + 1) -th via is smaller than a sum of a radius of the i-th via and a radius of the i + 1-th via and is 10 μm or more. Manufacturing method.
前記ビアの中心距離が、上面から見た場合に繰返し二点、正三角形の頂点及び正四角形の頂点を含む正多角形の頂点のいずれかであることを特徴とする請求項に記載の半導体パッケージ用多層基板の製造方法。 2. The semiconductor according to claim 1 , wherein a center distance of the via is one of a regular polygon vertex including two points repeatedly, a regular triangle vertex, and a regular square vertex when viewed from above. A method of manufacturing a multilayer substrate for a package. 前記正多角形の頂点数は、前記複数のビアの段数に応じて選択することを特徴とする請求項1または2に記載の半導体パッケージ用多層基板の製造方法The number of vertices regular polygon, a method for manufacturing a multilayer substrate for a semiconductor package according to claim 1 or 2, characterized in that selected depending on the number of the plurality of vias.
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