JP5373832B2 - はんだ濡れ性の前面金属部を備えるｉｉｉ族窒化物パワーデバイス - Google Patents

はんだ濡れ性の前面金属部を備えるｉｉｉ族窒化物パワーデバイス Download PDF

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JP5373832B2
JP5373832B2 JP2011025214A JP2011025214A JP5373832B2 JP 5373832 B2 JP5373832 B2 JP 5373832B2 JP 2011025214 A JP2011025214 A JP 2011025214A JP 2011025214 A JP2011025214 A JP 2011025214A JP 5373832 B2 JP5373832 B2 JP 5373832B2
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semiconductor device
solder
power semiconductor
group iii
nitride power
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JP2011187946A (ja
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チェアー チュアン
エイ ブリエール マイケル
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インターナショナル レクティフィアー コーポレイション
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Description

（関連出願）
本出願は２０１０年２月１６日出願の係属中の仮出願第６１／３３７，９２４号「ソースおよびドレイン棒はんだを備える、はんだ濡れ性の前面金属部を有するＩＩＩ族窒化物パワーデバイス」の優先権を主張する。その係属中の仮出願における開示は、参照により本出願に完全に組み込むものとする。
本出願は、一般に半導体デバイス分野、とくに半導体デバイスのパッケージングに関する。
ハイパワー性能のための技術分野では、窒化ガリウム高電子移動度トランジスタ、すなわちＧａＮ ＨＥＭＴのようなＩＩＩ族窒化物パワーデバイスが知られている。しかしながら、こうしたデバイスの性能は、従来の相互接続スキームを用いることにより制約されていた。よって、当技術分野では、複数の相互接続金属層を用いるＧａＮ ＨＥＭＴデバイスが開発された。
こうした多層ＩＩＩ族窒化物パワーデバイスは、従来の集積方法、例えばプリント回路基板のような支持体表面上へ集積するためのはんだボールアレイなどを用いた。とくに、縮小されたフットプリントパッケージを集積する場合、はんだブリッジのような問題を回避するため、はんだボールアレイを用いることは好都合であることが多い。あいにく、こうした従来の集積方法は、回路を通る電流のフローを制限することによりデバイスのＲｄｓｏｎ、すなわち「オン抵抗」を増加させ、その結果そもそも多層ＩＩＩ族窒化物パワーデバイスを用いる利点を打ち消す。
よって、Ｒｄｓｏｎを低減しつつ、多層ＩＩＩ族窒化物パワーデバイスを支持体表面上に集積し、これによりＩＩＩ族窒化物パワーデバイスのハイパワー性能能力を活用するための解決方法が望まれている。
実質的には、図面の少なくとも１つに示し、および／またはそれに関連して説明するような、より完全には特許請求の範囲に記載するような、はんだ濡れ性の前面金属部を備えるＩＩＩ族窒化物パワーデバイス。
本発明の実施形態による多層ＩＩＩ族窒化物パワーデバイスの断面図を示す。 本発明の実施形態による多層ＩＩＩ族窒化物パワーデバイスの上面図を示す。 本発明の実施形態による多層ＩＩＩ族窒化物パワーデバイスを収容する基板の上面図を示す。 本発明の実施形態による基板上に取り付けた多層ＩＩＩ族窒化物パワーデバイスの断面図を示す。 本発明の実施形態による多層ＩＩＩ族窒化物パワーデバイスを集積する回路図を示す。
本発明は、はんだ濡れ性の前面金属部を備えるＩＩＩ族窒化物パワーデバイスを対象とする。以下の説明は、本発明の実施に関連する具体的な情報を含む。当業者であれば、本発明を本出願で具体的に議論するものとは異なる方法で実施することができることを認識できる。また、本発明の具体的な詳細のいくつかについては、本発明を不明りょうにしないよう議論をしていない。本願に記載されていない詳細な説明も、当業者の知識の範囲内である。
本出願の図面およびそれらに付随する詳細な説明は、本発明の単なる典型的な実施形態を対象とする。さらに、より明瞭にかつ読みやすくするため、図面は縮尺どおり正確に表示しないこともある。簡潔さを保つため、本発明の他の実施形態については、本出願に具体的に記載せず、本図面にも具体的に示さない。
図１を参照すると、本発明の１つの実施形態による典型的な多層ＩＩＩ族窒化物パワーデバイスの断面図を示す。図１では、パワーデバイス１００は、多層ＡｌＧａＮ／ＧａＮ高電子移動度トランジスタ（ＨＥＭＴ）またはヘテロ接合電界効果トランジスタ（ＨＦＥＴ）からなることができる。図１に示すように、パワーデバイス１００は、保護膜１１０、はんだ濡れ性の前面金属部（ＳＦＭ）１４０ａおよび１４０ｂ、金属層１３０ａ、１３０ｂ、１３０ｃ、１３０ｄおよび１３０ｅ、金属間誘電体（ＩＭＤ）層１１２ａ、１１２ｂおよび１１２ｃ、テトラエトキシシラン（ＴＥＯＳ）層１１４ａおよび１１４ｂ、ビア１３２ａ、１３２ｂ、１３２ｃおよび１３２ｄ、窒化アルミニウムガリウム（ＡｌＧａＮ）層１２４、窒化ガリウム（ＧａＮ）層１２２、シリコン基板１２０、窒化フィールド１２６、窒化ゲート１２８、ならびに図示しない他の要素を含む。
図１では、金属層１３０ａは、例えば、窒化チタニウム、または別の適切なゲート金属からなることができる。金属層１３０ｅは、例えば、アルミニウム、またはその他の適切な金属からなることができる。ＩＭＤ層１１２ａ〜１１２ｃは、例えば、ＴＥＯＳからなることができる。保護膜１１０は、例えば、エポキシ、ポリイミド、酸化ケイ素、または他の適切な物質からなることができる。エポキシは、ダイをはんだ付けするときに構造的完全性を維持するため、２０〜２５ミクロンのような十分な厚さを提供するのに好適であり得る。図１に示すように、保護膜１１０はＳＦＭ１４０ａおよび１４０ｂの周りを囲み、そこから例えば約５ミクロンほど延在する。１つの実施形態では、保護膜１１０は、ＳＦＭ１４０ａおよび１４０ｂの幅に対応するため、約２００ミクロン幅のはんだ付け面を残すように構成することができる。ＳＦＭ１４０ａおよび１４０ｂは、その呼称が示すように、上面または前面の露出した金属がはんだ濡れ性を有するように構成される。例えば、ＳＦＭ１４０ａおよび１４０ｂはそれぞれ、金属層１３０ｅとともに積層構成でトリメタルを形成することができ、９２．５％鉛はんだのような高鉛はんだとの使用に適している。１つのこうしたトリメタルは、金属層１３０ｅがアルミニウムからなり、ＳＦＭ１４０ａおよび１４０ｂがそれぞれ下層としてのチタニウム、中層としてのニッケル、および上層としての銀からなる、ＴｉＮｉＡｇからなることができる。トリメタルＳＦＭのチタンはアルミニウム金属層１３０ｅと接するバリア層として有効であり、銀は溶けてイオンになりはんだ付け時の導電性を高め、ニッケルは接触層として残る。
図１に示すように、ＡｌＧａＮ層１２４およびＧａＮ層１２２をシリコン基板１２０の上に配置し、高移動度の二次元電子ガス（２ＤＥＧ）を形成する。ＧａＮ系ＩＩＩ族窒化物パワーデバイスは、例えば、とくにＤＣ−ＤＣコンバータのようなパワーマネジメントアプリケーションに適した、固有の高い降伏特性により有利である。図１は４つの相互接続金属層パワーデバイスとして構成されたパワーデバイス１００を示すが、代替実施形態は異なる数の相互接続金属層を備えるパワーデバイスからなることができる。図１に示す特定の断面では、ビア１３２ａおよび１３２ｂは金属層１３０ｂを金属層１３０ｃに接続しているように見られ、ビア１３２ｃは金属層１３０ｃを金属層１３０ｄに接続しているように見られ、ビア１３２ｄは金属層１３０ｄを金属層１３０ｅに接続しているように見られる。適切な接続性のためには備えるビアが不十分に見えるかもしれないが、図１の断面を異なる深さで取れば、ＩＩＩ族窒化物デバイスのゲート、ソース、およびドレイン接続を外部でまたは外部に完全に接続するのに必要な接続を提供する追加のビアが図示される。図１に示すＩＩＩ族窒化物パワーデバイス１００の多重相互接続金属層構造ならびにＳＦＭ１４０ａおよび１４０ｂを用いることにより、電流のソースからドレインまでの効率的な移動が可能となり、これによりオン抵抗（Ｒｄｓｏｎ）を有利に最小化するが、これはＩＩＩ族窒化物パワーデバイス１００のソースおよびドレインには大電流が通過するため重要となり得る。
図２を参照すると、本発明の１つの実施形態による典型的な多層ＩＩＩ族窒化物パワーデバイスの上面図を示す。多くのパワーアプリケーションでは、いくつかのＨＦＥＴ（またはＨＥＭＴ）を単一のダイ上に集積することが望ましくあり得る。よって、図２に示すように、パワーデバイス２００は２つのＨＦＥＴ、制御ＦＥＴ２３０および同期ＦＥＴ２４０を集積する。この例では、制御ＦＥＴ２３０は、ゲートデジット２３６、ソースデジット２３２ａ、２３２ｂ、２３２ｃおよび２３２ｄ、ならびにドレインデジット２３４ａ、２３４ｂおよび２３４ｃを含む。同期ＦＥＴ２４０は、ゲートデジット２４６、ソースデジット２２２、２４２ａ、２４２ｂおよび２４２ｃ、ならびにドレインデジット２４４ａ、２４４ｂ、２４４ｃおよび２４４ｄを含む。図２に示すように、パワーデバイス２００は、ダイの上のＳＦＭから間隔のあいた交互の相互嵌合したソースおよびドレインデジットを露出する。次にこれらの細長いデジットを、長い棒はんだを用い、支持基板上の銅トレースにはんだ付けすることができる。この方法では、はんだブリッジを最小化しながら、はんだ付け面の表面積が従来のはんだボールまたは従来のはんだバンプを用いることに対して最適化される。図２には８列のデジットを示すが、代替実施形態は、アプリケーション要件に従ってより多いまたは少ないデジットを用いることができる。
図３を参照すると、本発明の１つの実施形態による典型的なＩＩＩ族窒化物パワーデバイスを収容する典型的な基板の上面図を示す。図３に示すように、基板３００は、以下で議論する図４に示す断面に対応する断面Ａ−Ａを含む。基板３００は、図２のパワーデバイス２００に対応するＩＩＩ族窒化物ダイ３１０、ゲートドライバ集積回路（ＩＣ）３１２、ならびにコンデンサ３１４ａ、３１４ｂ、３１４ｃおよび３１４ｄを含んでいる、いくつかの部品を収容することができる。はんだパッド３０１はゲートドライバＩＣ３１２のピン１接続を示し、時計回りの方向にピン数が増えていく。ゲートドライバＩＣ３１２としては、例えば、インターナショナルレクティフィアーから市販されているＩＲＤ２０１０ドライバＩＣを備えることができる。基板３００は、該基板３００上にひっくり返すと、パワーデバイス２００に対応するＩＩＩ族窒化物ダイ３１０によって、露出したＳＦＭをそれぞれ受ける、棒はんだ３５４ａ、３５４ｂ、３５６ａ、３５６ｂ、３５８ａ、３５８ｂ、３６０ａ、３６０ｂ、３４４、３６２、３４６、３６４、３４８、３６６、３２２ａ、３２２ｂ、および３５０をさらに含む。基板は、例えば、はんだフィルのすべての側面上に２５ミクロンの空パッドを備える対応する開口を備えることにより、ＳＦＭの位置付けを助けることができる。
棒はんだ下の基板３００の灰色部分は銅トレースであり、これは導電性を向上させ、抵抗を低減するため、好適には１平方インチ当たり１〜２ｏｚ以上の厚さとすることができる。ビア３５２のようないくつかのビアも基板３００全体に示すが、導電性を向上させ、抵抗を低減するため、好適には少なくとも４０ミクロンの壁を備えることができる。ビアは、プリント回路基板へのような外部回路接続へのルートを提供することができる。図３ではビアを同じ大きさとして示すが、実際には異なる大きさとすることができる。
棒はんだ３６２、３６４、および３６６は、ゲートドライバＩＣ３１２から入力電圧（Ｖｉｎ）を受ける、制御ＦＥＴ２３０のドレインに接続しているＳＦＭと接触する。棒はんだ３４４、３４６、３４８、および３５０は、同期ＦＥＴ２４０のソースまたはパワーグランド（Ｐグランド）に接続し、アナログまたはシグナルグランドと区別されたＳＦＭと接触する。棒はんだ３４４、３４６、３４８、および３５０は、孤立しているように見えるかもしれないが、実際には、ビアによって図示しない接地層にともに接地されている。棒はんだ３５４ａ、３５４ｂ、３５６ａ、３５６ｂ、３５８ａ、３５８ｂ、３６０ａおよび３６０ｂは、制御ＦＥＴ２３０のソースを同期ＦＥＴ２４０のドレインに接続するスイッチノード３３６に接続している。スイッチノード３３６は、制御ＦＥＴ２３０の「ゲートリターン」としても機能する。ノード３４４は制御ＦＥＴ２３０のゲートに接続し、ノード３３８はＰグランドに接続し、同期ＦＥＴ２４０の「ゲートリターン」としても機能し、ノード３４０は同期ＦＥＴ２４０のゲートに接続している。
ノード３３２は、ゲートドライバＩＣ３１２を、ブートストラップまたはブースト（ＢＳＴ）コンデンサからなるであろうコンデンサ３１４ｃに接続する。ノード３４２は、ゲートドライバＩＣ３１２を、リップルノイズをフィルタするバイパスコンデンサからなるであろうコンデンサ３１４ｄに接続する。図３にはコンデンサ３１４ａおよび３１４ｂも示すが、並列接続され、ゲートドライバＩＣ３１２からＶｉｎを受ける。図３に示すように、はんだパッド３７０ａ〜３７０ｄおよび３７２ａ〜３７２ｄは、基板３００上に適切に位置付けられ、コンデンサ３１４ａ〜３１４ｄを受ける。
ここで図４を参照すると、本発明の１つの実施形態による基板上に取り付けられた典型的な多層ＩＩＩ族窒化物パワーデバイスの断面図を示す。以上で議論したように、図４の断面は図３の断面Ａ‐Ａから取っている。ＩＩＩ族窒化物ダイ４１０をひっくり返すと、露出したＳＦＭは棒はんだ４０４および４０６の真上にくる。図３のスイッチノード３３６を、はんだ棒４０４の上にある同期ＦＥＴ２４０のドレインおよびはんだ棒４０６の上にある制御ＦＥＴ２３０のソースを接続する銅トレース４８２によって短絡させる。
図４に示すように、従来のはんだボールまたはバンプを用いるのではなくＩＩＩ族窒化物ダイ４１０のＳＦＭと平行する棒はんだ４０４および４０６を用いることは、導電および放熱のためのより大きな表面積をもたらし、Ｒｄｓｏｎを有利に低減する。さらに、棒はんだ４０４および４０６は横方向に連続しているので、電流を棒はんだ４０４および４０６を通して横方向に送ることができ、さらに導電性を向上させる。対照的に、従来のはんだボールまたはバンプを用いた場合、ボールが非導電性ギャップを導入するため、電流を銅トレース４８２またはＩＩＩ族窒化物ダイ４１０を通る別のルートを提供する必要があり、電流は横方向に進むことができない。
ここで図５を参照すると、本発明の１つの実施形態による典型的な多層ＩＩＩ族窒化物パワーデバイスを集積する回路図を示す。Ｑ１と表示される制御ＦＥＴ５１０ａは、図２の制御ＦＥＴ２３０に対応することができる。Ｑ２と表示される同期ＦＥＴ５１０ｂは、図２の同期ＦＥＴ２４０に対応することができる。Ｃ１と表示されるコンデンサ５１２ａは、図３の並列接続コンデンサ３１４ａおよび３１４ｂに対応することができる。Ｃ２と表示されるコンデンサ５１２ｃは、図３のコンデンサ３１４ｃに対応することができる。Ｃ３と表示されるコンデンサ５１２ｄは、図３のコンデンサ３１４ｄに対応することができる。インターナショナルレクティフィアーによるＩＲＤ２０１０ドライバＩＣとして図示するゲートドライバＩＣ５１４は、図３に示すゲートドライバＩＣ３１２に対応することができる。
以上で議論したように、ＩＩＩ族窒化物パワーデバイスのダイ上で加工および集積され、パッケージ基板上で棒はんだに接続されたＳＦＭは、ともにＲｄｓｏｎを最小化し、従ってＦＥＴ５１０ａ（Ｑ１）とＦＥＴ５１０ｂ（Ｑ２）との間のスイッチノード（ＳＷ）における導電性を向上させ、図５に示すパワー回路５００、例えばＤＣ−ＤＣバックコンバータ（本出願では一般に「ＤＣ−ＤＣ変換回路」とも称する）を、より効率良く稼働させることができる。こうして、以上で議論したように、図１〜５の実施形態では、本発明は、とりわけ、その中で用いられるパワートランジスタの実効Ｒｄｓｏｎの低減を含む伝熱および導電性能の向上をもたらす、ＩＩＩ族窒化物パワーデバイスおよびそのパッケージを実現する。
上述の本発明の詳細な説明から、本発明の概念を、その範囲から逸脱することなく、様々な技術を用いて実施することができることは明らかである。また、本発明を特定の実施形態を具体的に参照して説明したが、当業者であれば、本発明の精神および範囲から逸脱することなく、外形および細部を変更することができることを理解するだろう。例えば、導電および非導電セルは、本発明の精神をなお具現化しながらも、異なる要素および構成を有することができる。このように、記載した実施形態はあらゆる点で例示的であって限定的ではないと見なされたい。本発明は、本明細書に記載した特定の実施形態に限定されず、多くの再構成、修正、代用が可能であることも理解されたい。

Claims (20)

  1. 第１のＩＩＩ族窒化物層と、
    該第１のＩＩＩ族窒化物層とヘテロ接合を形成する第２のＩＩＩ族窒化物層と、
    該第２のＩＩＩ族窒化物層上のフィールド窒化物層およびゲート窒化物と、
    該ゲート窒化物上のゲート金属と、
    該第２のＩＩＩ族窒化物層上の上部金属層および下部金属層を含む複数の相互接続金属層であって、該下部金属層は前記ゲート金属上のソースコンタクト、ドレインコンタクトおよびゲートコンタクトを含む、相互接続金属層と、
    該ソースコンタクト、該ドレインコンタクトおよび該ゲートコンタクトと前記上部金属層とを接続するため、前記複数の相互接続金属層を複数の誘電体層を通して相互接続する複数のビアと、
    前記上部金属層上のはんだ濡れ性の前面金属部であって、間隔を空けて延在する指部（デジット）に実質的に沿って延びた棒はんだを介した外部回路接続のために設けられた、該間隔を空けて延在するデジットを有するはんだ濡れ性の前面金属部と、を備える、
    第１の高電子移動度トランジスタ（ＨＥＭＴ）を含むＩＩＩ族窒化物パワー半導体デバイス。
  2. 前記間隔を空けて延在するデジットが、交互に前記ソースコンタクトおよび前記ドレインコンタクトと接合する、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  3. 第２のＨＥＭＴをさらに含み、前記第１のＨＥＭＴの前記はんだ濡れ性の前面金属部および該第２のＨＥＭＴのはんだ濡れ性の前面金属部は、交互の相互嵌合したソースおよびドレイン指部（ソースおよびドレインデジット）を露出する、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  4. 前記上部金属層上に前記はんだ濡れ性の前面金属部を囲む保護膜をさらに備える、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  5. 前記上部金属層上にエポキシ、ポリアミドおよび酸化ケイ素からなる群から選択される保護膜をさらに備える、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  6. 前記第１のＩＩＩ族窒化物層がＧａＮからなり、前記第２のＩＩＩ族窒化物層がＡｌＧａＮからなる、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  7. 前記はんだ濡れ性の前面金属部がチタン−ニッケル−銀（ＴｉＮｉＡｇ）のトリメタルからなる、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  8. 前記第１のＩＩＩ族窒化物層がシリコン基板上にある、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  9. 前記はんだ濡れ性の前面金属部を、前記棒はんだを用いて、前記外部回路接続のための回路基板の導電トレースにはんだ付けする、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  10. 前記はんだ濡れ性の前面金属部を、前記棒はんだを用いて、ＤＣ‐ＤＣ変換回路を実装するための回路基板の導電トレースにはんだ付けする、請求項１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  11. 複数の相互接続金属層を有する第１の高電子移動度トランジスタ（ＨＥＭＴ）を含み、
    該第１のＨＥＭＴは上部金属層上にはんだ濡れ性の前面金属部を備え、該はんだ濡れ性の前面金属部は該第１のＨＥＭＴのゲートコンタクト、ソースコンタクトおよびドレインコンタクトと接合する間隔を空けて延在した指部（デジット）を含み、該はんだ濡れ性の前面金属部は前記間隔を空けて延在したデジットに実質的に沿って延びた棒はんだを介した外部回路接続のために設けられる、
    ＩＩＩ族窒化物パワー半導体デバイス。
  12. 前記間隔を空けて延在したデジットが前記ソースコンタクトおよび前記ドレインコンタクトと交互に接合する、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  13. 第２のＨＥＭＴをさらに含み、前記第１のＨＥＭＴの前記はんだ濡れ性の前面金属部および該第２のＨＥＭＴのはんだ濡れ性の前面金属部が交互の相互嵌合したソースおよびドレイン指部（ソースおよびドレインデジット）と露出する、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  14. 前記上部金属層上に前記はんだ濡れ性の前面金属部を囲む保護膜をさらに備える、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  15. 前記上部金属層上にエポキシ、ポリアミド、および酸化ケイ素からなる群から選択される保護膜をさらに備える、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  16. 前記第１のＨＥＭＴがＡｌＧａＮ／ＧａＮ ＨＥＭＴである、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  17. 前記はんだ濡れ性の前面金属部がチタン−ニッケル−銀（ＴｉＮｉＡｇ）のトリメタルからなる、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  18. 前記第１のＨＥＭＴをシリコン基板上に配置する、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  19. 前記はんだ濡れ性の前面金属部を、棒はんだを用いて、前記外部回路接続のための回路基板の導電トレースにはんだ付けする、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
  20. 前記はんだ濡れ性の前面金属部を、棒はんだを用いて、ＤＣ‐ＤＣ変換回路を実装するための回路基板の導電トレースにはんだ付けする、請求項１１に記載のＩＩＩ族窒化物パワー半導体デバイス。
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