JP5373403B2 - データ処理システムを試験するための方法および装置 - Google Patents

データ処理システムを試験するための方法および装置 Download PDF

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Publication number
JP5373403B2
JP5373403B2 JP2008555430A JP2008555430A JP5373403B2 JP 5373403 B2 JP5373403 B2 JP 5373403B2 JP 2008555430 A JP2008555430 A JP 2008555430A JP 2008555430 A JP2008555430 A JP 2008555430A JP 5373403 B2 JP5373403 B2 JP 5373403B2
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Japan
Prior art keywords
test
processor
code
stop
output
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Expired - Fee Related
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JP2008555430A
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English (en)
Japanese (ja)
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JP2009527821A (ja
JP2009527821A5 (enExample
Inventor
アール． モリソン、ギャリー
エイ． リヨン、ホセ
シー． モイヤー、ウィリアム
エム． レイポルド、アンソニー
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2008555430A 2006-02-16 2007-01-18 データ処理システムを試験するための方法および装置 Expired - Fee Related JP5373403B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/355,681 2006-02-16
US11/355,681 US7444568B2 (en) 2006-02-16 2006-02-16 Method and apparatus for testing a data processing system
PCT/US2007/060660 WO2007103591A2 (en) 2006-02-16 2007-01-18 Method and apparatus for testing a data processing system

Publications (3)

Publication Number Publication Date
JP2009527821A JP2009527821A (ja) 2009-07-30
JP2009527821A5 JP2009527821A5 (enExample) 2010-03-04
JP5373403B2 true JP5373403B2 (ja) 2013-12-18

Family

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Family Applications (1)

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JP2008555430A Expired - Fee Related JP5373403B2 (ja) 2006-02-16 2007-01-18 データ処理システムを試験するための方法および装置

Country Status (5)

Country Link
US (1) US7444568B2 (enExample)
JP (1) JP5373403B2 (enExample)
KR (1) KR101318697B1 (enExample)
TW (1) TWI403744B (enExample)
WO (1) WO2007103591A2 (enExample)

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US7797599B2 (en) * 2006-09-27 2010-09-14 Verigy (Singapore) Pte. Ltd. Diagnostic information capture from logic devices with built-in self test
US20080098269A1 (en) * 2006-09-29 2008-04-24 Bhavsar Dilip K Mechanism for concurrent testing of multiple embedded arrays
US20090228751A1 (en) * 2007-05-22 2009-09-10 Tilman Gloekler method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engine
US7721176B2 (en) * 2007-12-06 2010-05-18 International Business Machines Corporation Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints
US8086925B2 (en) * 2008-05-20 2011-12-27 International Business Machines Corporation Method and system for LBIST testing of an electronic circuit
WO2010038096A1 (en) * 2008-09-30 2010-04-08 Freescale Semiconductor, Inc. Method and apparatus for handling an output mismatch
WO2010120737A1 (en) * 2009-04-13 2010-10-21 Telcordia Technologies, Inc. Learning program behavior for anomaly detection
US8522085B2 (en) * 2010-01-27 2013-08-27 Tt Government Solutions, Inc. Learning program behavior for anomaly detection
US8312331B2 (en) * 2009-04-16 2012-11-13 Freescale Semiconductor, Inc. Memory testing with snoop capabilities in a data processing system
US8136001B2 (en) * 2009-06-05 2012-03-13 Freescale Semiconductor, Inc. Technique for initializing data and instructions for core functional pattern generation in multi-core processor
US9874870B2 (en) * 2009-08-26 2018-01-23 Fisher-Rosemount Systems, Inc. Methods and apparatus to manage testing of a process control system
US20110087861A1 (en) * 2009-10-12 2011-04-14 The Regents Of The University Of Michigan System for High-Efficiency Post-Silicon Verification of a Processor
US8458543B2 (en) * 2010-01-07 2013-06-04 Freescale Semiconductor, Inc. Scan based test architecture and method
US8438442B2 (en) * 2010-03-26 2013-05-07 Freescale Semiconductor, Inc. Method and apparatus for testing a data processing system
US8335881B2 (en) * 2010-03-26 2012-12-18 Freescale Semiconductor, Inc. Method and apparatus for handling an interrupt during testing of a data processing system
US8527826B2 (en) * 2011-11-07 2013-09-03 International Business Machines Corporation Logic corruption verification
US9281079B2 (en) * 2013-02-12 2016-03-08 International Business Machines Corporation Dynamic hard error detection
US9404969B1 (en) * 2013-11-01 2016-08-02 Cadence Design Systems, Inc. Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies
US9285424B2 (en) 2014-07-25 2016-03-15 Freescale Semiconductor,Inc. Method and system for logic built-in self-test
US10031181B1 (en) * 2015-06-18 2018-07-24 Marvell Israel (M.I.S.L.) Ltd. Integrated circuit package receiving test pattern and corresponding signature pattern
US9891282B2 (en) * 2015-12-24 2018-02-13 Intel Corporation Chip fabric interconnect quality on silicon
US10578672B2 (en) * 2015-12-31 2020-03-03 Stmicroelectronics (Grenoble 2) Sas Method, device and article to test digital circuits
US10452493B2 (en) * 2016-05-24 2019-10-22 Virginia Tech Intellectual Properties, Inc. Microprocessor fault detection and response system
US10249380B2 (en) * 2017-01-27 2019-04-02 Qualcomm Incorporated Embedded memory testing with storage borrowing
JP2019158749A (ja) * 2018-03-15 2019-09-19 株式会社東芝 画像処理装置及び画像処理方法
US11204849B2 (en) * 2020-03-13 2021-12-21 Nvidia Corporation Leveraging low power states for fault testing of processing cores at runtime
CN115356620B (zh) * 2022-08-17 2025-07-25 地平线(上海)人工智能技术有限公司 片上系统的数字逻辑自测试方法、装置、电子设备和介质

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US3671940A (en) * 1970-03-19 1972-06-20 Burroughs Corp Test apparatus for digital computer
US3839705A (en) * 1972-12-14 1974-10-01 Gen Electric Data processor including microprogram control means
US4042914A (en) * 1976-05-17 1977-08-16 Honeywell Information Systems Inc. Microprogrammed control of foreign processor control functions
US4679194A (en) * 1984-10-01 1987-07-07 Motorola, Inc. Load double test instruction
JP2644798B2 (ja) * 1988-01-29 1997-08-25 株式会社日立製作所 信号処理回路の自己診断方式
JPH0455778A (ja) * 1990-06-26 1992-02-24 Toshiba Corp 半導体装置のテスト方法
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Also Published As

Publication number Publication date
WO2007103591A2 (en) 2007-09-13
US7444568B2 (en) 2008-10-28
TW200817704A (en) 2008-04-16
JP2009527821A (ja) 2009-07-30
KR101318697B1 (ko) 2013-10-16
WO2007103591A3 (en) 2008-12-04
US20070260950A1 (en) 2007-11-08
TWI403744B (zh) 2013-08-01
KR20080098609A (ko) 2008-11-11

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