JP5260558B2 - ダミー画素、暗電流低減方法及び画像センサ - Google Patents
ダミー画素、暗電流低減方法及び画像センサ Download PDFInfo
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H01L27/144—Devices controlled by radiation
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Description
2.サポートするOB画素サブアレー領域からアクティブクリア画素アレーを分離するアクティブクリアダミー画素のサブアレー領域
3.ダミー画素サブアレーに任意に含むことができるOBダミー画素サブアレー領域
4.深く逆バイアス(3V)され、動作中のセンサの自己放出の領域に隣接する余分な少数キャリアを吸収する複数のN型拡散領域を含む任意のガードバンド領域
Claims (18)
- フォトダイオードと、
上記フォトダイオードに接続され、ソフトリセットモードでバイアスされたリセットトランジスタとを備え、
上記リセットトランジスタは、リセットラインに接続されたゲート及びドレインを有し、該リセットラインは、第1の所定の電圧に設定されていることを特徴とするダミー画素。 - 上記リセットラインは、アクティブクリア画素のリセットトランジスタのドレインが接続されるリセットバスには接続されていないことを特徴とする請求項1記載のダミー画素。
- 上記フォトダイオード及び上記リセットトランジスタのソースに接続されたゲートと、上記リセットラインに接続されたドレインとを有する増幅トランジスタを更に備える請求項2記載のダミー画素。
- 上記増幅トランジスタのソースに接続されたドレインと、第2の所定の電圧に接続されたゲートとを有する読出トランジスタを更に備える請求項3記載のダミー画素。
- 上記第1の所定の電圧は、回路電源電圧であることを特徴とする請求項4記載のダミー画素。
- 上記第2の所定の電圧は、ゼロボルトであることを特徴とする請求項5記載のダミー画素。
- 上記フォトダイオードは、迷走電子のための電流シンクを構成することを特徴とする請求項1記載のダミー画素。
- 上記ダミー画素は、アクティブクリア画素として形成されていることを特徴とする請求項1記載のダミー画素。
- 上記ダミー画素は、オプティカルブラック画素として形成されていることを特徴とする請求項1記載のダミー画素。
- 画像センサにおける暗電流を低減する暗電流低減方法において、
上記画像センサ内に少なくとも1つの行又は列のダミー画素を形成する工程を有し、
上記各ダミー画素は、ソフトリセットモードで永続的にバイアスされたリセットトランジスタを有する画素であり、
上記各ダミー画素のフォトダイオードは、迷走電子のための電流シンクとして機能することを特徴とする暗電流低減方法。 - 上記ダミー画素は、アクティブクリア画素として形成されることを特徴とする請求項10記載の暗電流低減方法。
- 上記ダミー画素は、オプティカルブラック画素として形成されていることを特徴とする請求項10記載の暗電流低減方法。
- 上記少なくとも1つの行又は列のダミー画素は、画像センサの周辺領域に形成され、エッジ効果を減少させることを特徴とする請求項10記載の暗電流低減方法。
- 上記少なくとも1つの行又は列のダミー画素は、画像センサのサブアレーの間に形成され、サブアレーを互いに分離することを特徴とする請求項10記載の暗電流低減方法。
- アクティブクリア画素のアレーと、
オプティカルブラック画素の複数のサブアレーと、
上記アクティブクリア画素のアレー及び上記オプティカルブラック画素のサブアレーの間に配置されたダミー画素からなる複数のサブアレーとを備え、
上記各ダミー画素は、
フォトダイオードと、
上記フォトダイオードに接続され、ソフトリセットモードでバイアスされたリセットトランジスタとを備え、
上記リセットトランジスタは、リセットラインに接続されたゲート及びドレインを有し、該リセットラインは、第1の所定の電圧に設定されており、上記アクティブクリア画素のリセットトランジスタのドレインが接続されるリセットバスには接続されていないことを特徴とする画像センサ。 - 当該画像センサの周辺に配置され、エッジ効果を低減するダミー画素のサブアレーを更に備える請求項15記載の画像センサ。
- 上記ダミー画素は、アクティブクリア画素として形成されていることを特徴とする請求項15記載の画像センサ。
- 上記ダミー画素は、オプティカルブラック画素として形成されていることを特徴とする請求項15記載の画像センサ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/715,736 US7755679B2 (en) | 2007-03-07 | 2007-03-07 | Apparatus and method for reducing edge effect in an image sensor |
US11/715,736 | 2007-03-07 | ||
PCT/US2008/002242 WO2008108926A1 (en) | 2007-03-07 | 2008-02-20 | Apparatus and method for reducing edge effect in an image sensor |
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JP2010520708A JP2010520708A (ja) | 2010-06-10 |
JP2010520708A5 JP2010520708A5 (ja) | 2011-03-17 |
JP5260558B2 true JP5260558B2 (ja) | 2013-08-14 |
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JP2009552685A Active JP5260558B2 (ja) | 2007-03-07 | 2008-02-20 | ダミー画素、暗電流低減方法及び画像センサ |
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Country | Link |
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US (1) | US7755679B2 (ja) |
EP (1) | EP2118919B1 (ja) |
JP (1) | JP5260558B2 (ja) |
WO (1) | WO2008108926A1 (ja) |
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