JP5244128B2 - 電界効果トランジスタ（ＦＥＴ）の製造方法、ｎ型およびｐ型電界効果トランジスタ - Google Patents

電界効果トランジスタ（ＦＥＴ）の製造方法、ｎ型およびｐ型電界効果トランジスタ Download PDF

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JP5244128B2
JP5244128B2 JP2009549213A JP2009549213A JP5244128B2 JP 5244128 B2 JP5244128 B2 JP 5244128B2 JP 2009549213 A JP2009549213 A JP 2009549213A JP 2009549213 A JP2009549213 A JP 2009549213A JP 5244128 B2 JP5244128 B2 JP 5244128B2
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Japan
Prior art keywords
stress
layer
region
active semiconductor
sacrificial
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JP2009549213A
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Japanese (ja)
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JP2010527140A5 (https=
JP2010527140A (ja
Inventor
チダンバラオ、デュレセティ
ヘンソン、ウィリアム、ケー
リュー、ヤオチェン
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2009549213A 2007-02-12 2008-02-06 電界効果トランジスタ（ＦＥＴ）の製造方法、ｎ型およびｐ型電界効果トランジスタ Expired - Fee Related JP5244128B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/673,716 2007-02-12
US11/673,716 US7632724B2 (en) 2007-02-12 2007-02-12 Stressed SOI FET having tensile and compressive device regions
PCT/US2008/053152 WO2008100751A1 (en) 2007-02-12 2008-02-06 Stressed soi fet having tensile and compressive device regions

Publications (3)

Publication Number Publication Date
JP2010527140A JP2010527140A (ja) 2010-08-05
JP2010527140A5 JP2010527140A5 (https=) 2010-09-16
JP5244128B2 true JP5244128B2 (ja) 2013-07-24

Family

ID=39685098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009549213A Expired - Fee Related JP5244128B2 (ja) 2007-02-12 2008-02-06 電界効果トランジスタ（ＦＥＴ）の製造方法、ｎ型およびｐ型電界効果トランジスタ

Country Status (6)

Country Link
US (1) US7632724B2 (https=)
JP (1) JP5244128B2 (https=)
KR (1) KR20090121290A (https=)
BR (1) BRPI0807243A2 (https=)
TW (1) TW200901367A (https=)
WO (1) WO2008100751A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
JP5299268B2 (ja) * 2007-03-30 2013-09-25 富士通セミコンダクター株式会社 半導体集積回路装置およびその製造方法
US8169025B2 (en) * 2010-01-19 2012-05-01 International Business Machines Corporation Strained CMOS device, circuit and method of fabrication
US9406798B2 (en) 2010-08-27 2016-08-02 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
US8642430B2 (en) * 2012-04-09 2014-02-04 GlobalFoundries, Inc. Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
US9406508B2 (en) 2013-10-31 2016-08-02 Samsung Electronics Co., Ltd. Methods of forming a semiconductor layer including germanium with low defectivity
US9209301B1 (en) * 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
FR3029011B1 (fr) * 2014-11-25 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de mise en contrainte d'une zone de canal de transistor
US9768254B2 (en) 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
US9685510B2 (en) * 2015-09-10 2017-06-20 International Business Machines Corporation SiGe CMOS with tensely strained NFET and compressively strained PFET
WO2018125120A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Techniques for forming dual-strain fins for co-integrated n-mos and p-mos devices
US10263107B2 (en) * 2017-05-01 2019-04-16 The Regents Of The University Of California Strain gated transistors and method
US10770586B2 (en) * 2018-02-04 2020-09-08 Tower Semiconductor Ltd. Stressing structure with low hydrogen content layer over NiSi salicide
CN115376606B (zh) * 2022-08-11 2024-09-17 深圳市晶存科技股份有限公司 动态随机存储器通道测试方法、系统、装置及存储介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3951134B2 (ja) * 2003-07-24 2007-08-01 セイコーエプソン株式会社 半導体装置およびその製造方法
US20070126034A1 (en) * 2003-10-10 2007-06-07 Tokyo Institute Of Technology Semiconductor substrate, semiconductor device and process for producing semiconductor substrate
WO2005112129A1 (ja) * 2004-05-13 2005-11-24 Fujitsu Limited 半導体装置およびその製造方法、半導体基板の製造方法
US7227205B2 (en) 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
JP2006040958A (ja) * 2004-07-22 2006-02-09 Sumco Corp 歪みｓｏｉ基板
US7064045B2 (en) * 2004-08-30 2006-06-20 Miradia Inc. Laser based method and device for forming spacer structures for packaging optical reflection devices
KR100585157B1 (ko) 2004-09-07 2006-05-30 삼성전자주식회사 다수의 와이어 브릿지 채널을 구비한 모스 트랜지스터 및그 제조방법
US7125759B2 (en) * 2005-03-23 2006-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor-on-insulator (SOI) strained active areas
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
US7381649B2 (en) 2005-07-29 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for a multiple-gate FET device and a method for its fabrication
US20080191285A1 (en) * 2007-02-09 2008-08-14 Chih-Hsin Ko CMOS devices with schottky source and drain regions

Also Published As

Publication number Publication date
JP2010527140A (ja) 2010-08-05
WO2008100751A1 (en) 2008-08-21
BRPI0807243A2 (pt) 2014-06-17
US20080191281A1 (en) 2008-08-14
US7632724B2 (en) 2009-12-15
KR20090121290A (ko) 2009-11-25
TW200901367A (en) 2009-01-01

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